Display device

Abstract

A display device is provided and includes: a substrate; a circuit layer; and an element layer. The substrate may include a non-display area and a display area in which an emission area may be arranged. In order to transfer a data signal to a data line at a side edge of the display area, a bypass auxiliary line passing through a central portion of the display area is used to reduce a width of the sub-area. The horizontal portions of these bypass auxiliary lines may reach an edge portion of the display device under the other data lines in a form that intersects the other data lines. Accordingly, the shield auxiliary electrode may be disposed between the intersecting data line and the horizontal bypassing auxiliary line at a position where these other data lines overlap the horizontal bypassing auxiliary line in a plan view to reduce crosstalk between the horizontal bypassing auxiliary line and the data line.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2023-0113688, filed on August 29, 2023, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The disclosure relates to a display device. BACKGROUND

[0003] As information society advances, there are increasing demands for display devices that display images in various ways. For example, display devices are employed in various electronic devices such as smartphones, digital cameras, laptop computers, navigation devices, and smart TVs.

[0004] A display device can be a flat panel display device such as a liquid crystal display device, a field emission display device, and a light emitting display device. Examples of the light emitting display device can include an organic light emitting display device including an organic light emitting element, an inorganic light emitting display device including an inorganic light emitting element such as an inorganic semiconductor, and a micro light emitting display device including a micro light emitting element.

[0005] An organic light emitting display device displays images using organic light emitting elements each including a light emitting layer made of an organic light emitting material. As described above, the organic light emitting display device uses self-light emitting elements to implement image display, and thus can have relatively superior performance in power consumption, response speed, light emitting efficiency, brightness, and wide viewing angle, compared to other display devices.

[0006] A surface of a display device can be a display surface including a display area in which an image can be displayed and a non-display area that can be disposed at a periphery of the display area. An emission area that emits light having various brightnesses and colors can be arranged in the display area. SUMMARY

[0007] The present utility model aims to provide a display device that can include a light emitting element disposed in an emission area, a light emitting pixel driver electrically connected to the light emitting element, and a data line that transmits a data signal to the light emitting pixel driver.

[0008] In addition, the display device can further include a data supply line electrically connected between the data line and the display driving circuit to supply the data signal.

[0009] Since the data supply line can be disposed in the non-display area, as the display device becomes higher resolution or larger, the number and the extension length of the data supply line increase, so that the width of the non-display area can increase.

[0010] In view of the above, disclosed aspects provide a display device in which an increase rate of a width of a non-display area due to an arrangement of data supply lines can be reduced.

[0011] According to disclosed aspects, a display device can be provided that can include a substrate, a circuit layer disposed on the substrate, and an element layer disposed on the circuit layer. The substrate can include a main area including a display area in which an emission area can be disposed and a non-display area disposed around the display area, and a sub-area protruding from one side of the main area. The element layer can include light emitting elements respectively disposed in the emission area. The circuit layer can include light emitting pixel drivers respectively electrically connected to the light emitting elements, the light emitting pixel drivers can be arranged in a first direction and a second direction, data lines extending in the second direction and transmitting a data signal to the light emitting pixel drivers, first auxiliary lines extending in the first direction, and second auxiliary lines extending in the second direction and respectively paired with the data lines.

[0012] The first auxiliary lines can include a first bypass auxiliary line electrically connected to a first data line disposed adjacent to an edge of the substrate in the first direction among the data lines. The second auxiliary lines can include a second bypass auxiliary line electrically connected to the first bypass auxiliary line, the second bypass auxiliary line can be paired with a second data line spaced farther from the edge of the substrate in the first direction than the first data line among the data lines. The circuit layer can further include at least one shield auxiliary electrode superposed with an intersection area between the first bypass auxiliary line and at least one data line disposed between the second bypass auxiliary line and the first data line in the first direction.

[0013] The at least one shield auxiliary electrode can be disposed on a first insulating layer covering the first auxiliary lines. The data lines and the second auxiliary lines can be disposed on a second insulating layer covering the at least one shield auxiliary electrode. In a third direction in which the first insulating layer and the second insulating layer are stacked on each other, the at least one shield auxiliary electrode can be disposed between the at least one data line and the first bypass auxiliary line.

[0014] The at least one shield auxiliary electrode can extend in parallel with the first bypass auxiliary line, and can further be superposed with an intersection area between the first bypass auxiliary line and at least one second auxiliary line among the second auxiliary lines respectively paired with the at least one data line.

[0015] Each of the light emitting pixel drivers can include a first transistor electrically connected between a first node and a second node, a pixel capacitor electrically connected between a third node and a first power line that transmits a first power, a second transistor electrically connected between a data line and the first node, a third transistor electrically connected between the second node and the third node, a fourth transistor electrically connected between a gate initialization voltage line and the third node, a fifth transistor electrically connected between the first power line and the first node, a sixth transistor electrically connected between the second node and a fourth node, a seventh transistor electrically connected between the fourth node and an anode initialization voltage line that transmits an anode initialization voltage, and an eighth transistor electrically connected between a bias voltage line and the first node. The first node can be electrically connected to a first electrode of the first transistor. The second node can be electrically connected to a second electrode of the first transistor. The third node can be electrically connected to a gate electrode of the first transistor. The fourth node can be electrically connected to one of the light emitting elements. The first power line can extend in a second direction, can be arranged between adjacent first auxiliary lines in a first direction, and can be disposed on the second insulating layer. Among the at least one shield auxiliary electrode, two shield auxiliary electrodes adjacent in the first direction can be disposed adjacent to both sides of the first power line in the first direction.

[0016] The at least one shield auxiliary electrode can be electrically connected to the first power line.

[0017] The circuit layer can further include a first semiconductor layer disposed on the base, a first gate insulating layer covering the first semiconductor layer, a first gate conductive layer disposed on the first gate insulating layer, a second gate insulating layer covering the first gate conductive layer, a second gate conductive layer disposed on the second gate insulating layer, a first interlayer insulating layer covering the second gate conductive layer, a second semiconductor layer disposed on the first interlayer insulating layer, a third gate insulating layer covering the second semiconductor layer, a third gate conductive layer disposed on the third gate insulating layer, a second interlayer insulating layer covering the third gate conductive layer, a first source-drain conductive layer disposed on the second interlayer insulating layer, a first planarization layer covering the first source-drain conductive layer, a second source-drain conductive layer disposed on the first planarization layer, and a second planarization layer covering the second source-drain conductive layer. The first insulating layer can include the second interlayer insulating layer. The second insulating layer can include the first planarization layer.

[0018] The third gate conductive layer can include the first auxiliary line. The first source-drain conductive layer can include the at least one shield auxiliary electrode. The second source-drain conductive layer can include the data line, the second auxiliary line, and the first power line.

[0019] Each of the third gate conductive layer, the first source-drain conductive layer, and the second source-drain conductive layer has a multi-layer structure, which can include a main layer and at least one sub-layer disposed on at least one side of the main layer. The main layer can include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), copper (Cu), and combinations thereof, and the at least one sub-layer can include titanium (Ti).

[0020] The display device can further include a display driving circuit disposed in the sub-area to supply the data signal to the data line. The circuit layer can further include a data supply line extending from the display driving circuit to the display area to transmit the data signal to the data line. Among the data supply lines, a first data supply line transmitting the data signal of the first data line can be electrically connected to the second bypass auxiliary line. Among the data supply lines, a second data supply line transmitting the data signal of the second data line can be electrically connected (e.g., directly electrically connected) to the second data line.

[0021] The display device can further include a display driving circuit disposed in the sub-area. The circuit layer can further include a demultiplexing circuit disposed in the sub-area to output the data signal to the data line based on a data multiplexing signal supplied from the display driving circuit, and a data supply line electrically connected between the demultiplexing circuit and the data line to transmit the data signal to the data line. Among the data supply lines, a first data supply line transmitting the data signal of the first data line can be electrically connected to the first bypass auxiliary line. Among the data supply lines, a second data supply line transmitting the data signal of the second data line can be electrically connected (e.g., directly electrically connected) to the second data line.

[0022] According to disclosed aspects, a display device can be provided, the display device including a substrate, a circuit layer disposed on the substrate, and an element layer disposed on the circuit layer. The substrate can include a main area and a sub-area protruding from one side of the main area, the main area can include a display area in which an emission area can be disposed and a non-display area disposed around the display area, and the sub-area can protrude from one side of the main area. The element layer can include light emitting elements respectively disposed in the emission area. The circuit layer can include light emitting pixel drivers respectively electrically connected to the light emitting elements, the light emitting pixel drivers can be arranged in a first direction and a second direction, data lines extending in the second direction to transmit a data signal to the light emitting pixel drivers, first bypass auxiliary lines extending in the first direction and electrically connected to first data lines disposed adjacent to an edge of the substrate in the first direction among the data lines, second bypass auxiliary lines extending in the second direction and electrically connected to the first bypass auxiliary lines, the second bypass auxiliary lines can be paired with second data lines that can be spaced farther apart from the edge of the substrate in the first direction than the first data lines among the data lines, and at least one shield auxiliary electrode superposed with at least one data line intersecting the first bypass auxiliary line among the data lines.

[0023] The circuit layer can further include a first semiconductor layer disposed on the substrate, a first gate insulating layer covering the first semiconductor layer, a first gate conductive layer disposed on the first gate insulating layer, a second gate insulating layer covering the first gate conductive layer, a second gate conductive layer disposed on the second gate insulating layer, a first interlayer insulating layer covering the second gate conductive layer, a second semiconductor layer disposed on the first interlayer insulating layer, a third gate insulating layer covering the second semiconductor layer, a third gate conductive layer disposed on the third gate insulating layer, a second interlayer insulating layer covering the third gate conductive layer, a first source-drain conductive layer disposed on the second interlayer insulating layer, a first planarization layer covering the first source-drain conductive layer, a second source-drain conductive layer disposed on the first planarization layer, and a second planarization layer covering the second source-drain conductive layer. The third gate conductive layer can include the first bypass auxiliary lines. The first source-drain conductive layer can include the at least one shield auxiliary electrode. The second source-drain conductive layer can include the data lines and the second bypass auxiliary lines.

[0024] The at least one shield auxiliary electrode can extend in parallel with the first bypass auxiliary lines, and the at least one shield auxiliary electrode can be disposed between the at least one data line and the first bypass auxiliary lines in a third direction in which the second interlayer insulating layer and the first planarization layer are stacked on each other.

[0025] Each of the third gate conductive layer, the first source-drain conductive layer, and the second source-drain conductive layer has a multi-layer structure including a main layer and at least one sub-layer disposed on at least one side of the main layer. The main layer includes any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), copper (Cu), and combinations thereof. The at least one sub-layer can include titanium (Ti).

[0026] The display device can further include a display driving circuit disposed in the sub-area. The circuit layer can further include a demultiplexing circuit disposed in the sub-area to output data signals to the data lines based on data multiplexing signals supplied from the display driving circuit, and a data supply line electrically connected between the demultiplexing circuit and the data lines and transmitting the data signals to the data lines. Among the data supply lines, a first data supply line transmitting a data signal of a first data line can be electrically connected to the second bypass auxiliary line. Among the data supply lines, a second data supply line transmitting a data signal of a second data line can be electrically connected (e.g., directly electrically connected) to the second data line.

[0027] Each of the light emitting pixel drivers can include a first transistor electrically connected between a first node and a second node, a pixel capacitor electrically connected between a third node and a first power line transmitting a first power, a second transistor electrically connected between a data line and the first node, a third transistor electrically connected between the second node and the third node, a fourth transistor electrically connected between a gate initialization voltage line and the third node, a fifth transistor electrically connected between the first power line and the first node, a sixth transistor electrically connected between the second node and a fourth node, a seventh transistor electrically connected between the fourth node and an anode initialization voltage line transmitting an anode initialization voltage, and an eighth transistor electrically connected between a bias voltage line and the first node. The first node can be electrically connected to a first electrode of the first transistor. The second node can be electrically connected to a second electrode of the first transistor. The third node can be electrically connected to a gate electrode of the first transistor. The fourth node can be electrically connected to one of the light emitting elements. The at least one shield auxiliary electrode can be electrically connected to the first power line.

[0028] The display device according to an embodiment can include a substrate, a circuit layer, and an element layer. The circuit layer can include light emitting pixel drivers which can be respectively electrically connected to light emitting elements of the element layer and can be arranged in a first direction and a second direction, data lines which can extend in the second direction and transmit data signals to the light emitting pixel drivers, a first bypass auxiliary line which can extend in the first direction and can be electrically connected to first data lines among the data lines which are disposed adjacent to an edge of the substrate in the first direction, and a second bypass auxiliary line which can extend in the second direction, can be paired with second data lines among the data lines which are spaced farther apart from the edge of the substrate in the first direction than the first data lines, and can be electrically connected to the first bypass auxiliary line.

[0029] The circuit layer can further include data supply lines which are electrically connected between the data lines and a display driving circuit which supplies data signals. Among the data supply lines, a first data supply line which transmits a data signal of the first data line can be electrically connected to the first data line through the first bypass auxiliary line and the second bypass auxiliary line. Among the data supply lines, a second data supply line which transmits a data signal of the second data line can be electrically connected (e.g., directly electrically connected) to the second data line.

[0030] In this way, since the first data supply line does not extend to the first data line adjacent to the edge of the substrate, the extension length of the data supply line can be reduced. Accordingly, the increase rate of the width of a non-display area due to the disposition of the data supply line can be reduced.

[0031] According to an embodiment, the circuit layer can include at least one shield auxiliary electrode which overlaps at least one data line among the data lines which intersects the first bypass auxiliary line.

[0032] The at least one shield auxiliary electrode can overlap an intersection region between the at least one data line and the first bypass auxiliary line.

[0033] The at least one shield auxiliary electrode can be disposed between the at least one data line and the first bypass auxiliary line in a third direction along which an insulating layer can be stacked.

[0034] In this way, the influence of the data signal of the first bypass auxiliary line on the data signal of the at least one data line can be blocked by the at least one shield auxiliary electrode. Accordingly, since the data signal of the at least one data line can be stably maintained, degradation of display quality due to the disposition of the first bypass auxiliary line can be prevented.

[0035] However, effects according to disclosed embodiments can not be limited to the above-illustrated effects, and various other effects can be incorporated herein. BRIEF DESCRIPTION OF DRAWINGS

[0036] The above and other aspects and features of the present disclosure will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings, which illustrate:

[0037] Figure 1 is a perspective view illustrating a display device according to an embodiment;

[0038] Figure 2 is a plan view illustrating Figure 1 a display device;

[0039] Figure 3 is a schematic cross-sectional view taken along line A-A' of Figure 2

[0040] Figure 4 is a schematic layout view illustrating Figure 2 part B thereof;

[0041] Figure 5 is a schematic view illustrating an equivalent circuit of a light emitting pixel driver of Figure 4 according to an embodiment;

[0042] Figure 6 is a schematic cross-sectional view illustrating a first transistor, a second transistor, a fourth transistor, a sixth transistor, and a light emitting element illustrated in Figure 5

[0043] Figure 7 is an enlarged view illustrating Figure 6 part C thereof;

[0044] Figure 8 is an enlarged view illustrating Figure 6 part D thereof;

[0045] Figure 9 is an enlarged view illustrating Figure 6 part E thereof;

[0046] Figure 10 is a plan view illustrating a substrate of Figure 3 according to an embodiment;

[0047] Figure 11 is a schematic layout view illustrating Figure 10 part F thereof according to an embodiment;

[0048] Figure 12 is a schematic cross-sectional view taken along line G-G' of Figure 11

[0049] Figure 13 is a schematic layout view illustrating Figure 10 part F thereof according to an embodiment;

[0050] Figure 14 is​​​Figure 13 schematic diagram of an equivalent circuit of the demultiplexing circuit of

[0051] Figure 15 is a timing chart showing a data multiplex signal, a first demultiplex control signal, and a second demultiplex control signal of the demultiplex input line shown in Figure 14

[0052] Figure 16 is a plan view of a portion H of the Figure 13

[0053] Figure 17 is a schematic cross-sectional view taken along line I-I' of Figure 16 DETAILED DESCRIPTION

[0054] In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the present inventive subject matter. As used herein, the term "embodiment" and "implementation" are interchangeable terms that refer to non-limiting examples of the apparatus or methods disclosed herein. It will be apparent, however, that various embodiments can be practiced without these specific details, or with one or more equivalent arrangements. In other instances, well-known structures and functions have not been described in detail in order to avoid obscuring the subject matter of this disclosure. Also, various embodiments need not always include the same feature, component, module, layer, film, pane, region, and / or aspect, etc. (hereinafter, individually or collectively referred to as "element") as other embodiments, unless otherwise specified.

[0055] Unless otherwise noted, embodiments shown are to be understood to provide features of the present inventive subject matter. Thus, features, components, modules, layers, films, panes, regions, and / or aspects, etc. (hereinafter, individually or collectively referred to as "elements") of various embodiments can be otherwise combined, separated, interchanged, and / or rearranged without departing from the concept of the present inventive subject matter, unless otherwise specified.

[0056] The use of cross-hatching and / or shading in the drawings is generally provided to illustrate the boundaries, of the elements shown. As such, neither cross-hatching nor shading is intended to convey or dictate any particular material, material property, dimension, ratio, commonality of elements between the illustrated elements, and / or any other characteristic, attribute, property, or the like, to inferences drawn from the description, or the specification as a whole. Moreover, the size and relative sizes of the elements in the drawings are intended to be illustrative of particular embodiments and are not necessarily in accordance with the scale of the actual drawings. When an embodiment can be implemented differently, a specific process sequence can be performed differently from the order described. For example, two consecutively described processes can be performed substantially simultaneously or in the opposite order to the described order. Additionally, the same reference numbers and / or reference designations can represent the same elements or features.

[0057] ​​​When an element or layer is referred to as being “on”, “connected to”, or “coupled to” another element or layer, it can be directly on, connected, or coupled to the other element or layer, or intervening elements or layers can be present. In contrast, when an element or layer is referred to as being “directly on”, “directly connected to”, or “directly coupled to” another element or layer, there are no intervening elements or layers present. In this regard, the term “connected” can refer to physical or electrical and / or fluid connection, with or without intervening elements. Also, the X-axis, Y-axis and Z-axis or first direction DR1, second direction DR2 and third direction DR3 are not limited to three axes of a rectangular coordinate system such as the x-axis, the y-axis and the z-axis, and can be interpreted in a broader sense. For example, the first direction DR1, the second direction DR2 and the third direction DR3 can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0058] For purposes of the present disclosure, the term “at least one of A and B” (and “at least one of X, Y, and Z,” or “at least one of A, B, and C”) can be interpreted to mean A or B or both A and B (or X or Y or both X and Y, or A or B or both A and B or X or Y or both X and Y or any combination thereof). Further, the term “at least one of A and B” (and “at least one of X, Y, and Z,” or “at least one of A, B, and C”) can be interpreted to mean only A, only B, or any combination of A and B (or X, Y, or any combination of X and Y, or A, B, or any combination of A and B or X, Y, or any combination of X and Y). As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0059] Although the terms “first,” “second,” etc. can be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the disclosure.

[0060] Spatially relative terms such as “beneath”, “below”, “lower”, “under”, “above”, “upper”, “on”, “directly on”, “side” (e.g., as in “sidewall”), and the like, can be used herein for ease of description to describe one element’s or feature’s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0061] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, to the extent that the terms "comprise," "have," "contain," and / or "include" and / or their derivatives are used herein, such terms are intended to be inclusive in a manner similar to the term "comprising," as an alternative to the term "consisting only of." It is also noted that the terms "substantial," "approximately," and other similar terms, as used herein, are used in a relative sense and not in an absolute sense. Thus, they are used to indicate that a value, calculation, and / or provided value is not exact, but is nonetheless desired to be as close as possible to the intended value.

[0062] Various embodiments are described herein with reference to cross-sectional and / or exploded illustrations that are schematic illustrations of embodiments (and intermediate structures) of embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments disclosed herein should not necessarily be construed as limited to the particular illustrated shapes of regions, unless otherwise explicitly defined or implied by context. In this manner, regions illustrated in the figures can be schematic in nature and the shapes of the regions as disclosed herein can not reflect actual shapes of the regions and, as such, are not intended to limit the scope of embodiments to the particular illustrated shapes of regions.

[0063] Unless otherwise defined or implied herein, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0064] In the following, embodiments will be described with reference to the drawings.

[0065] Figure 1 is a perspective view showing a display device according to an embodiment. Figure 2 is a plan view showing Figure 1 a display device of Figure 3 is a schematic cross-sectional view taken along line A-A' of Figure 2

[0066] Reference is made to Figure 1 and Figure 2 ​The display device 100 is a device for displaying moving or still images. The display device 100 can be used as a display screen for various devices such as televisions, laptops, monitors, billboards, and Internet of Things (IoT) devices, as well as portable electronic devices such as mobile phones, smartphones, tablet PCs, smartwatches, watch phones, mobile communication terminals, e-notebooks, e-book readers, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs).

[0067] Display device 100 may be a light-emitting display device, such as an organic light-emitting display using organic light-emitting diodes, a quantum dot light-emitting display including a quantum dot light-emitting layer, an inorganic light-emitting display including inorganic semiconductors, and a micro light-emitting display using micro or nano light-emitting diodes (LEDs). In the following description, it is assumed that display device 100 is an organic light-emitting display device. However, the disclosure is not limited to this, and display devices including organic insulating materials, organic light-emitting materials, and metallic materials may be applied.

[0068] The display device 100 may be formed to be generally flat, but is not limited thereto. For example, the display device 100 may include curved portions formed at the left and right ends and having a constant or varying curvature. The display device 100 may be formed flexibly, such that the display device 100 can be bent, folded, rolled or rolled.

[0069] like Figure 1 , Figure 2 and Figure 3 As shown, the display device 100 may include a substrate 110.

[0070] The substrate 110 may include a main region MA corresponding to the display surface of the display device 100 and a sub-region SBA protruding from one side of the main region MA.

[0071] like Figure 2 As shown, the main region MA may include a display region DA located in the center of the main region MA and a non-display region NDA located around the display region DA.

[0072] In the planar view, the display area DA can be formed in a rectangular shape, having a short side in a first direction DR1 and a long side in a second direction DR2 that intersects the first direction DR1. The corner where the short side in the first direction DR1 and the long side in the second direction DR2 meet can be rounded (rounded) to have a certain curvature, or it can be a right angle. The planar shape of the display area DA is not limited to a rectangular shape, and can be formed in other polygonal shapes, circular shapes, or elliptical shapes.

[0073] A non-display area NDA can be disposed at an edge of the main area MA to surround the display area DA.

[0074] The sub-area SBA can be an area protruding from one side of the non-display area NDA of the main area MA in the second direction DR2.

[0075] Since a portion of the sub-area SBA can be deformed to be curved, another portion of the sub-area SBA can be disposed on a rear surface of the display device 100.

[0076] Figure 2 And Figure 3 The display device 100 is shown with a portion of the sub-area SBA in a curved state.

[0077] Referring to Figure 3 , the display device 100 according to an embodiment includes a substrate 110, a circuit layer 120 disposed on the substrate 110, and an element layer 130 disposed on the circuit layer 120.

[0078] The display device 100 according to an embodiment can further include an encapsulation layer 140 disposed on the element layer 130 and a touch sensor layer 150 disposed on the encapsulation layer 140.

[0079] In addition, the display device 100 according to an embodiment can further include a polarization layer 160 disposed on the touch sensor layer 150 to reduce reflection of external light.

[0080] The substrate 110 can be formed of an insulating material such as a polymer resin. For example, the substrate 110 can be formed of polyimide. The substrate 110 can be a flexible substrate that can be bent, folded, or rolled.

[0081] The substrate 110 can be formed of an insulating material such as glass or the like.

[0082] The substrate 110 can include a main area MA and a sub-area SBA. The main area MA can include a display area DA and a non-display area NDA.

[0083] Figure 4 is a schematic layout view showing Figure 2 part B of FIG. 1A.

[0084] Referring to Figure 4 , the display area DA of the display device 100 according to an embodiment can include an emission area EA. The display area DA can further include a non-emission area disposed in a gap between the emission areas EA.

[0085] Light emitting pixel drivers EPD (or pixel circuits) corresponding to the emission areas EA, respectively, can be arranged in parallel with each other in the display area DA in the first direction DR1 and the second direction DR2. The light emitting pixel drivers EPD can be electrically connected to the light emitting elements LE of the element layer 130 respectively provided in the emission areas EA, respectively (see FIG. 2). Figure 5

[0086] The emission areas EA can have a rhombic planar shape or a rectangular planar shape. However, this can be merely an example, and the planar shape of the emission areas EA according to the embodiment can not be limited to the planar shape shown in Figure 4 In a plan view, the emission areas EA can have a polygonal shape such as a square, a pentagon, a hexagon, or the like, or can have a circular shape or an elliptical shape including curved edges.

[0087] The emission areas EA can include a first emission area EA1 emitting light of a first color in a waveband, a second emission area EA2 emitting light of a second color in a waveband lower than the waveband of the first color, and a third emission area EA3 emitting light of a third color in a waveband lower than the waveband of the second color.

[0088] For example, the first color can be red having a waveband in the range of approximately 600 nm to approximately 750 nm. The second color can be green having a waveband in the range of approximately 480 nm to approximately 560 nm. The third color can be blue having a waveband in the range of approximately 370 nm to approximately 460 nm.

[0089] The first emission areas EA1 and the third emission areas EA3 can be alternately arranged in the first direction DR1.

[0090] The second emission areas EA2 can be arranged side by side in at least one of the first direction DR1 and the second direction DR2.

[0091] The second emission areas EA2 can be adjacent to the first emission areas EA1 and the third emission areas EA3 in diagonal directions DR4 and DR5 intersecting the first direction DR1 and the second direction DR2.

[0092] Pixels PX displaying their own brightness and color can be provided by the first emission areas EA1, the second emission areas EA2, and the third emission areas EA3 adjacent to each other among the emission areas EA.

[0093] In other words, the pixels PX can be basic units for displaying various colors including white in a certain brightness.

[0094] ​Each of the pixels PX can include at least one first emission area EA1, at least one second emission area EA2, and at least one third emission area EA3, which can be adjacent to each other. Accordingly, each of the pixels PX can display various colors by a mixture of light emitted from the first emission area EA1, the second emission area EA2, and the third emission area EA3, which can be adjacent to each other.

[0095] Figure 5 is a schematic view of an equivalent circuit of a light emitting pixel driver according to an embodiment. Figure 4

[0096] Referring to Figure 5 , one of the light emitting elements LE of the element layer 130 can be electrically connected between one of the light emitting pixel drivers EPD of the circuit layer 120 and the second power ELVSS.

[0097] The anode electrode 131 (see Figure 6 ) of the light emitting element LE can be electrically connected to the light emitting pixel driver EPD, and the cathode electrode 134 (see Figure 6 ) of the light emitting element LE can be applied with the second power ELVSS lower than the first power ELVDD.

[0098] The capacitor Cel electrically connected in parallel with the light emitting element LE refers to a parasitic capacitance between the anode electrode 131 and the cathode electrode 134.

[0099] The circuit layer 120 can further include a first power line VDL for transmitting the first power ELVDD, a gate initialization voltage line VGIL for transmitting a gate initialization voltage VGINT, an anode initialization voltage line VAIL for transmitting an anode initialization voltage VAINT, and a bias voltage line VBL for transmitting a bias voltage VBS.

[0100] The circuit layer 120 can further include a scan write line GWL for transmitting a scan write signal GW, a scan initialization line GIL for transmitting a scan initialization signal GI, an emission control line ECL for transmitting an emission control signal EC, a gate control line GCL for transmitting a gate control signal GC, and a bias control line GBL for transmitting a bias control signal GB.

[0101] One light emitting pixel driver EPD of the circuit layer 120 can include a first transistor T1 configured to generate a driving current for driving the light emitting element LE, two or more transistors T2 to T8 electrically connected to the first transistor T1, and at least one first pixel capacitor PC1.

[0102] The first transistor T1 can be electrically connected in series with the light emitting element LE between the first power ELVDD and the second power ELVSS.​

[0103] The first transistor T1 can be electrically connected between a first node N1 and a second node N2. The first node N1 can be electrically connected to a first electrode (e.g., a source electrode) of the first transistor T1. The second node N2 can be electrically connected to a second electrode (e.g., a drain electrode) of the first transistor T1.

[0104] In other words, the first electrode (e.g., the source electrode) of the first transistor T1 can be electrically connected to the first power line VDL through the fifth transistor T5. Also, the second electrode (e.g., the drain electrode) of the first transistor T1 can be electrically connected to the anode electrode 131 of the light emitting element LE through the sixth transistor T6.

[0105] The first pixel capacitor PC1 can be electrically connected between the first power line VDL and a third node N3. The third node N3 can be electrically connected to a gate electrode of the first transistor T1.

[0106] The gate electrode of the first transistor T1 can be electrically connected to the first power line VDL through the first pixel capacitor PC1.

[0107] Accordingly, the potential of the gate electrode of the first transistor T1 can be maintained at the voltage charged in the first power line VDL.

[0108] The second transistor T2 can be electrically connected between a data line DL and the first node N1.

[0109] In other words, the second transistor T2 can be electrically connected between the first electrode of the first transistor T1 and the data line DL. The second transistor T2 can be turned on by a scan write signal GW of a scan write line GWL.

[0110] The first electrode of the first transistor T1 can be electrically connected to the data line DL through the second transistor T2.

[0111] The fifth transistor T5 can be electrically connected between the first node N1 and the first power line VDL.

[0112] The sixth transistor T6 can be electrically connected between the second node N2 and a fourth node N4. The fourth node N4 can be electrically connected to the anode electrode 131 of the light emitting element LE.

[0113] The fifth transistor T5 can be electrically connected between the first electrode of the first transistor T1 and the first power line VDL.

[0114] The sixth transistor T6 can be electrically connected between the second electrode of the first transistor T1 and the anode electrode 131 of the light emitting element LE.

[0115] The fifth transistor T5 and the sixth transistor T6 can be turned on by an emission control signal EC of an emission control line ECL.

[0116] In a case where the data signal Vdata of the data line DL is transmitted to the first electrode of the first transistor T1 through the turned-on second transistor T2, a voltage difference between the gate electrode of the first transistor T1 and the first electrode of the first transistor T1 can be a voltage difference between the first power ELVDD and the data signal Vdata.

[0117] In a case where the voltage difference between the gate electrode of the first transistor T1 and the first electrode of the first transistor T1 (i.e., a gate-to-source voltage difference) becomes equal to or greater than a threshold voltage, the first transistor T1 can be turned on, thereby generating a drain-source current corresponding to the data signal Vdata in the first transistor T1.

[0118] In a case where the fifth transistor T5 and the sixth transistor T6 are turned on, the first transistor T1 can be electrically connected in series with the light emitting element LE between the first power line VDL and the second power line VSL. Accordingly, the drain-source current of the first transistor T1 corresponding to the data signal Vdata can be supplied as a driving current of the light emitting element LE.

[0119] Accordingly, the light emitting element LE can emit light having a luminance corresponding to the data signal Vdata.

[0120] The third transistor T3 can be electrically connected between the second node N2 and the third node N3. The third transistor T3 can be electrically connected between the gate electrode of the first transistor T1 and the second electrode of the first transistor T1. The third transistor T3 can be turned on by a gate control signal GC of a gate control line GCL.

[0121] By the turned-on third transistor T3, a voltage difference between the second node N2 and the third node N3 can be initialized.

[0122] The fourth transistor T4 can be electrically connected between a gate initialization voltage line VGIL and the third node N3. The fourth transistor T4 can be electrically connected between the gate electrode of the first transistor T1 and the gate initialization voltage line VGIL. The fourth transistor T4 can be turned on by a scan initialization signal GI of a scan initialization line GIL.

[0123] The potential of the third node N3 can be initialized by the turned-on fourth transistor T4.

[0124] The third transistor T3 and the fourth transistor T4 can be provided as N-type MOSFETs.

[0125] The seventh transistor T7 can be electrically connected between the fourth node N4 and the anode initialization voltage line VAIL. The seventh transistor T7 can be electrically connected between the anode electrode 131 of the light emitting element LE and the anode initialization voltage line VAIL. The seventh transistor T7 can be turned on by the bias control signal GB of the bias control line GBL.

[0126] The potential of the fourth node N4 can be initialized by the turned-on seventh transistor T7.

[0127] The eighth transistor T8 can be electrically connected between the first node N1 and the bias voltage line VBL. The eighth transistor T8 can be electrically connected between the first electrode of the first transistor T1 and the bias voltage line VBL. The eighth transistor T8 can be turned on by the bias control signal GB of the bias control line GBL.

[0128] The potential of the first node N1 can be initialized by the turned-on eighth transistor T8.

[0129] Among the first to eighth transistors T1 to T8, each of the transistors T1, T2, and T5 to T8 other than the third and fourth transistors T3 and T4 can be implemented as a P-type MOSFET.

[0130] When each of the third and fourth transistors T3 and T4 among the first to eighth transistors T1 to T8 included in the light emitting pixel driver EPD can be implemented as an N-type MOSFET, each of the remaining transistors T1, T2, and T5 to T8 other than the two transistors can be implemented as a P-type MOSFET.

[0131] Accordingly, according to an embodiment, the circuit layer 120 can include a first semiconductor layer and a second semiconductor layer.

[0132] The first semiconductor layer can include a channel portion, a first electrode portion, and a second electrode portion of each of the first to eighth transistors T1 to T8. In each of the first to eighth transistors T1 to T8, the channel portion can be superposed with the gate electrode. Further, in each of the first to eighth transistors T1 to T8, the first and second electrode portions can be electrically connected to both ends of the channel portion. The first electrode portion can become the first electrode, and the second electrode portion can become the second electrode.

[0133] The second semiconductor layer can include a channel portion, a first electrode portion, and a second electrode portion of each of the third transistor T3 and the fourth transistor T4. In each of the third transistor T3 and the fourth transistor T4, the channel portion can be disposed between the first gate electrode and the second gate electrode stacked with each other, and can be stacked with the first gate electrode and the second gate electrode. In each of the third transistor T3 and the fourth transistor T4, the first electrode portion and the second electrode portion can be electrically connected to both ends of the channel portion. The first electrode portion can become the first electrode, and the second electrode portion can become the second electrode.

[0134] Figure 6 is a schematic cross-sectional view illustrating Figure 5 the first transistor, the second transistor, the fourth transistor, the sixth transistor, and the light emitting element shown in FIG. 1A. Figure 7 is an enlarged view of a portion C of Figure 6 FIG. 1B. Figure 8 is an enlarged view of a portion D of Figure 6 FIG. 1B. Figure 9 is an enlarged view of a portion E of Figure 6 FIG. 1B.

[0135] Referring to Figure 6 , the display device 100 according to an embodiment can include a substrate 110, a circuit layer 120 on the substrate 110, an element layer 130 on the circuit layer 120, and an encapsulation layer 140 on the element layer 130.

[0136] According to an embodiment, the circuit layer 120 can include a first semiconductor layer CH1, S1, D1, CH2, S2, D2, CH6, S6, and D6 disposed on the substrate 110, a first gate insulating layer 122 covering the first semiconductor layer, first gate conductive layers G1, G2, and G6 disposed on the first gate insulating layer 122, a second gate insulating layer 123 covering the first gate conductive layers, second gate conductive layers CPE and LB2 disposed on the second gate insulating layer 123, a first interlayer insulating layer 124 covering the second gate conductive layers, a second semiconductor layer CH4, S4, and D4 disposed on the first interlayer insulating layer 124, a third gate insulating layer 125 covering the second semiconductor layer, a third gate conductive layer G4 disposed on the third gate insulating layer 125, a second interlayer insulating layer 126 covering the third gate conductive layer, first source-drain conductive layers ANDE1, VGIL, GCNE, DCE disposed on the second interlayer insulating layer 126, a first planarization layer 127 covering the first source-drain conductive layers, second source-drain conductive layers DL and ANDE2 disposed on the first planarization layer 127, and a second planarization layer 128 covering the second source-drain conductive layers.

[0137] According to an embodiment, the circuit layer 120 can further include a buffer layer 121 covering the substrate 110. The first semiconductor layer can be disposed on the buffer layer 121. The buffer layer 121 can cover the first light blocking layer LB1 on the substrate 110.

[0138] The first light blocking layer LB1 can overlap the channel portion CH1 of the first transistor T1.

[0139] Referring to Figure 7 , Figure 8 and Figure 9 , each of the third gate conductive layer GCDL3 (G4 in Figure 6 ), the first source-drain conductive layer SDCDL1 (ANDE1, VGIL, GCNE, and DCE in Figure 6 ), and the second source-drain conductive layer SDCDL2 (DL and ANDE2 in Figure 6 ) on the third gate insulating layer 125, the second interlayer insulating layer 126, and the first planarization layer 127, respectively, can have a multi-layer structure including a main layer (MNL1 in Figure 7 , MNL2 in Figure 8 , and MNL3 in Figure 9 ) and at least one sub-layer (SBL1 in Figure 7 , SBL21 and SBL22 in Figure 8 , and SBL31 and SBL32 in Figure 9 ) disposed on at least one of both sides of the main layer.

[0140] The main layer (MNL1 in Figure 7 , MNL2 in Figure 8 , and MNL3 in Figure 9 ) can include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), copper (Cu), and combinations thereof.

[0141] The at least one sub-layer (SBL1 in Figure 7 , SBL21 and SBL22 in Figure 8 , and SBL31 and SBL32 in Figure 9 ) can include titanium (Ti).

[0142] For example, as shown in Figure 7 , the third gate conductive layer GCDL3 on the third gate insulating layer 125 can have a two-layer structure including a first main layer MNL1 and a first sub-layer SBL1 on the first main layer MNL1. For example, the third gate conductive layer GCDL3 can have a two-layer structure of Ti / Al.

[0143] As shown in Figure 8As shown, the first source-drain conductive layer SDCDL1 on the second interlayer insulating layer 126 can have a three-layer structure including a second main layer MNL2 and a second sublayer SBL21 and a third sublayer SBL22 disposed on both sides of the second main layer MNL2. For example, the first source-drain conductive layer SDCDL1 on the second interlayer insulating layer 126 can have a Ti / Al / Ti three-layer structure.

[0144] like Figure 9 As shown, the second source-drain conductive layer SDCDL2 on the first planarization layer 127 can have a three-layer structure including a third main layer MNL3 and a fourth sublayer SBL31 and a fifth sublayer SBL32 disposed on both sides of the third main layer MNL3. For example, the second source-drain conductive layer SDCDL2 on the first planarization layer 127 can have a Ti / Al / Ti three-layer structure.

[0145] As referenced above Figure 4 and Figure 5 The circuit layer 120 may include a light-emitting pixel driver EPD electrically connected to a light-emitting element LE disposed in the emission region EA, and wiring for transmitting various signals and voltages to the light-emitting pixel driver EPD. The light-emitting pixel driver EPD may include a first transistor T1 and two or more transistors T2 to T8 electrically connected to the first transistor T1.

[0146] like Figure 6 As shown, according to an embodiment, the first transistor T1 may include a channel portion CH1, a source portion S1, and a drain portion D1 disposed on a substrate 110 in a first semiconductor layer, and a gate electrode G1 disposed on a first gate insulating layer 122 covering the first semiconductor layer in a first gate conductive layer. The source portion S1 and the drain portion D1 may be electrically connected to the two ends of the channel portion CH1. Compared with the channel portion CH1, the source portion S1 and the drain portion D1 may be doped at a higher concentration. The gate electrode G1 may be stacked with the channel portion CH1.

[0147] Similarly, the second transistor T2 may include a channel portion CH2, a source portion S2, and a drain portion D2 disposed on the substrate 110 in the first semiconductor layer, and a gate electrode G2 disposed on the first gate insulating layer 122 in the first gate conductive layer.

[0148] In addition, the sixth transistor T6 may include a channel portion CH6, a source portion S6, and a drain portion D6 disposed on the substrate 110 in the first semiconductor layer, and a gate electrode G6 disposed on the first gate insulating layer 122 in the first gate conductive layer.

[0149] The source portion S2 of the second transistor T2 can be electrically connected to the data line DL through the data connection electrode DCE.

[0150] The data connection electrode DCE can be disposed in the first source-drain conductive layer on the second interlayer insulating layer 126, and can be electrically connected to the source portion S2 of the second transistor T2 through the data auxiliary connection hole DCAH that penetrates the second interlayer insulating layer 126, the third gate insulating layer 125, the first interlayer insulating layer 124, the second gate insulating layer 123, and the first gate insulating layer 122.

[0151] The data line DL can be disposed in the second source-drain conductive layer on the first planarization layer 127, and can be electrically connected to the data connection electrode DCE through the data connection hole DCH that penetrates the first planarization layer 127.

[0152] The drain portion D2 of the second transistor T2 can be electrically connected to the source portion S1 of the first transistor T1.

[0153] The drain portion D1 of the first transistor T1 can be electrically connected to the source portion S6 of the sixth transistor T6.

[0154] The drain portion D6 of the sixth transistor T6 can be electrically connected to the anode electrode 131 through the first anode connection electrode ANDE1 and the second anode connection electrode ANDE2.

[0155] The first anode connection electrode ANDE1 can be disposed in the first source-drain conductive layer, can be disposed on the second interlayer insulating layer 126, and can be electrically connected to the drain portion D6 of the sixth transistor T6 through the first anode contact hole ANCT1 that penetrates the second interlayer insulating layer 126, the third gate insulating layer 125, the first interlayer insulating layer 124, the second gate insulating layer 123, and the first gate insulating layer 122.

[0156] The second anode connection electrode ANDE2 can be disposed in the second source-drain conductive layer, can be disposed on the first planarization layer 127, and can be electrically connected to the first anode connection electrode ANDE1 through the second anode contact hole ANCT2 that penetrates the first planarization layer 127.

[0157] The anode electrode 131 can be disposed on the second planarization layer 128, and can be electrically connected to the second anode connection electrode ANDE2 through the third anode contact hole ANCT3 that penetrates the second planarization layer 128.

[0158] According to an embodiment, since the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 have substantially the same structure as the first transistor T1, the second transistor T2, and the sixth transistor T6, redundant descriptions can be omitted below.

[0159] The first gate conductive layer on the first gate insulating layer 122 can include not only a gate electrode of each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8, but also a scan write line GWL electrically connected to the gate electrode G2 of the second transistor T2 and a bias control line GBL electrically connected to the gate electrode of the seventh transistor T7 and the gate electrode of the eighth transistor T8.

[0160] The first pixel capacitor PC1 can be disposed in a stacked region between the gate electrode G1 of the first transistor T1 and a pixel capacitor electrode CPE.

[0161] The pixel capacitor electrode CPE can be disposed in the second gate conductive layer on the second gate insulating layer 123.

[0162] According to an embodiment, in order to be disposed in a type different from those of the first transistor T1, the second transistor T2, and the sixth transistor T6, the fourth transistor T4 can include a channel portion CH4 disposed in a second semiconductor layer on the first interlayer insulating layer 124, a source portion S4 and a drain portion D4, and a gate electrode G4 disposed in a third gate conductive layer on the third gate insulating layer 125.

[0163] The channel portion CH4 of the fourth transistor T4 can be stacked with the second light blocking layer LB2.

[0164] The second light blocking layer LB2 can be disposed in the second gate conductive layer on the second gate insulating layer 123.

[0165] According to an embodiment, since the third transistor T3 has substantially the same structure as that of the fourth transistor T4, redundant descriptions will be omitted below.

[0166] The first source-drain conductive layer on the second interlayer insulating layer 126 can further include a gate initialization voltage line VGIL, a gate connection electrode GCNE, and a data connection electrode DCE.

[0167] The gate initialization voltage line VGIL can be electrically connected to the source portion S4 of the fourth transistor T4 through an initialization connection hole VICH.

[0168] The gate connection electrode GCNE can be electrically connected to the drain portion D4 of the fourth transistor T4 through a first gate connection hole GCH1, and can be electrically connected to the gate electrode G1 of the first transistor T1 through a second gate connection hole GCH2.

[0169] The data line DL can be disposed in the second source-drain conductive layer on the first planarization layer 127.

[0170] The element layer 130 can include light emitting elements LE disposed on the second planarization layer 128 and respectively corresponding to the emission areas EA.

[0171] Each of the light emitting elements LE can include an anode electrode 131 and a cathode electrode 134 facing each other and a light emitting layer 133 disposed between the anode electrode 131 and the cathode electrode 134.

[0172] Each of the light emitting elements LE can further include a first common layer disposed between the anode electrode 131 and the light emitting layer 133 and a second common layer disposed between the light emitting layer 133 and the cathode electrode 134.

[0173] The element layer 130 can include the anode electrode 131 respectively corresponding to the emission areas EA, a pixel definition layer 132 corresponding to the non-emission areas between the emission areas EA and covering edges of the anode electrode 131, and the cathode electrode 134 disposed on the light emitting layer 133 and the pixel definition layer 132.

[0174] The anode electrode 131 can be disposed in each of the emission areas EA and can be electrically connected to one light emitting pixel driver EPD of the circuit layer 120. The anode electrode 131 can be referred to as a pixel electrode.

[0175] The anode electrode 131 can be electrically connected to the second anode connection electrode ANDE2 through a third anode contact hole ANCT3 penetrating the second planarization layer 128.

[0176] The light emitting layer 133 can be formed of an organic light emitting material that converts an electron-hole pair into light.

[0177] The cathode electrode 134 can be disposed in a display area DA including the emission areas EA. The cathode electrode 134 can be electrically connected to a second power supply line VSSPL (see Figure 11 ) that transmits the second electric power ELVSS. The cathode electrode 134 can be referred to as a common electrode.

[0178] The encapsulation layer 140 can be disposed on the circuit layer 120 and cover the element layer 130.

[0179] As an example, the encapsulation layer 140 can include a first encapsulation layer disposed on the element layer 130 and made of an inorganic insulating material, a second encapsulation layer disposed on the first encapsulation layer, laminated with the element layer 130, and made of an organic insulating material, and a third encapsulation layer disposed on the first encapsulation layer, covering the second encapsulation layer, and made of an inorganic insulating material.

[0180] Figure 10 is a plan view illustrating a substrate according to an embodiment. Figure 3

[0181] Referring to​Figure 10 The base 110 of the display device 100 according to an embodiment includes a main area MA corresponding to a display surface and a sub area SBA protruding from one side of the main area MA.

[0182] The main area MA can include a display area DA disposed at a substantial portion of the center and a non-display area NDA disposed at a periphery to surround the display area DA.

[0183] The display area DA can include a detour area DEA disposed at a side adjacent to the sub area SBA and a general area GA disposed in a remaining area other than the detour area DEA.

[0184] The detour area DEA can include a detour middle area MDDA disposed at the center in the first direction DR1, a first detour side area SDA1 parallel to the detour middle area MDDA in the first direction DR1 and in contact with the non-display area NDA, and a second detour side area SDA2 disposed between the detour middle area MDDA and the first detour side area SDA1.

[0185] The first detour side area SDA1 can be disposed adjacent to a bending corner of the base 110, as compared to the detour middle area MDDA and the second detour side area SDA2.

[0186] The first detour side area SDA1 and the second detour side area SDA2 can be disposed between the detour middle area MDDA and the non-display area NDA on both sides of the detour middle area MDDA in the first direction DR1.

[0187] The general area GA can include a general middle area GMA extending to the detour middle area MDDA of the detour area DEA in the second direction DR2, a first general side area GSA1 extending to the first detour side area SDA1 of the detour area DEA in the second direction DR2, and a second general side area GSA2 extending to the second detour side area SDA2 of the detour area DEA in the second direction DR2.

[0188] The non-display area NDA can include a gate driver circuit area GRDA in which a gate driver circuit can be disposed.

[0189] The gate driver circuit area GRDA can be disposed in a portion of the non-display area NDA adjacent to at least one side of the display area DA in the first direction DR1.

[0190] The gate driver circuit of the gate driver circuit area GRDA can sequentially transmit a gate signal to a gate line. Here, the gate line can include a scan write line GWL (see Figure 5 ) that transmits a scan write signal GW (see Figure 5), transmit scan initialization signal GI (see Figure 5 The scan initialization line GIL (see) Figure 5 ), transmit gate control signal GC (see Figure 5 The gate control line GCL (see) Figure 5 ), transmission bias control signal GB (see Figure 5 The bias control line GBL (see) Figure 5 ) and transmit control signals EC (see Figure 5 The transmit control line ECL (see) Figure 1 ).

[0191] The sub-region SBA may include a curved region BA that can be deformed into a curved shape, a first sub-region SB1 located between one side of the curved region BA and the main region MA, and a second sub-region SB2 extending to the other side of the curved region BA.

[0192] In the case that the curved region BA can be deformed into a curved shape, the second sub-region SB2 can be set below the base 110 and can be superimposed on the main region MA.

[0193] The display driver circuit 200 can be set in the second sub-region SB2.

[0194] Integrating into circuit board 300 (see Figure 11 The signal pads (also known as solder pads or solder pads) of the SPD can be set at the edge of the second sub-region SB2.

[0195] Figure 10 This illustrates an embodiment. Figure 12 The layout diagram of part F. Figure 11 It is along Figure 11 A cross-sectional view taken by line G-G'.

[0196] Reference Figure 5 According to an embodiment, the circuit layer 120 of the display device 100 may include light-emitting elements LE electrically connected to the element layer 130 and light-emitting pixel drivers EPDs arranged in a first direction DR1 and a second direction DR2, extending in the second direction DR2 and carrying data signals Vdata (see Figure 12) The data lines DL, the first bypass auxiliary line TASL1 electrically connected to the first data line DL1 among the data lines DL and extending in the first direction DR1, and the second bypass auxiliary line TASL2 electrically connected to the first bypass auxiliary line TASL1 and extending in the second direction DR2 in pairs with the second data line DL2 among the data lines DL, which are transmitted to the light emitting pixel driver EPD, can be spaced farther from the edge of the substrate 110 in the first direction DR1 than the first data line DL1.

[0197] The first bypass auxiliary line TASL1 can be some of the first auxiliary lines ASL1 extending in the first direction DR1.

[0198] The first auxiliary lines ASL1 can overlap the light emitting pixel drivers EPD of the display area DA. The number of the first auxiliary lines ASL1 can be the number of columns each including the emission areas EA arranged in the first direction DR1.

[0199] The first bypass auxiliary line TASL1 can be disposed between the first data line DL1 and the second bypass auxiliary line TASL2. Therefore, since both ends of the first bypass auxiliary line TASL1 can be disposed in the display area DA, in order to reduce the visibility of both ends of the first bypass auxiliary line TASL1, the first auxiliary lines ASL1 can include not only the first bypass auxiliary line TASL1 but also the power auxiliary horizontal line VASHL.

[0200] The second bypass auxiliary line TASL2 can be some of the second auxiliary lines ASL2 extending in the second direction DR2 and can be in pairs with the data lines DL, respectively.

[0201] The data lines DL and the second auxiliary lines ASL2 can be arranged in pairs alternately in the first direction DR1.

[0202] The second bypass auxiliary line TASL2 can be disposed between the first bypass auxiliary line TASL1 and the non-display area NDA. Therefore, since an end portion of the second bypass auxiliary line TASL2 can be disposed in the display area DA, in order to reduce the visibility of the end portion of the second bypass auxiliary line TASL2, the second auxiliary lines ASL2 can include not only the second bypass auxiliary line TASL2 but also the power auxiliary vertical line VASVL.

[0203] The power auxiliary horizontal lines VASHL and the power auxiliary vertical lines VASVL can transmit at least one of the first power ELVDD, the second power ELVSS, and the initialization voltage. As an example, the power auxiliary horizontal lines VASHL and the power auxiliary vertical lines VASVL can transmit the second power ELVSS. In another example, some of the power auxiliary horizontal lines VASHL and some of the power auxiliary vertical lines VASVL can transmit the second power ELVSS, and other of the power auxiliary horizontal lines VASHL and other of the power auxiliary vertical lines VASVL can transmit the initialization voltage.

[0204] According to an embodiment, the data lines DL can include first data lines DL1 disposed in a first bypass side area SDA1 in contact with the non-display area NDA in the first direction DR1 and second data lines DL2 disposed in a second bypass side area SDA2 between the first bypass side area SDA1 and a bypass middle area MDDA in the first direction DR1.

[0205] According to an embodiment, the circuit layer 120 can further include data supply lines DSPL extending from the display driving circuit 200 to the display area DA and transmitting data signals Vdata of the data lines DL.

[0206] The data supply lines DSPL can include first data supply lines DSPL1 transmitting data signals of the first data lines DL1 and second data supply lines DSPL2 transmitting data signals of the second data lines DL2.

[0207] The data supply lines DSPL can extend to the second bypass side area SDA2 and the bypass middle area MDDA.

[0208] Accordingly, the second data supply lines DSPL2 transmitting data signals of the second data lines DL2 can extend to the second bypass side area SDA2 and can be electrically connected (e.g., directly electrically connected) to the second data lines DL2.

[0209] On the other hand, the first data supply lines DSPL1 transmitting data signals of the first data lines DL1 can extend to a second bypass auxiliary line TASL2 of the second bypass side area SDA2 and can be electrically connected to the first data lines DL1 through the second bypass auxiliary line TASL2 and a first bypass auxiliary line TASL1.

[0210] In this way, since the first data supply line DSPL1 does not extend to the first data line DL1 of the first detour side area SDA1, but extends to the second detour auxiliary line TASL2 of the second detour side area SDA2, the extension length of the first data supply line DSPL1 can be reduced. As a result, the width of the area required to arrange the data supply line DSPL can be reduced, so that the width of the non-display area NDA can be reduced.

[0211] Further, since the data supply line DSPL can not be disposed in the portion of the non-display area NDA located between the curved corner portion of the substrate 110 and the first detour side area SDA1, the width of the non-display area NDA can be further reduced.

[0212] The data line DL can further include a third data line DL3 disposed in the detour middle area MDDA. The data supply line DSPL can further include a third data supply line DSPL3 that transmits a data signal of the third data line DL3.

[0213] The third data supply line DSPL3 can extend to the detour middle area MDDA and can be electrically connected (e.g., directly electrically connected) to the third data line DL3.

[0214] The circuit layer 120 can further include a first power supply line VDSPL and a second power supply line VSSPL that respectively transmit a first power ELVDD and a second power ELVSS for driving the light emitting element LE.

[0215] The first power supply line VDSPL and the second power supply line VSSPL can be disposed in the non-display area NDA and can extend to the sub area SBA.

[0216] The first power supply line VDSPL can be electrically connected to a first power pad for transmitting the first power ELVDD among the signal pads SPD disposed in the second sub area SB2.

[0217] The second power supply line VSSPL can be electrically connected to a second power pad for transmitting the second power ELVSS among the signal pads SPD disposed in the second sub area SB2.

[0218] The power auxiliary horizontal line VASHL can be electrically connected to the second power supply line VSSPL.

[0219] The power auxiliary vertical line VASVL can be electrically connected to the power auxiliary horizontal line VASHL and the second power supply line VSSPL.

[0220] According to an embodiment, the circuit layer 120 can further include a first power line VDL electrically connected between the light emitting pixel driver EPD and the first power supply line VDSPL.

[0221] The first power line VDL can be disposed between two second auxiliary lines ASL2 adjacent to each other in the first direction DR1.

[0222] Referring to Figure 7 , the circuit layer 120 of the display device 100 according to an embodiment can further include at least one shield auxiliary electrode SHAE overlapping at least one data line among the data lines DL that intersects the first turn-around auxiliary line TASL1.

[0223] The at least one shield auxiliary electrode SHAE can overlap the intersection region between the first turn-around auxiliary line TASL1 and at least one data line among the data lines DL that is disposed between the second turn-around auxiliary line TASL2 and the first data line DL1 in the first direction DR1, i.e., the overlapping region in a plan view. It will be understood that the term "intersection region" by no means refers to an electrical connection, but rather refers to a region in which the at least one data line and the first turn-around auxiliary line TASL1 overlap each other in a plan view.

[0224] According to an embodiment, the at least one shield auxiliary electrode SHAE can be disposed on a first insulating layer (e.g., the second interlayer insulating layer 126) that covers the first auxiliary line ASL1, and the data lines DL and the second auxiliary lines ASL2 can be disposed on a second insulating layer (e.g., the first planarization layer 127) that covers the at least one shield auxiliary electrode SHAE.

[0225] The third gate conductive layer GCDL3 (see Figure 8 ) disposed on the third gate insulating layer 125 can include the first auxiliary line ASL1, the first source-drain conductive layer SDCDL1 (see Figure 9 ) on the second interlayer insulating layer 126 can include the at least one shield auxiliary electrode SHAE, and the second source-drain conductive layer SDCDL2 (see Figure 7 ) on the first planarization layer 127 can include the data lines DL and the second auxiliary lines ASL2.

[0226] The first insulating layer that covers the first auxiliary line ASL1 can include the second interlayer insulating layer 126, and the second insulating layer that covers the at least one shield auxiliary electrode SHAE can include the first planarization layer 127.

[0227] Accordingly, in a third direction DR3 in which the first insulating layer and the second insulating layer are stacked on each other, the at least one shield auxiliary electrode SHAE can be disposed between the at least one data line and the first turn-around auxiliary line TASL1.

[0228] Further, in order to reduce the wiring resistance of the first auxiliary line ASL1, the third gate conductive layer GCDL3 (see Figure 7) can be provided as a double-layer structure in which a first main layer MNL1 (see Figure 7 ) and a first sub-layer SBL1 (see Figure 12 ) are stacked with each other.

[0229] The at least one shield auxiliary electrode SHAE can correspond to one-to-one with at least one data line provided between the first data line DL1 and the second turn-around auxiliary line TASL2 in the first direction DR1.

[0230] However, this can be only an example, and in the absence of a possibility of an electrical short-circuit, the at least one shield auxiliary electrode SHAE can extend in parallel to the first turn-around auxiliary line TASL1 in the first direction DR1, and can correspond to two or more data lines, which can be adjacent to each other, among at least one data line provided between the first data line DL1 and the second turn-around auxiliary line TASL2.

[0231] As shown in Figure 11 , the at least one shield auxiliary electrode SHAE can extend in parallel to the first turn-around auxiliary line TASL1 in the first direction DR1, and can also overlap an intersection region between the first turn-around auxiliary line TASL1 and at least one second auxiliary line ASL2 among the second auxiliary lines ASL2, which can be paired with the at least one data line, respectively.

[0232] As shown in Figure 12 , the first auxiliary line ASL1 can extend in the first direction DR1 between the first turn-around side region SDA1 and the second turn-around side region SDA2, and can include the first turn-around auxiliary line TASL1 arranged in the second direction DR2.

[0233] According to an embodiment, in order to easily prevent an electrical short-circuit defect between the first turn-around auxiliary lines TASL1, the shorter the first turn-around auxiliary lines TASL1 can be, the more adjacent (or the closer together) the first turn-around auxiliary lines TASL1 can be provided to the sub-region SBA in the second direction DR2.

[0234] Therefore, at least one second auxiliary line ASL2 among the second auxiliary lines ASL2 provided between the first data line DL1 and the second turn-around auxiliary line TASL2 in the first direction DR1 can be a power auxiliary vertical line VASVL.

[0235] As shown in Figure 13 , the second turn-around auxiliary line TASL2 can be electrically connected to the first turn-around auxiliary line TASL1 through a first turn-around connection hole TCH1.

[0236] The first data line DL1 can be electrically connected to the first turn-around auxiliary line TASL1 through a second turn-around connection hole TCH2.

[0237] Each of the first detour connection hole TCH1 and the second detour connection hole TCH2 can penetrate the first planarization layer 127 and the second interlayer insulating layer 126.

[0238] In this way, according to the embodiment, the at least one shield auxiliary electrode SHAE superimposed with the at least one data line DL intersecting the first detour auxiliary line TASL1 can be disposed between the first detour auxiliary line TASL1 and the at least one data line DL.

[0239] Accordingly, the influence of the data signal passing through the first detour auxiliary line TASL1 on the data signal transmitted through the at least one data line DL can be shielded by the at least one shield auxiliary electrode SHAE. Accordingly, the data signal of the at least one data line DL can remain relatively stable without being distorted due to the combination with the data signal of the first detour auxiliary line TASL1. Thus, degradation of display quality due to the arrangement of the first detour auxiliary line TASL1 intersecting the at least one data line DL can be prevented.

[0240] Figure 10 is a layout diagram illustrating a portion F of Figure 14 according to the embodiment. Figure 13 is a schematic diagram of an equivalent circuit of a demultiplexing circuit of Figure 15 Figure 14 is a timing chart illustrating a data multiplexing signal, a first demultiplexing control signal, and a second demultiplexing control signal of a demultiplexing input line illustrated in Figure 14

[0241] Except for the fact that the circuit layer 120 further includes a demultiplexing circuit DMC that outputs a data signal to a data line DL based on a data multiplexing signal supplied from a display driving circuit (D-IC) 200 (see Figure 13 ) and the fact that a data supply line DSPL can be electrically connected between the demultiplexing circuit DMC and the data line DL, Figure 11 The display device 100 of the embodiment illustrated in Figure 14 is substantially the same as the display device 100 of the embodiment illustrated in

[0242] The demultiplexing circuit DMC can be disposed in the sub-area SBA.

[0243] According to the embodiment, the demultiplexing circuit DMC can be disposed in the second sub-area SB2.

[0244] The circuit layer 120 can further include a demultiplexing input line DMIPL electrically connected between the display driving circuit 200 and the demultiplexing circuit DMC.

[0245] ​​The demultiplexing input line DMIPL can transmit a data multiplex signal supplied from the display driving circuit 200 to the demultiplexing circuit DMC.

[0246] The data supply lines DSPL can extend from the demultiplexing circuit DMC to the second bypass side area SDA2 and the bypass middle area MDDA.

[0247] Among the data supply lines DSPL, a first data supply line DSPL1 that transmits a data signal of the first data line DL1 can extend to the second bypass side area SDA2 and can be electrically connected to the second bypass auxiliary line TASL2. The first data supply line DSPL1 can be electrically connected to the first data line DL1 of the first bypass side area SDA1 through the first bypass auxiliary line TASL1 and the second bypass auxiliary line TASL2.

[0248] Among the data supply lines DSPL, a second data supply line DSPL2 that transmits a data signal of the second data line DL2 can extend to the second bypass side area SDA2 and can be electrically connected (e.g., directly electrically connected) to the second data line DL2.

[0249] Among the data supply lines DSPL, a third data supply line DSPL3 that transmits a data signal of the third data line DL3 can extend to the bypass middle area MDDA and can be electrically connected (e.g., directly electrically connected) to the third data line DL3.

[0250] Each of the demultiplexing circuits DMC can be electrically connected to two or more data supply lines DSPL.

[0251] As an example, each of the demultiplexing circuits DMC can include two output terminals.

[0252] The output terminals of the demultiplexing circuit DMC among the plurality of demultiplexing circuits DMC can be electrically connected to the first data supply line DSPL1 and the second data supply line DSPL2.

[0253] As another example, the output terminals of the demultiplexing circuit DMC among the plurality of demultiplexing circuits DMC can be electrically connected to two first data supply lines DSPL1 or can be electrically connected to two second data supply lines DSPL2.

[0254] The output terminals of another demultiplexing circuit DMC among the plurality of demultiplexing circuits DMC can be electrically connected to two third data supply lines DSPL3.

[0255] Reference Figure 15Each of the demultiplexing circuits DMC can include two or more demultiplexing transistors TDM1 and TDM2 electrically connected between each of the two or more data supply lines DSPL and a demultiplexing input line DMIPL.

[0256] As an example, each of the demultiplexing circuits DMC can include a first demultiplexing transistor TDM1 turned on by a first demultiplexing control signal CLA and a second demultiplexing transistor TDM2 turned on by a second demultiplexing control signal CLB.

[0257] Referring to Figure 16 The display driving circuit 200 can output a data multiplexing signal DTMS during each of image frame periods nth_H and nth+1_H (where n can be a natural number of 1 or more). The data multiplexing signal DTMS can include a first data signal and a second data signal corresponding to each of the image frame periods nth_H and nth+1_H (where n can be a natural number of 1 or more).

[0258] The first data signal of the data multiplexing signal DTMS can be output to a data supply line DSPL electrically connected to an output terminal of the demultiplexing circuit DMC during a first period AT in each of the image frame periods nth_H and nth+1_H through a first demultiplexing transistor TDM1 turned on by a first demultiplexing control signal CLA.

[0259] The second data signal of the data multiplexing signal DTMS can be output to another data supply line DSPL electrically connected to an output terminal of the demultiplexing circuit DMC during a second period BT after the first period AT in each of the image frame periods nth_H and nth+1_H through a second demultiplexing transistor TDM2 turned on by a second demultiplexing control signal CLB.

[0260] In this way, according to embodiments, since the data signals of the data lines DL can be supplied in a time-division manner using the demultiplexing circuit DMC, some of the data signals supplied during the first period AT can be susceptible to distortion.

[0261] Specifically, in the first detour side region SDA1 and the second detour side region SDA2, the data signals can be supplied to a portion of at least one data line DL intersecting the first detour auxiliary line TASL1 during the first period AT, and thus can be relatively greatly affected by the data signals transmitted through the first detour auxiliary line TASL1.

[0262] However, the circuit layer 120 of the display device 100 according to embodiments can include at least one shield auxiliary electrode SHAE disposed between at least one data line DL and the first bypass auxiliary line TASL1, so that distortion of a data signal supplied during the first period AT can be reduced.

[0263] Figure 13 is a plan view showing a portion H of Figure 17 according to embodiments. Figure 16 Figure 16 is a schematic cross-sectional view taken along line I-I' of

[0264] Referring to Figure 17 and Figure 16 , the data lines DL (DL1 and DL2), the second auxiliary lines ASL2 (VASVL), and the first power lines VDL can extend in the second direction DR2 and can be disposed in the same layer.

[0265] The first power lines VDL can be disposed in the first direction DR1 between the second auxiliary lines ASL2 (VASVL).

[0266] A second auxiliary line ASL2 (VASVL) of the two second auxiliary lines ASL2 (VASVL) disposed on both sides of the first direction DR1 of the first power lines VDL can be adjacent to a data line DL (DL1, DL2) paired therewith on one side (e.g., left side of Figure 16 ) in the first direction DR1. Further, another second auxiliary line ASL2 (VASVL) of the two second auxiliary lines ASL2 (VASVL) disposed on both sides of the first direction DR1 of the first power lines VDL can be adjacent to a data line DL (DL1, DL2) paired therewith on another side (e.g., right side of Figure 16 ) in the first direction DR1.

[0267] The first bypass auxiliary line TASL1 can extend in the first direction DR1.

[0268] Further, the bias control line GBL, the bias voltage line VBL, the gate initialization voltage line VGIL, the scan initialization line GIL, the scan write line GWL, and the gate control line GCL can extend in the first direction DR1.

[0269] The bias control line GBL and the bias voltage line VBL can be adjacent to each other and can at least partially overlap each other.

[0270] As an example, the bias control line GBL can be disposed in the first gate conductive layer on the first gate insulating layer 122.

[0271] ​Furthermore, the bias voltage line VBL can be disposed on the second gate insulating layer 123 within the second gate conductive layer. However, this is merely an example and can be changed as needed depending on the circuit design.

[0272] The gate initialization voltage line VGIL can be on one side of the second direction DR2 (e.g., Figure 16 (The upper side) is adjacent to the bias control line GBL.

[0273] like Figure 17 and Figure 17 As shown, the first auxiliary line ASL1, including the first bypass auxiliary line TASL1, can be superimposed on a portion of the gate initialization voltage line VGIL.

[0274] As an example, the gate initialization voltage line VGIL can be provided on the first gate insulating layer 122 in the first gate conductive layer.

[0275] According to an embodiment, the first auxiliary line ASL1, including the first bypass auxiliary line TASL1, can be disposed on the second gate insulating layer 123 in the second gate conductive layer.

[0276] According to an embodiment, the circuit layer 120 may include at least one shielding auxiliary electrode SHAE disposed in the intersection region between at least one data line DL1, DL2 and the first bypass auxiliary line TASL1.

[0277] The first auxiliary line ASL1, including the first bypass auxiliary line TASL1, can be disposed on the third gate insulating layer 125 in the third gate conductive layer.

[0278] At least one shielding auxiliary electrode SHAE may be disposed on the second interlayer insulating layer 126 covering the third gate conductive layer in the first source-drain conductive layer.

[0279] At least one shielding auxiliary electrode SHAE may extend parallel to the first bypass auxiliary line TASL1 and may be superimposed on the intersection region between at least one second auxiliary line ASL2 (VASVL) paired with at least one data line DL1, DL2 and the first bypass auxiliary line TASL1.

[0280] In addition, at least one shielded auxiliary electrode SHAE may be stacked at both ends with the first electric field line VDL.

[0281] like Figure 16 As shown, at least one shielded auxiliary electrode SHAE can be electrically connected to the first power line VDL through the shielded auxiliary connection hole SHACH.

[0282] In this way, since the potential of the at least one shield auxiliary electrode SHAE can be maintained at the constant voltage of the first power ELVDD, the electrical shielding of the at least one shield auxiliary electrode SHAE can be made more robust.

[0283] Thus, although the data signal of the at least one data line DL (DL1, DL2) intersecting the first bypass auxiliary line TASL1 can be supplied during the first time period AT, the data signal can be electrically separated from the first bypass auxiliary line TASL1 due to the at least one shield auxiliary electrode SHAE, and thus can be easily maintained during the second time period BT. Accordingly, distortion of the data signal of the at least one data line DL (DL1, DL2) intersecting the first bypass auxiliary line TASL1 can be prevented, and thus the display quality can be improved.

[0284] Unlike the illustration of Figure 17 and Figure 16 , the at least one shield auxiliary electrode SHAE can not be electrically connected to the first power line VDL, but can be electrically connected to another line that transmits a constant voltage. For example, in addition to the first power line VDL, the at least one shield auxiliary electrode SHAE can be electrically connected to one of a gate initialization voltage line VGIL, an anode initialization voltage line VAIL, a bias voltage line VBL, and a second power line VSL that transmits a second power ELVSS.

[0285] As shown in Figure 16 , the scan initialization line GIL can be adjacent to the first auxiliary line ASL1 (TASL1) and the gate initialization voltage line VGIL on one side (e.g., the upper side of Figure 16 ) in the second direction DR2.

[0286] The scan write line GWL can be adjacent to the scan initialization line GIL on one side (e.g., the lower side of Figure 16 ) in the second direction DR2.

[0287] The gate control line GCL can be adjacent to the scan write line GWL on one side (e.g., the lower side of Figure 6 ) in the second direction DR2.

[0288] As an example, the scan write line GWL can be disposed in the first gate conductive layer on the first gate insulating layer 122.

[0289] According to an embodiment, the circuit layer 120 can further include a scan initialization auxiliary line GIAL superposed with the scan initialization line GIL and a gate control auxiliary line GCAL superposed with the gate control line GCL.

[0290] Each of the scan initialization auxiliary lines GIAL and the gate control auxiliary lines GCAL can be disposed in the second gate conductive layer on the second gate insulating layer 123.

[0291] The second semiconductor layer can be disposed on the first interlayer insulating layer 124 covering the second gate conductive layer.

[0292] Each of the scan initialization lines GIL and the gate control lines GCL can be disposed in the third gate conductive layer on the third gate insulating layer 125 covering the second semiconductor layer.

[0293] The portion of the gate control auxiliary lines GCAL which is superposed with the second semiconductor layer can be a second light blocking layer of the third transistor T3, and the portion of the gate control lines GCL which is superposed with the second semiconductor layer can be a gate electrode of the third transistor T3.

[0294] Further, the portion of the scan initialization auxiliary lines GIAL which is superposed with the second semiconductor layer can be a second light blocking layer LB2 (see Figure 6 ) of the fourth transistor T4, and the portion of the scan initialization lines GIL which is superposed with the second semiconductor layer can be a gate electrode G4 (see ​ ) of the fourth transistor T4.

[0295] However, the disclosed effects can not be limited to those set forth herein. The disclosed above and other effects will become more apparent to those of ordinary skill in the art by reading the claims by reference in connection with the above description.

Claims

1. A display device, characterized by comprising: The display device includes: a substrate; a circuit layer disposed on the substrate; and an element layer disposed on the circuit layer, wherein the substrate includes a main area and a sub-area protruding from one side of the main area, the main area including a display area in which an emission area is arranged and a non-display area disposed around the display area, the element layer includes light emitting elements respectively disposed in the emission area, and the circuit layer includes light emitting pixel drivers respectively electrically connected to the light emitting elements, the light emitting pixel drivers being arranged in a first direction and a second direction, data lines extending in the second direction and transmitting a data signal to the light emitting pixel drivers, first auxiliary lines extending in the first direction, and second auxiliary lines extending in the second direction and respectively paired with the data lines, wherein the first auxiliary lines include first bypass auxiliary lines electrically connected to first data lines among the data lines disposed adjacent to an edge of the substrate in the first direction, the second auxiliary lines include second bypass auxiliary lines electrically connected to the first bypass auxiliary lines, the second bypass auxiliary lines being paired with second data lines among the data lines spaced farther apart from the edge of the substrate in the first direction than the first data lines in the first direction, and the circuit layer further includes at least one shield auxiliary electrode superposed with an intersection area between the first bypass auxiliary line and at least one data line among the data lines disposed between the second bypass auxiliary line and the first data line in the first direction. 2.The display device of claim 1, wherein the at least one shield auxiliary electrode is disposed on a first insulating layer covering the first auxiliary lines, the data lines and the second auxiliary lines are disposed on a second insulating layer covering the at least one shield auxiliary electrode, and in a third direction in which the first insulating layer and the second insulating layer are stacked on each other, the at least one shield auxiliary electrode is disposed between the at least one data line and the first bypass auxiliary line.

3. The display device according to claim 2, wherein The at least one shield auxiliary electrode extends in parallel with the first bypass auxiliary line and is further superposed with an intersection area between the first bypass auxiliary line and at least one second auxiliary line among the second auxiliary lines respectively paired with the at least one data line.

4. The display device according to claim 3, wherein Each of the light emitting pixel drivers includes: a first transistor electrically connected between a first node and a second node; a pixel capacitor electrically connected between a third node and a first power line transmitting a first power; a second transistor electrically connected between the data line and the first node; a third transistor electrically connected between the second node and the third node; a fourth transistor electrically connected between a gate initialization voltage line and the third node; a fifth transistor electrically connected between the first power line and the first node; a sixth transistor electrically connected between the second node and a fourth node; a seventh transistor electrically connected between the fourth node and an anode initialization voltage line that transmits an anode initialization voltage; and an eighth transistor electrically connected between a bias voltage line and the first node, the first node is electrically connected to a first electrode of the first transistor, the second node is electrically connected to a second electrode of the first transistor, the third node is electrically connected to a gate electrode of the first transistor, the fourth node is electrically connected to one of the light emitting elements, the first power line extends in the second direction, is arranged between adjacent first auxiliary lines in the first direction, and is provided on the second insulating layer, and among the at least one shield auxiliary electrode, two shield auxiliary electrodes adjacent in the first direction are provided adjacent to both sides of the first power line in the first direction.

5. The display device according to claim 4, wherein the at least one shield auxiliary electrode is electrically connected to the first power line.

6. The display device according to claim 4, wherein The circuit layer further includes: a first semiconductor layer provided on the substrate; a first gate insulating layer covering the first semiconductor layer; a first gate conductive layer provided on the first gate insulating layer; a second gate insulating layer covering the first gate conductive layer; a second gate conductive layer provided on the second gate insulating layer; a first interlayer insulating layer covering the second gate conductive layer; a second semiconductor layer provided on the first interlayer insulating layer; a third gate insulating layer covering the second semiconductor layer; a third gate conductive layer provided on the third gate insulating layer; a second interlayer insulating layer covering the third gate conductive layer; a first source-drain conductive layer provided on the second interlayer insulating layer; a first planarization layer covering the first source-drain conductive layer; a second source-drain conductive layer provided on the first planarization layer; and a second planarization layer covering the second source-drain conductive layer, and wherein the first insulating layer includes the second interlayer insulating layer, and the second insulating layer includes the first planarization layer.

7. The display device of claim 6, wherein the third gate conductive layer includes the first auxiliary line, the first source-drain conductive layer includes the at least one shield auxiliary electrode, and the second source-drain conductive layer includes the data line, the second auxiliary line, and the first power line.

8. The display device of claim 7, wherein each of the third gate conductive layer, the first source-drain conductive layer, and the second source-drain conductive layer has a multi-layer structure including a main layer and at least one sub-layer provided on at least one side of the main layer, the main layer includes any one of molybdenum, aluminum, chromium, gold, nickel, neodymium, copper, and combinations thereof, and the at least one sub-layer includes titanium.

9. The display device according to claim 2, wherein The display device further includes: a display driving circuit provided in the sub-region to supply the data signal to the data line, wherein, The circuit layer further includes data supply lines extending from the display driving circuit to the display area to transmit the data signals to the data lines, Among the data supply lines, a first data supply line transmitting a data signal of the first data line is electrically connected to the first bypass auxiliary line, and Among the data supply lines, a second data supply line transmitting a data signal of the second data line is directly electrically connected to the second data line.

10. The display device according to claim 2, wherein The display device further includes: a display driving circuit disposed in the sub-area, wherein the circuit layer further includes a demultiplexing circuit disposed in the sub-area to output the data signals to the data lines based on data multiplexing signals supplied from the display driving circuit, and data supply lines electrically connected between the demultiplexing circuit and the data lines to transmit the data signals to the data lines, Among the data supply lines, a first data supply line transmitting a data signal of the first data line is electrically connected to the first bypass auxiliary line, and Among the data supply lines, a second data supply line transmitting a data signal of the second data line is directly electrically connected to the second data line.

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