Array substrate and display panel
By placing the demultiplexing transistor on the side of the scan line away from the pixel unit in the liquid crystal display panel and adopting a two-layer metal layer design, the problem of cross-line overlap between the demultiplexing transistor and the switching transistor is solved, thereby improving the display effect and production efficiency, and enhancing the sub-pixel density and resolution.
Patent Information
- Application Number
- CN202423317185.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2025-11-21
- Estimated Expiration
- 2034-12-31
AI Technical Summary
In traditional LCD panels, the overlapping of demultiplexing transistors and switching transistors across lines leads to increased parasitic capacitance, affecting display quality. Furthermore, the multi-layer metal design increases production costs and reduces production efficiency.
The demultiplexing transistor is placed on the side of the scan line away from the pixel unit. A two-layer metal layer design is used to avoid the overlap of the demultiplexing transistor and the switching transistor across the line. The number of data lines and clock signal lines is reduced through reasonable layout.
Reducing the parasitic capacitance of demultiplexing transistors and switching transistors improves display quality, lowers production costs and increases production efficiency, while also enhancing subpixel density and resolution.
Smart Images
Figure CN223582279U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of display, in particular to an array substrate and a display panel. BACKGROUND
[0002] At present, full screen is the development trend of the market, in order to improve the screen ratio, reducing the size of the lower frame is an important technical point. In order to reduce the size of the lower frame, the traditional liquid crystal display panel can integrate the demultiplexer (Demux) of the array substrate in the lower frame non-pixel area into the sub-pixel inside the pixel area.
[0003] The demultiplexer includes a demultiplexing transistor, when the demultiplexing transistor is integrated in the sub-pixel, the demultiplexing transistor will cross the line overlap with the switching transistor of the sub-pixel, resulting in the increase of the parasitic capacitance of the demultiplexing transistor and the switching transistor, which affects the display effect of the display panel.
[0004] Therefore, it is necessary to provide a new technical scheme to solve the above technical problems. UTILITY MODEL CONTENT
[0005] The purpose of the present application is to provide an array substrate and a display panel to improve the display effect of the display panel.
[0006] To solve the above problems, the technical scheme of the present application is as follows:
[0007] In a first aspect, the present application provides an array substrate, comprising a pixel area, the array substrate comprising:
[0008] A first pixel unit is arranged in the pixel area and comprises a first switching transistor;
[0009] A first scanning line is electrically connected to the gate of the first switching transistor; and
[0010] A demultiplexer is arranged in the pixel area and comprises a first demultiplexing transistor, the output of the first demultiplexing transistor being electrically connected to the input of the first switching transistor;
[0011] In the plan view of the array substrate, the first scanning line is located on one side of the first pixel unit, and the first demultiplexing transistor is located on the side of the first scanning line away from the first pixel unit.
[0012] In an embodiment of the present application, the array substrate further comprises a first clock signal line, the first clock signal line being electrically connected to the gate of the first demultiplexing transistor;
[0013] In a plan view of the array substrate, the first clock signal line is located on a side of the first scan line away from the first pixel unit, and the first demultiplexing transistor is located between the first clock signal line and the first scan line.
[0014] In an embodiment of the present application, the first scan line and the first clock signal line are arranged in the same layer;
[0015] The first switch transistor comprises:
[0016] a first gate arranged in the same layer as the first scan line and electrically connected to the first scan line; and
[0017] a first source-drain metal layer arranged in a layer different from the first gate;
[0018] The first demultiplexing transistor comprises:
[0019] a second gate arranged in the same layer as the first gate and spaced apart from the first gate and electrically connected to the first clock signal line; and
[0020] a second source-drain metal layer arranged in the same layer as the first source-drain metal layer and spaced apart from the first source-drain metal layer.
[0021] In an embodiment of the present application, the first pixel unit comprises two first sub-pixels arranged in a column direction, and each of the first sub-pixels comprises the first switch transistor;
[0022] The array substrate further comprises:
[0023] a first connection line extending in the column direction, and an output terminal of the first demultiplexing transistor being electrically connected to input terminals of the first switch transistors of two first sub-pixels of the same first pixel unit through the first connection line; and
[0024] a second scan line, the first scan line and the second scan line being arranged alternately in the column direction;
[0025] In a plan view of the array substrate, the first scan line is located on the same side of the two first sub-pixels of the same first pixel unit and is electrically connected to the adjacent first sub-pixel;
[0026] The second scan line is located between the two first sub-pixels of the same first pixel unit and is electrically connected to the other first sub-pixel of the same first pixel unit.
[0027] In an embodiment of the present application, the multiplexer further comprises a second demultiplexing transistor;
[0028] The array substrate further comprises:
[0029] a second pixel unit, arranged alternately with the first pixel unit along a row direction, the second pixel unit comprising two second sub-pixels arranged along a column direction, each of the first sub-pixel comprising a second switch transistor;
[0030] a second connection line, extending along the column direction, the second connection line arranged alternately with the first connection line along the row direction, an output terminal of the second demultiplexing transistor electrically connected to input terminals of the second switch transistors of the two second sub-pixels of the same second pixel unit through the second connection line; and
[0031] a second clock signal line, electrically connected to gate terminals of the second demultiplexing transistor;
[0032] in a plan view of the array substrate, the first scan line is located on the same side of the two second sub-pixels of the same second pixel unit and electrically connected to the adjacent second sub-pixel;
[0033] the second scan line and the second clock signal line are located between the two second sub-pixels of the same second pixel unit, and the second scan line is electrically connected to the other second sub-pixel of the same second pixel unit;
[0034] the second demultiplexing transistor is located between the second scan line and the second clock signal line.
[0035] In an embodiment of the present application, the first clock signal line, the first scan line, the second clock signal line and the second scan line are arranged alternately along the column direction.
[0036] In an embodiment of the present application, the array substrate further comprises a first data line, the first data line extending along the column direction, the first data line electrically connected to the input terminal of the first demultiplexing transistor and the input terminal of the second demultiplexing transistor, respectively;
[0037] in a plan view of the array substrate, the first data line is located on a side of the first pixel unit away from the second pixel unit.
[0038] In an embodiment of the present application, the multiplexer further comprises a third demultiplexing transistor and a fourth demultiplexing transistor;
[0039] the array substrate further comprises:
[0040] a third pixel unit comprising two third sub-pixels arranged along a column direction, each of the third sub-pixel comprising a third switch transistor;
[0041] A third connection line extends along the column direction, the third connection line is electrically connected with an output terminal of the third demultiplexing transistor, and the third connection line electrically connects two third sub-pixels of the same third pixel unit.
[0042] A fourth pixel unit includes two fourth sub-pixels arranged along the column direction, each of the fourth sub-pixels includes a fourth switch transistor, and the third pixel unit and the fourth pixel unit are alternately arranged along the row direction.
[0043] A fourth connection line extends along the column direction, the fourth connection line is electrically connected with an output terminal of the fourth demultiplexing transistor, and the fourth connection line electrically connects two fourth sub-pixels of the same fourth pixel unit, and the third connection line and the fourth connection line are alternately arranged along the row direction.
[0044] In a plan view of the array substrate, the first scan line is located on the same side of two second sub-pixels of the same third pixel unit and is electrically connected with adjacent third sub-pixels.
[0045] The first scan line is located on the same side of two fourth sub-pixels of the same fourth pixel unit and is electrically connected with adjacent fourth sub-pixels.
[0046] The second scan line and the second clock signal line are located between two third sub-pixels of the same third pixel unit, and the second scan line is electrically connected with another third sub-pixel of the same third pixel unit.
[0047] The second scan line and the second clock signal line are located between two fourth sub-pixels of the same fourth pixel unit, and the second scan line is electrically connected with another fourth sub-pixel of the same fourth pixel unit.
[0048] The third demultiplexing transistor is located between the first scan line and the first clock signal line.
[0049] The fourth demultiplexing transistor is located between the second scan line and the second clock signal line.
[0050] In an embodiment of the present application, the first sub-pixel further includes a first pixel electrode, and the first pixel electrode is electrically connected with an output terminal of the first switch transistor.
[0051] The second sub-pixel further includes a second pixel electrode, and the second pixel electrode is electrically connected with an output terminal of the second switch transistor.
[0052] The third sub-pixel further comprises a third pixel electrode, which is electrically connected with the output terminal of the third switch transistor;
[0053] The fourth sub-pixel further comprises a fourth pixel electrode, which is electrically connected with the output terminal of the fourth switch transistor;
[0054] The first pixel unit, the third pixel unit, the second pixel unit and the fourth pixel unit are arranged alternately along the row direction;
[0055] The first connection line, the third connection line, the second connection line and the fourth connection line are arranged alternately along the row direction;
[0056] The first demultiplexing transistor and the third demultiplexing transistor are arranged alternately along the row direction;
[0057] The second demultiplexing transistor and the fourth demultiplexing transistor are arranged alternately along the row direction;
[0058] The array substrate further comprises a second data line, which extends along the column direction, and the second data line is electrically connected with the input terminal of the third demultiplexing transistor and the input terminal of the fourth demultiplexing transistor respectively, and the second data line and the first data line are arranged alternately along the row direction;
[0059] In the plan view of the array substrate, the second data line is located between the second pixel unit and the fourth pixel unit.
[0060] In an embodiment of the present application, one first pixel unit, one first demultiplexing transistor corresponding to the first pixel unit, one first connection line corresponding to the first pixel unit, one third pixel unit, one third demultiplexing transistor corresponding to the third pixel unit, one third connection line corresponding to the third pixel unit, one second pixel unit, one second demultiplexing transistor corresponding to the second pixel unit, one second connection line corresponding to the second pixel unit, one fourth pixel unit, one fourth demultiplexing transistor corresponding to the fourth pixel unit and one fourth connection line corresponding to the fourth pixel unit form one minimum cycle unit;
[0061] In the plan view of the array substrate, a plurality of minimum cycle units are arranged in the pixel area.
[0062] In an embodiment of the present application,
[0063] In a first time period, the first data line outputs a positive polarity voltage, the second data line outputs a negative polarity voltage, the first clock signal line outputs a high potential, the second clock signal line outputs a low potential, the first demultiplexing transistor is turned on, the first data line is electrically connected with the first pixel electrode, and the second demultiplexing transistor, the third demultiplexing transistor and the fourth demultiplexing transistor are turned off;
[0064] In a second time period, the first data line outputs a positive polarity voltage, the second data line outputs a negative polarity voltage, the first clock signal line outputs a low potential, the second clock signal line outputs a high potential, the second demultiplexing transistor is turned on, the first data line is electrically connected with the second pixel electrode, and the first demultiplexing transistor, the third demultiplexing transistor and the fourth demultiplexing transistor are turned off;
[0065] In a third time period, the first data line outputs a negative polarity voltage, the second data line outputs a positive polarity voltage, the first clock signal line outputs a high potential, the second clock signal line outputs a low potential, the third demultiplexing transistor is turned on, the second data line is electrically connected with the third pixel electrode, and the first demultiplexing transistor, the second demultiplexing transistor and the fourth demultiplexing transistor are turned off;
[0066] In a fourth time period, the first data line outputs a negative polarity voltage, the second data line outputs a positive polarity voltage, the first clock signal line outputs a low potential, the second clock signal line outputs a high potential, the fourth demultiplexing transistor is turned on, the second data line is electrically connected with the fourth pixel electrode, and the first demultiplexing transistor, the second demultiplexing transistor and the third demultiplexing transistor are turned off.
[0067] In an embodiment of the present application, the first pixel electrode corresponds to a pixel of a first color, the second pixel electrode corresponds to a pixel of a second color, the third pixel electrode corresponds to a pixel of a third color, and the fourth pixel electrode corresponds to a pixel of the second color.
[0068] In an embodiment of the present application, the first color, the second color and the third color are all different.
[0069] In a second aspect, the present application provides a display panel, comprising an array substrate, the array substrate comprising a pixel region, the array substrate further comprising a first pixel unit, a first scan line and a multiplexer, the first pixel unit being arranged in the pixel region and comprising a first switch transistor, the first scan line being electrically connected to a gate electrode of the first switch transistor, and the multiplexer being arranged in the pixel region and comprising a first demultiplexing transistor, an output electrode of the first demultiplexing transistor being electrically connected to an input electrode of the first switch transistor, in a plan view of the array substrate, the first scan line is located on one side of the first pixel unit, and the first demultiplexing transistor is located on a side of the first scan line away from the first pixel unit.
[0070] The present application sets the first demultiplexing transistor on a side of the first scan line away from the first pixel unit, thereby avoiding the phenomenon of cross-line overlap between the demultiplexing transistor and the switch transistor of the sub-pixel, reducing the parasitic capacitance of the demultiplexing transistor and the switch transistor, and improving the display effect of the display panel. BRIEF DESCRIPTION OF DRAWINGS
[0071] Figure 1 is a schematic diagram of a conventional array substrate;
[0072] Figure 2 is a schematic diagram of an embodiment of the array substrate of the present application;
[0073] Figure 3 is a schematic diagram of an embodiment of the array substrate of the present application;
[0074] Figure 4 is a schematic diagram of an embodiment of the array substrate of the present application;
[0075] Figure 5 is a schematic diagram of an embodiment of the array substrate of the present application;
[0076] Figure 6 is a schematic diagram of an embodiment of the array substrate of the present application;
[0077] Figure 7 is a schematic diagram of a minimum cycle unit of the present application;
[0078] Figure 8 is a schematic diagram of an embodiment of the array substrate of the present application;
[0079] Figure 9 is Figure 8 a timing diagram of the array substrate of the present application. DETAILED DESCRIPTION
[0080] The meanings of the terms used in the specification and claims correspond to the meanings commonly understood by those of ordinary skill in the art to which the present application pertains. The terms used in the specification and claims are only for the purpose of facilitating the description and understanding of the present application, and are not intended to limit the present application to the narrow interpretation of the specific terms used in the specification and claims.
[0081] Referring to Figure 1 In the conventional array substrate 100a, in order to reduce the size of the lower frame, the demultiplexing transistor T01 originally located in the lower frame non-pixel area is integrated into the sub-pixel in the pixel area, so as to achieve the effect of reducing the size of the lower frame non-pixel area. However, since the switching transistor T02 is also arranged in the sub-pixel, the demultiplexing transistor T01 and the switching transistor T02 are arranged on the same side of the scan signal line G0, so that the demultiplexing transistor T01 and the switching transistor T02 will have a cross-line overlapping phenomenon, resulting in an increase in the parasitic capacitance of the demultiplexing transistor T01 and the switching transistor T02, which affects the display effect of the display panel.
[0082] Meanwhile, referring to Figure 1 In the conventional array substrate 100a, since the wiring of the input terminal of the demultiplexing transistor T01 will have a cross-line overlapping phenomenon with the wiring of the input terminal / output terminal of the switching transistor T02, the source / drain metal layer of the demultiplexing transistor T01 needs to be arranged in a different layer from the source / drain metal layer of the switching transistor T02, or when the source / drain metal layer of the demultiplexing transistor T01 and the source / drain metal layer of the switching transistor T02 are arranged in the same layer, an additional cross-wiring layer needs to be arranged. Meanwhile, the gate of the demultiplexing transistor T01 and the gate of the switching transistor T02 both need to be made of a metal layer. Therefore, in the conventional array substrate 100a, in order to realize the cross-line overlapping design of the demultiplexing transistor T01 and the switching transistor T02, at least three metal layers are needed, one of which is used to arrange the gate of the demultiplexing transistor T01 and the gate of the switching transistor T02, another of which is used to arrange the source / drain metal layer of the demultiplexing transistor T01 and the source / drain metal layer of the switching transistor T02, and the other of which is used to arrange the cross-wiring of the demultiplexing transistor T01 and the switching transistor T02. For the three metal layers, a photomask needs to be used for patterning in the process of the conventional array substrate 100a, resulting in an increase in the number of photomasks used, an increase in production cost, and a decrease in production efficiency.
[0083] The present application provides a display panel. The display panel is a liquid crystal display panel. The display panel comprises an array substrate 100 and a counter substrate arranged oppositely, and a liquid crystal layer between the array substrate 100 and the counter substrate.
[0084] Referring to Figure 2 The present application provides an array substrate 100 comprising a pixel area PA.
[0085] The array substrate 100 further comprises a first pixel unit 10, a first scan line G1 and a multiplexer 20. The first pixel unit 10 is arranged in the pixel area PA and comprises a first switch transistor T1. The first scan line G1 is electrically connected to the gate of the first switch transistor T1. The multiplexer 20 is arranged in the pixel area PA. The multiplexer 20 comprises a first demultiplexing transistor 21. The output of the first demultiplexing transistor 21 is electrically connected to the input of the first switch transistor T1.
[0086] In the plan view of the array substrate 100, the first scan line G1 is located on one side of the first pixel unit 10. The first demultiplexing transistor 21 is located on the side of the first scan line G1 away from the first pixel unit 10.
[0087] The present application sets the first demultiplexing transistor 21 on the side of the first scan line G1 away from the first pixel unit 10, thereby avoiding the cross-line overlap between the demultiplexing transistor and the switch transistor of the sub-pixel, reducing the parasitic capacitance of the demultiplexing transistor and the switch transistor, and improving the display effect of the display panel.
[0088] Optionally, the first pixel unit 10 comprises at least one first sub-pixel 11, and each first sub-pixel 11 comprises a first pixel electrode 113. The first pixel electrode 113 is electrically connected to the output of the first switch transistor T1.
[0089] Optionally, the first sub-pixel 11 further comprises a first capacitor, and the first capacitor is electrically connected to the output of the first switch transistor T1.
[0090] Optionally, referring to Figure 2 , the array substrate 100 further comprises a first clock signal line CK1. The first clock signal line CK1 is electrically connected to the gate of the first demultiplexing transistor 21.
[0091] In the plan view of the array substrate 100, the first clock signal line CK1 is located on the side of the first scan line G1 away from the first pixel unit 10. The first demultiplexing transistor 21 is located between the first clock signal line CK1 and the first scan line G1.
[0092] In the present embodiment, the first clock signal line CK1 is used to control the on-off of the first demultiplexing transistor 21. The first scan line G1 is used to control the on-off of the first switch transistor T1. The first demultiplexing transistor 21 can be turned on by outputting a high potential through the first clock signal line CK1. The first switch transistor T1 can be turned on by outputting a high potential through the first scan line G1.
[0093] Optionally, referring to Figure 2The array substrate 100 further comprises a first data line D1. The first data line D1 extends along the column direction Y, and the first data line D1 is electrically connected with the input terminal of the first demultiplexing transistor 21 respectively.
[0094] In the embodiment, the first pixel unit 10 is electrically connected with the data processing chip through the first data line D1. When the data processing chip outputs a signal through the first data line D1, the signal output by the data processing chip can be transmitted to the first pixel electrode 113 along the first data line D1, the input terminal of the first demultiplexing transistor 21, the output terminal of the first demultiplexing transistor 21, the input terminal of the first switching transistor T1, and the output terminal of the first switching transistor T1 by controlling the first demultiplexing transistor 21 to be turned on and the first switching transistor T1 to be turned on, so that the first pixel electrode 113 is turned on, the rotation of the liquid crystal is controlled, and the light emission of the first sub-pixel 11 is realized.
[0095] Optionally, referring to Figure 3 The first scan line G1 and the first clock signal line CK1 are arranged in the same layer.
[0096] The first switching transistor T1 comprises a first gate 111 and a first source-drain metal layer 112. The first gate 111 is arranged in the same layer as the first scan line G1 and is electrically connected with the first scan line G1. The first source-drain metal layer 112 is arranged in a layer different from the first gate 111.
[0097] The first demultiplexing transistor 21 comprises a second gate and a second source-drain metal layer. The second gate is arranged in the same layer as the first gate 111 and is spaced apart from the first gate 111, and is electrically connected with the first clock signal line CK1. The second source-drain metal layer is arranged in the same layer as the first source-drain metal layer 112 and is spaced apart from the first source-drain metal layer 112.
[0098] In the embodiment, since the first switching transistor T1 and the first demultiplexing transistor 21 do not need to cross and overlap, the first source-drain metal layer 112 and the second source-drain metal layer can be arranged in the same layer, and an additional metal layer is not needed to connect the input terminal of the first switching transistor T1 and the output terminal of the first demultiplexing transistor 21. Therefore, in the array substrate 100 of the embodiment, only two metal layers are needed to realize the arrangement of the first switching transistor T1 and the first demultiplexing transistor 21. One of the two metal layers is used to arrange the first gate 111 of the first switching transistor T1, the second gate of the first demultiplexing transistor 21, the first clock signal line CK1, and the first scan line G1. The other of the two metal layers is used to arrange the first source-drain metal layer 112 of the first switching transistor T1 and the second source-drain metal layer of the first demultiplexing transistor 21. Compared with the structure of the conventional array substrate 100a which needs at least three metal layers, at least one metal layer is reduced in the present application, so that the number of masks needed to produce the array substrate 100 is reduced, the production cost is reduced, and the production efficiency is improved.
[0099] It should be understood that in a transistor, the source-drain metal layer includes a source and a drain. The source and the drain are arranged in a spaced manner, and the source and the drain are electrically connected to the active layer of the transistor, respectively. The metal layer where the gate is located is arranged in a spaced manner with the source-drain metal layer through an insulating layer. In a sub-pixel, the source-drain metal layer of the switch transistor is arranged in a spaced manner with the pixel electrode through an insulating layer, and the drain of the switch transistor is electrically connected to the pixel electrode. Optionally, the source is an input terminal, and the drain is an output terminal.
[0100] Optionally, referring to Figure 3 , the first switch transistor T1 and the first demultiplexing transistor 21 are transistors in a top-gate structure. The first metal layer is arranged on the substrate 71, and the first metal layer includes a first source-drain metal layer 112 of the first switch transistor T1 and a second source-drain metal layer of the first demultiplexing transistor 21. The first source-drain metal layer 112 includes a first source 112a and a first drain 112b. The second source-drain metal layer includes a second source and a second drain. The first switch transistor T1 further includes a first active layer 114 arranged on the first source 112a and the first drain 112b. The first demultiplexing transistor 21 further includes a second active layer arranged on the second source and the second drain. The first insulating layer 72 covers the first metal layer, the first active layer 114, and the second active layer. The second metal layer is arranged on the first insulating layer 72, and the second metal layer includes a first gate 111 of the first switch transistor T1, a first scan line G1, a first clock signal line CK1, and a second gate of the first demultiplexing transistor 21. The second insulating layer 73 covers the second metal layer. The first pixel electrode 113 is arranged on the second insulating layer 73 and is electrically connected to the first drain 112b through the second insulating layer 73 and the first insulating layer 72.
[0101] Optionally, referring to Figure 4 , the first switch transistor T1 and the first demultiplexing transistor 21 are transistors in a bottom-gate structure. The first metal layer is arranged on the substrate 71, and the first metal layer includes a first gate 111 of the first switch transistor T1, a first scan line G1, a first clock signal line CK1, and a second gate of the first demultiplexing transistor 21. The first insulating layer 72 covers the first metal layer. The first active layer 114 and the second active layer are arranged on the first insulating layer 72. The second metal layer is arranged on the first active layer 114 and the second active layer, and the second metal layer includes a first source-drain metal layer 112 and a second source-drain metal layer. The first source 112a and the first drain 112b are arranged in a spaced manner on the first active layer 114, and the second source and the second drain are arranged in a spaced manner on the second active layer. The second insulating layer 73 covers the second metal layer, the first active layer 114, and the second active layer. The first pixel electrode 113 is arranged on the second insulating layer 73 and is electrically connected to the first drain 112b through the second insulating layer 73.
[0102] Compared with the top-gate structure design, the bottom-gate structure can reduce the via depth of the first pixel electrode 113, so that the first pixel electrode 113 only needs to pass through one layer of the second insulating layer 73 to be electrically connected with the first drain 112b.
[0103] Optionally, referring to Figure 5 , the first pixel unit 10 includes two first sub-pixels 11 arranged along the column direction Y. Each first sub-pixel 11 includes a first switch transistor T1.
[0104] The array substrate 100 further includes a first connection line A1 and a second scan line G2. The first connection line A1 extends along the column direction Y. The output terminal of one demultiplexing transistor is electrically connected with the input terminals of the first switch transistors T1 of the two first sub-pixels 11 of the same first pixel unit 10 through the first connection line A1. The first scan line G1 and the second scan line G2 are alternately arranged along the column direction Y.
[0105] In the plan view of the array substrate 100, the first scan line G1 is located on the same side of the two first sub-pixels 11 of the same first pixel unit 10. The first scan line G1 is electrically connected with the adjacent first sub-pixel 11. The second scan line G2 is located between the two first sub-pixels 11 of the same first pixel unit 10. The second scan line G2 is electrically connected with the other first sub-pixel 11 of the same first pixel unit 10.
[0106] In the present embodiment, the first pixel unit 10 includes two first sub-pixels 11. Through the design of the first connection line A1, one first demultiplexing transistor 21 can control the signal input of the two first sub-pixels 11 in the same first pixel unit 10, which reduces the number of first demultiplexing transistors 21 and reduces the production cost. At the same time, the first demultiplexing transistor 21 does not produce cross-line overlap with the two first switch transistors T1 in the same first pixel unit 10, so that under the premise of integrating the demultiplexing transistor in the pixel area PA, the phenomenon of cross-line overlap between the demultiplexing transistor and the switch transistor of the sub-pixel is avoided, the parasitic capacitance of the first demultiplexing transistor 21 and the first switch transistor T1 is reduced, and the display effect of the display panel is improved.
[0107] The first scan line G1 and the second scan line G2 are used to control the on-off of the first sub-pixels 11 in different rows.
[0108] Optionally, referring to Figure 6 , the multiplexing demultiplexer 20 further includes a second demultiplexing transistor 22.
[0109] The array substrate 100 further comprises a second pixel unit 30, a second connection line A2 and a second clock signal line CK2. The second pixel unit 30 is arranged alternately with the first pixel unit 10 along the row direction X. The second pixel unit 30 comprises two second sub-pixels 31 arranged along the column direction Y. Each first sub-pixel 11 comprises a second switch transistor T2. The second connection line A2 extends along the column direction Y. The second connection line A2 is arranged alternately with the first connection line Al along the row direction X. The output terminal of the second demultiplexing transistor 22 is electrically connected to the input terminal of the second switch transistor T2 of the two second sub-pixels 31 of the same second pixel unit 30 through the second connection line A2. The second clock signal line CK2 is electrically connected to the gate of the second demultiplexing transistor 22.
[0110] In the plan view of the array substrate 100, the first scan line G1 is located at the same side of the two second sub-pixels 31 of the same second pixel unit 30. The first scan line G1 is electrically connected to the adjacent second sub-pixel 31. The second scan line G2 and the second clock signal line CK2 are located between the two second sub-pixels 31 of the same second pixel unit 30. The second scan line G2 is electrically connected to the other second sub-pixel 31 of the same second pixel unit 30. The second demultiplexing transistor 22 is located between the second scan line G2 and the second clock signal line CK2.
[0111] The first data line Dl is electrically connected to the input terminal of the first demultiplexing transistor 21 and the input terminal of the second demultiplexing transistor 22 respectively. In the plan view of the array substrate 100, the first data line Dl is located at the side of the first pixel unit 10 away from the second pixel unit 30.
[0112] In the present embodiment, the input of the data signal of the first pixel unit 10 is controlled by the first demultiplexing transistor 21, and the input of the data signal of the second pixel unit 30 is controlled by the second demultiplexing transistor 22. The scheme that originally requires two data lines to input the data signal to the first pixel unit 10 and the second pixel unit 30 respectively is replaced by the scheme that only one first data line Dl is required to input the data signal to the first pixel unit 10 and the second pixel unit 30 through the first demultiplexing transistor 21 and the second demultiplexing transistor 22 respectively, thereby reducing the number of data lines and the number of data driving chips required for driving the array substrate 100 and the production cost.
[0113] The first scan line G1 is used to control the on-off of the first switch transistor Tl and the second switch transistor T2 of one row, and the second scan line G2 is used to control the on-off of the first switch transistor Tl and the second switch transistor T2 of the other row. The first clock signal line CK1 is used to control the on-off of the first demultiplexing transistor 21, and the second clock signal line CK2 is used to control the on-off of the second demultiplexing transistor 22.
[0114] When the data processing chip outputs a signal through the first data line D1, the first demultiplexing transistor 21 is controlled to be turned on, the first switch transistor T1 is controlled to be turned on, and the second demultiplexing transistor 22 is controlled to be turned off. The signal output by the data processing chip reaches the first pixel electrode 113 through the first data line D1, the input terminal of the first demultiplexing transistor 21, the output terminal of the first demultiplexing transistor 21, the first connecting line A1, the input terminal of the first switch transistor T1, and the output terminal of the first switch transistor T1, so that the first pixel electrode 113 is turned on, the rotation of the liquid crystal is controlled, and the light emission of the first sub-pixel 11 is realized. Alternatively, the second demultiplexing transistor 22 is controlled to be turned on, the second switch transistor T2 is controlled to be turned on, and the first demultiplexing transistor 21 is controlled to be turned off. The signal output by the data processing chip reaches the second pixel electrode 311 through the first data line D1, the input terminal of the second demultiplexing transistor 22, the output terminal of the second demultiplexing transistor 22, the second connecting line A2, the input terminal of the second switch transistor T2, and the output terminal of the second switch transistor T2, so that the second pixel electrode 311 is turned on, the rotation of the liquid crystal is controlled, and the light emission of the second sub-pixel 31 is realized.
[0115] Optionally, referring to Figure 6 , the first clock signal line CK1, the first scan line G1, the second clock signal line CK2, and the second scan line G2 are arranged alternately along the column direction Y.
[0116] In the embodiment, the gap between the two sub-pixels arranged along the column direction Y can be fully utilized, so that the pixel density is improved, and the resolution of the display panel is improved. Meanwhile, the arrangement design can avoid the phenomenon that the demultiplexing transistor and the switch transistor of the sub-pixel cross and overlap, reduce the parasitic capacitance of the demultiplexing transistor and the switch transistor, and improve the display effect of the display panel.
[0117] Optionally, referring to Figure 7 , the multiplexing demultiplexer 20 further includes a third demultiplexing transistor 23 and a fourth demultiplexing transistor 24.
[0118] The array substrate 100 further comprises a third pixel unit 40, a third connection line A3, a fourth pixel unit 50 and a fourth connection line A4. The third pixel unit 40 comprises two third sub-pixels 41 arranged along the column direction Y. Each third sub-pixel 41 comprises a third switch transistor T3. The third connection line A3 extends along the column direction Y. The third connection line A3 is electrically connected with the output terminal of the third demultiplexing transistor 23. The third connection line A3 electrically connects the two third sub-pixels 41 of the same third pixel unit 40. The fourth pixel unit 50 comprises two fourth sub-pixels 51 arranged along the column direction Y. Each fourth sub-pixel 51 comprises a fourth switch transistor T4. The third pixel unit 40 and the fourth pixel unit 50 are alternately arranged along the row direction X. The fourth connection line A4 extends along the column direction Y. The fourth connection line A4 is electrically connected with the output terminal of the fourth demultiplexing transistor 24. The fourth connection line A4 electrically connects the two fourth sub-pixels 51 of the same fourth pixel unit 50. The third connection line A3 and the fourth connection line A4 are alternately arranged along the row direction X.
[0119] In the plan view of the array substrate 100, the first scan line G1 is located at the same side of the two second sub-pixels 31 of the same third pixel unit 40. The first scan line G1 is electrically connected with the adjacent third sub-pixel 41. The first scan line G1 is located at the same side of the two fourth sub-pixels 51 of the same fourth pixel unit 50, and the first scan line G1 is electrically connected with the adjacent fourth sub-pixel 51. The second scan line G2 and the second clock signal line CK2 are located between the two third sub-pixels 41 of the same third pixel unit 40. The second scan line G2 is electrically connected with the other third sub-pixel 41 of the same third pixel unit 40. The second scan line G2 and the second clock signal line CK2 are located between the two fourth sub-pixels 51 of the same fourth pixel unit 50. The second scan line G2 is electrically connected with the other fourth sub-pixel 51 of the same fourth pixel unit 50. The third demultiplexing transistor 23 is located between the first scan line G1 and the first clock signal line CK1. The fourth demultiplexing transistor 24 is located between the second scan line G2 and the second clock signal line CK2.
[0120] In the present embodiment, the input of the data signal of the third pixel unit 40 is controlled by the third demultiplexing transistor 23, and the input of the data signal of the fourth pixel unit 50 is controlled by the fourth demultiplexing transistor 24. The scheme that originally requires two data lines to respectively input data signals to the third pixel unit 40 and the fourth pixel unit 50 is replaced by only one second data line D2, and the data signals of the third pixel unit 40 and the fourth pixel unit 50 are respectively input through the third demultiplexing transistor 23 and the fourth demultiplexing transistor 24, thereby reducing the number of data lines and the number of data driving chips required for driving the array substrate 100 and the production cost.
[0121] Meanwhile, the first clock signal line CK1 can control the on-off of the first demultiplexing transistor 21 and the third demultiplexing transistor 23 simultaneously, and the second clock signal line CK2 can control the on-off of the second demultiplexing transistor 22 and the fourth demultiplexing transistor 24 simultaneously, thereby reducing the number of clock signal lines, lowering the production cost, improving the density of the sub-pixels, and thus improving the resolution of the display panel.
[0122] Optionally, referring to Figure 7 The second sub-pixel 31 further includes a second pixel electrode 311 and a second capacitor. The second pixel electrode 311 is electrically connected with the output terminal of the second switch transistor T2. The second capacitor is electrically connected with the output terminal of the second switch transistor T2. The third sub-pixel 41 further includes a third pixel electrode 411 and a third capacitor. The third pixel electrode 411 is electrically connected with the output terminal of the third switch transistor T3. The third capacitor is electrically connected with the output terminal of the third switch transistor T3. The fourth sub-pixel 51 further includes a fourth pixel electrode 511 and a fourth capacitor. The fourth pixel electrode 511 is electrically connected with the output terminal of the fourth switch transistor T4. The fourth capacitor is electrically connected with the output terminal of the fourth switch transistor T4.
[0123] The first pixel unit 10, the third pixel unit 40, the second pixel unit 30, and the fourth pixel unit 50 are arranged alternately along the row direction X. The first connection line A1, the third connection line A3, the second connection line A2, and the fourth connection line A4 are arranged alternately along the row direction X. The first demultiplexing transistor 21 and the third demultiplexing transistor 23 are arranged alternately along the row direction X. The second demultiplexing transistor 22 and the fourth demultiplexing transistor 24 are arranged alternately along the row direction X.
[0124] The array substrate 100 further includes a second data line D2. The second data line D2 extends along the column direction Y. The second data line D2 is electrically connected with the input terminal of the third demultiplexing transistor 23 and the input terminal of the fourth demultiplexing transistor 24, respectively. The second data line D2 is arranged alternately with the first data line D1 along the row direction X. In the plan view of the array substrate 100, the second data line D2 is located between the second pixel unit 30 and the fourth pixel unit 50.
[0125] The embodiment further improves the space utilization rate between two adjacent sub-pixels, thereby improving the sub-pixel density of the array substrate 100 and the resolution of the display panel, and thus improving the display effect of the display panel.
[0126] Optionally, referring to Figure 8, a first pixel unit 10, a first demultiplexing transistor 21 arranged corresponding to the first pixel unit 10, a first connecting line A1 arranged corresponding to the first pixel unit 10, a third pixel unit 40, a third demultiplexing transistor 23 arranged corresponding to the third pixel unit 40, a third connecting line A3 arranged corresponding to the third pixel unit 40, a second pixel unit 30, a second demultiplexing transistor 22 arranged corresponding to the second pixel unit 30, a second connecting line A2 arranged corresponding to the second pixel unit 30, a fourth pixel unit 50, a fourth demultiplexing transistor 24 arranged corresponding to the fourth pixel unit 50, and a fourth connecting line A4 arranged corresponding to the fourth pixel unit 50 form a minimum cycle unit 60. In the plan view of the array substrate 100, a plurality of minimum cycle units 60 are arranged in the pixel area PA in an array.
[0127] In the embodiment, a plurality of minimum cycle units 60 are arranged in the pixel area PA in an array, and the complete pixel area PA is obtained through the row direction X cycle and the column direction Y cycle. Under the premise of integrating the demultiplexing transistor in the pixel area PA, the phenomenon of cross-line overlap between the demultiplexing transistor and the switching transistor of the sub-pixel is avoided, the parasitic capacitance of the demultiplexing transistor and the switching transistor is reduced, and the display effect of the display panel is improved. The lower frame of the array substrate 100 is reduced, and the design of the narrow-frame display panel is realized.
[0128] Optionally, the pixel color corresponding to the first pixel electrode 113 is a first color. The pixel color corresponding to the second pixel electrode 311 is a second color. The pixel color corresponding to the third pixel electrode 411 is a third color. The pixel color corresponding to the fourth pixel electrode 511 is a second color. The first color, the second color, and the third color are all different.
[0129] Optionally, the first color is one of red, green, and blue. The second color is a second color of red, green, and blue. The third color is a third color of red, green, and blue.
[0130] In the embodiment, the same color is arranged corresponding to the pixel electrode in the same pixel unit, and the design of the minimum cycle unit 60 is matched, so that the colors of the pixel electrodes in the same column in the pixel area PA are the same, the complexity of the driving circuit is simplified, and the function similar to the column inversion (Stripe) architecture is realized.
[0131] It can be understood that the column inversion architecture of the array substrate 100 refers to that one data line is responsible for driving the same color pixels in the same column. The data line of the present application can drive the same color pixels in two columns respectively by cooperating with the two demultiplexing transistors connected thereto.
[0132] Optionally, please refer toFigure 9 In the first time period K1, the first data line D1 outputs a positive polarity voltage. The second data line D2 outputs a negative polarity voltage. The first clock signal line CK1 outputs a high potential. The second clock signal line CK2 outputs a low potential. The first demultiplexing transistor 21 is turned on. When the first switch transistor T1 is turned on, the first data line D1 is electrically connected with the corresponding first pixel electrode 113. The second demultiplexing transistor 22, the third demultiplexing transistor 23, and the fourth demultiplexing transistor 24 are turned off.
[0133] In the second time period K2, the first data line D1 outputs a positive polarity voltage. The second data line D2 outputs a negative polarity voltage. The first clock signal line CK1 outputs a low potential. The second clock signal line CK2 outputs a high potential. The second demultiplexing transistor 22 is turned on. When the second switch transistor T2 is turned on, the first data line D1 is electrically connected with the corresponding second pixel electrode 311. The first demultiplexing transistor 21, the third demultiplexing transistor 23, and the fourth demultiplexing transistor 24 are turned off.
[0134] In the third time period K3, the first data line D1 outputs a negative polarity voltage. The second data line D2 outputs a positive polarity voltage. The first clock signal line CK1 outputs a high potential. The second clock signal line CK2 outputs a low potential. The third demultiplexing transistor 23 is turned on. When the third switch transistor T3 is turned on, the second data line D2 is electrically connected with the corresponding third pixel electrode 411. The first demultiplexing transistor 21, the second demultiplexing transistor 22, and the fourth demultiplexing transistor 24 are turned off.
[0135] In the fourth time period K4, the first data line D1 outputs a negative polarity voltage. The second data line D2 outputs a positive polarity voltage. The first clock signal line CK1 outputs a low potential. The second clock signal line CK2 outputs a high potential. The fourth demultiplexing transistor 24 is turned on. When the fourth switch transistor T4 is turned on, the second data line D2 is electrically connected with the corresponding fourth pixel electrode 511. The first demultiplexing transistor 21, the second demultiplexing transistor 22, and the third demultiplexing transistor 23 are turned off.
[0136] In the present embodiment, by controlling the conduction of the pixel electrodes of different sub-pixels in different time periods, the rotation of liquid crystal is controlled, so that the light emission of different sub-pixels is realized.
[0137] The specific embodiments of the present application are described in detail above. The above-described embodiments disclosed in the present application are only preferred embodiments of the present application. Those skilled in the art can make many variations and improvements without departing from the concept of the present application. These variations and improvements are also within the scope of protection of the present application as defined by the claims.
Claims
1. An array substrate comprising a pixel region, characterized by, The array substrate comprises: a first pixel unit arranged in the pixel region and comprising a first switch transistor; a first scan line electrically connected to a gate of the first switch transistor; and a multiplexer arranged in the pixel region and comprising a first multiplexing transistor, an output of the first multiplexing transistor being electrically connected to an input of the first switch transistor; in a plan view of the array substrate, the first scan line is located on one side of the first pixel unit, and the first multiplexing transistor is located on a side of the first scan line away from the first pixel unit.
2. The array substrate of claim 1, wherein, The array substrate further comprises a first clock signal line, the first clock signal line being electrically connected to a gate of the first multiplexing transistor; in the plan view of the array substrate, the first clock signal line is located on a side of the first scan line away from the first pixel unit, and the first multiplexing transistor is located between the first clock signal line and the first scan line.
3. The array substrate of claim 2, wherein, The first scan line and the first clock signal line are arranged in the same layer; The first switch transistor comprises: a first gate arranged in the same layer as the first scan line and electrically connected to the first scan line; and a first source-drain metal layer arranged in a different layer from the first gate; The first multiplexing transistor comprises: a second gate arranged in the same layer as the first gate and spaced apart from the first gate, and electrically connected to the first clock signal line; and a second source-drain metal layer arranged in the same layer as the first source-drain metal layer and spaced apart from the first source-drain metal layer.
4. The array substrate of claim 2, wherein, The first pixel unit comprises two first sub-pixels arranged in a column direction, each of the first sub-pixels comprising the first switch transistor; The array substrate further comprises: a first connection line extending in the column direction, an output of the first multiplexing transistor being electrically connected to inputs of the first switch transistors of two first sub-pixels of the same first pixel unit through the first connection line; and a second scan line, the first scan line and the second scan line being arranged alternately in the column direction; in the plan view of the array substrate, the first scan line is located on the same side of the two first sub-pixels of the same first pixel unit and is electrically connected to adjacent first sub-pixels; the second scan line is located between the two first sub-pixels of the same first pixel unit and is electrically connected to another first sub-pixel of the same first pixel unit.
5. The array substrate of claim 4, wherein, The multiplexer further comprises a second multiplexing transistor; The array substrate further comprises: a second pixel unit arranged alternately with the first pixel unit in a row direction, the second pixel unit comprising two second sub-pixels arranged in a column direction, each of the first sub-pixels comprising a second switch transistor; a second connection line extending in the column direction, the second connection line being arranged alternately with the first connection line in the row direction, an output of the second multiplexing transistor being electrically connected to inputs of the second switch transistors of two second sub-pixels of the same second pixel unit through the second connection line; and a second clock signal line electrically connected to a gate of the second multiplexing transistor. In a plan view of the array substrate, the first scan line is located on the same side of two second sub-pixels of the same second pixel unit and is electrically connected with adjacent second sub-pixels; The second scan line and the second clock signal line are located between two second sub-pixels of the same second pixel unit, and the second scan line is electrically connected with another second sub-pixel of the same second pixel unit; The second demultiplexing transistor is located between the second scan line and the second clock signal line.
6. The array substrate of claim 5, wherein, The first clock signal line, the first scan line, the second clock signal line and the second scan line are alternately arranged along the column direction.
7. The array substrate of claim 5, wherein, The array substrate further comprises a first data line, the first data line extends along the column direction, and the first data line is electrically connected with the input pole of the first demultiplexing transistor and the input pole of the second demultiplexing transistor, respectively; In a plan view of the array substrate, the first data line is located on the side of the first pixel unit away from the second pixel unit.
8. The array substrate of claim 7, wherein, The multiplexer further comprises a third demultiplexing transistor and a fourth demultiplexing transistor; The array substrate further comprises: A third pixel unit comprising two third sub-pixels arranged along the column direction, each of the third sub-pixels comprising a third switch transistor; A third connection line extending along the column direction, the third connection line being electrically connected with the output pole of the third demultiplexing transistor, and the third connection line electrically connecting two third sub-pixels of the same third pixel unit; A fourth pixel unit comprising two fourth sub-pixels arranged along the column direction, each of the fourth sub-pixels comprising a fourth switch transistor, the third pixel unit and the fourth pixel unit being alternately arranged along the row direction; A fourth connection line extending along the column direction, the fourth connection line being electrically connected with the output pole of the fourth demultiplexing transistor, and the fourth connection line electrically connecting two fourth sub-pixels of the same fourth pixel unit, the third connection line and the fourth connection line being alternately arranged along the row direction; In a plan view of the array substrate, the first scan line is located on the same side of two second sub-pixels of the same third pixel unit and is electrically connected with adjacent third sub-pixels; The first scan line is located on the same side of two fourth sub-pixels of the same fourth pixel unit and is electrically connected with adjacent fourth sub-pixels; The second scan line and the second clock signal line are located between two third sub-pixels of the same third pixel unit, and the second scan line is electrically connected with another third sub-pixel of the same third pixel unit; The second scan line and the second clock signal line are located between two fourth sub-pixels of the same fourth pixel unit, and the second scan line is electrically connected with another fourth sub-pixel of the same fourth pixel unit; The third demultiplexing transistor is located between the first scan line and the first clock signal line. The fourth demultiplexing transistor is located between the second scan line and the second clock signal line.
9. The array substrate of claim 8, wherein, The first sub-pixel further comprises a first pixel electrode, which is electrically connected with the output terminal of the first switch transistor. The second sub-pixel further comprises a second pixel electrode, which is electrically connected with the output terminal of the second switch transistor. The third sub-pixel further comprises a third pixel electrode, which is electrically connected with the output terminal of the third switch transistor. The fourth sub-pixel further comprises a fourth pixel electrode, which is electrically connected with the output terminal of the fourth switch transistor. The first pixel unit, the third pixel unit, the second pixel unit and the fourth pixel unit are alternately arranged along the row direction. The first connection line, the third connection line, the second connection line and the fourth connection line are alternately arranged along the row direction. The first demultiplexing transistor and the third demultiplexing transistor are alternately arranged along the row direction. The second demultiplexing transistor and the fourth demultiplexing transistor are alternately arranged along the row direction. The array substrate further comprises a second data line, which extends along the column direction, and is electrically connected with the input terminal of the third demultiplexing transistor and the input terminal of the fourth demultiplexing transistor, respectively. In the plan view of the array substrate, the second data line is located between the second pixel unit and the fourth pixel unit.
10. The array substrate of claim 9, wherein, One of the first pixel unit, one of the first demultiplexing transistor corresponding to the first pixel unit, one of the first connection line corresponding to the first pixel unit, one of the third pixel unit, one of the third demultiplexing transistor corresponding to the third pixel unit, one of the third connection line corresponding to the third pixel unit, one of the second pixel unit, one of the second demultiplexing transistor corresponding to the second pixel unit, one of the second connection line corresponding to the second pixel unit, one of the fourth pixel unit, one of the fourth demultiplexing transistor corresponding to the fourth pixel unit and one of the fourth connection line corresponding to the fourth pixel unit form one minimum cycle unit. In the plan view of the array substrate, a plurality of the minimum cycle units are arranged in the pixel area.
11. The array substrate of claim 9, wherein, In the first time period, the first data line outputs a positive polarity voltage, the second data line outputs a negative polarity voltage, the first clock signal line outputs a high potential, the second clock signal line outputs a low potential, the first demultiplexing transistor is opened, the first data line is electrically connected with the first pixel electrode, and the second demultiplexing transistor, the third demultiplexing transistor and the fourth demultiplexing transistor are closed. In the second time period, the first data line outputs a positive polarity voltage, the second data line outputs a negative polarity voltage, the first clock signal line outputs a low potential, the second clock signal line outputs a high potential, the second demultiplexing transistor is turned on, the first data line is electrically connected with the second pixel electrode, and the first demultiplexing transistor, the third demultiplexing transistor and the fourth demultiplexing transistor are turned off; In the third time period, the first data line outputs a negative polarity voltage, the second data line outputs a positive polarity voltage, the first clock signal line outputs a high potential, the second clock signal line outputs a low potential, the third demultiplexing transistor is turned on, the second data line is electrically connected with the third pixel electrode, and the first demultiplexing transistor, the second demultiplexing transistor and the fourth demultiplexing transistor are turned off; In the fourth time period, the first data line outputs a negative polarity voltage, the second data line outputs a positive polarity voltage, the first clock signal line outputs a low potential, the second clock signal line outputs a high potential, the fourth demultiplexing transistor is turned on, the second data line is electrically connected with the fourth pixel electrode, and the first demultiplexing transistor, the second demultiplexing transistor and the third demultiplexing transistor are turned off.
12. The array substrate of claim 9, wherein, The pixel color corresponding to the first pixel electrode is a first color, the pixel color corresponding to the second pixel electrode is a second color, the pixel color corresponding to the third pixel electrode is a third color, and the pixel color corresponding to the fourth pixel electrode is the second color. The first color, the second color and the third color are all different.
13. A display panel, characterized by An array substrate comprising any one of claims 1-12.