Bidirectional switching radio frequency power amplifier

Abstract

A bidirectional switching radio frequency power amplifier comprises two input and output radio frequency ports, two single-pole double-throw switches, an uplink and a downlink. The microcontroller unit controls the switching state of the two single-pole double-throw switches according to a feedback signal of the power detection module, and dynamically adjusts the gain of the power amplifier and the low-noise amplifier to realize automatic gain control: when the power of an input signal is lower than a set threshold value, the maximum gain amplification is started; and when the input signal power exceeds a set threshold value, controlling the output signal power to be a fixed value. Compared with the prior art, the device is an independent device and is provided with an input radio frequency port and an output radio frequency port, and the two radio frequency ports can be shared by input and output and can amplify signals. The bidirectional signal amplification function is equivalent, the system also has an automatic gain control function, if the input signal is small, the system only amplifies the input signal, and if the input signal is greater than a certain value, the input signal is output at a fixed value.

Description

TECHNICAL FIELD

[0001] The utility model relates to radio frequency amplification circuit technical field, especially in two -way switching's radio frequency power amplifier. BACKGROUND

[0002] Bidirectional RF switchable amplifier (BRFSA) is the core component of wireless communication system, which is used to realize time division multiplexing of transceiver channel, and plays a key role in TDD (time division duplex) system (such as 5G NR, Wi-Fi 6E), full duplex communication and radar system. Its core function is to share the same radio frequency link by quickly switching the transceiver state, thereby reducing system complexity and cost.

[0003] The existing BRFSA technology has the following technical defects in the high frequency band, high throughput and wide temperature range scenarios:

[0004] 1. Speed-efficiency trade-off: fast switching and low power consumption are difficult to achieve;

[0005] 2. Isolation-bandwidth contradiction: high isolation design leads to bandwidth compression;

[0006] 3. Integration-cost constraint: process limitations increase the implementation cost of complex systems.

[0007] Therefore, there is an urgent need for a new type of radio frequency power amplifier to solve the above technical problems. SUMMARY

[0008] In view of the above defects of the prior art, the utility model provides a bidirectional switching radio frequency power amplifier as follows:

[0009] The technical scheme of the utility model is as follows:

[0010] A bidirectional switching radio frequency power amplifier, comprising: input and output radio frequency ports (I01, I02), a first single-pole double-throw switch (SPDT1), a second single-pole double-throw switch (SPDT2), a receiving channel (RX1, RX2), an uplink and a downlink;

[0011] The input and output radio frequency ports (I01, I02) are connected to the uplink and the downlink through the first single-pole double-throw switch (SPDT1) and the second single-pole double-throw switch (SPDT2) respectively, realizing bidirectional peer amplification of radio frequency signals, and the receiving channel (RX1, RX2) is connected to the first single-pole double-throw switch (SPDT1) and the second single-pole double-throw switch (SPDT2) through a filter;

[0012] The uplink and the downlink each comprise an attenuator, a low noise amplifier (LNA), a filter, an amplifier, a power divider, and a power amplifier (PA) connected in sequence, and the power divider is further connected in sequence with a power detection module and a micro controller unit (MCU) for detecting the power value of an input signal in real time;

[0013] The micro controller unit (MCU) controls the switching state of the first single-pole double-throw switch (SPDT1) and the second single-pole double-throw switch (SPDT2) according to the feedback signal of the power detection module, and dynamically adjusts the gain of the power amplifier (PA) and the low noise amplifier (LNA) to realize automatic gain control: when the input signal power is lower than a set threshold, the maximum gain amplification is enabled; when the input signal power exceeds the set threshold, the output signal power is controlled to be a fixed value.

[0014] Preferably, the filters are each a band-pass filter with a passband frequency range of 400-500 MHz and an out-of-band rejection greater than 40 dB.

[0015] Preferably, the micro controller unit (MCU) adjusts the switching logic of the SPDT1 and the SPDT2 according to the instantaneous change of the input signal power to ensure that the uplink and downlink switching time is less than 800 microseconds.

[0016] Preferably, the power detection module comprises a logarithmic detector and a high-speed analog-to-digital converter, has a dynamic range of -70-30 dBm, and a measurement accuracy better than ±0.5 dB.

[0017] Preferably, the power amplifier (PA) adopts a silicon-based laterally diffused metal oxide semiconductor (LDMOS) process, has a third-order intermodulation intercept point (IP3) greater than 45 dBm, and meets the linear requirement that IMD3 is not less than 45 dBc.

[0018] Preferably, the first single-pole double-throw switch (SPDT1) and the second single-pole double-throw switch (SPDT2) are PIN diode switches with a switching time less than 500 nanoseconds and a maximum port withstand power of 30 dBm.

[0019] Compared with the prior art, the utility model has the following beneficial effects:

[0020] The utility model discloses a bidirectional switching radio frequency power amplifier, which is an independent device, has two radio frequency ports for input and output, and can input and output commonly and amplify signals. The bidirectional amplification function of signals is equal, and the system also has an automatic gain control function. If the input signal is small, the system only amplifies, and if the input signal is greater than a certain value, the system outputs a fixed value. The utility model can quickly switch the amplification link mode, and the working bandwidth is not affected. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 The utility model discloses a bidirectional switching radio frequency power amplifier's schematic diagram;

[0022] Figure 2 The utility model discloses a downlink circuit schematic diagram;

[0023] Figure 3 The utility model discloses an uplink circuit schematic diagram;

[0024] Figure 4 The utility model discloses a first single-pole double-throw switch and second single-pole double-throw switch's circuit schematic diagram;

[0025] Figure 5 The utility model discloses a microcontroller unit's circuit schematic diagram;

[0026] Figure 6 The utility model discloses a power detection module's circuit schematic diagram. DETAILED DESCRIPTION

[0027] The utility model will be clearly and completely described below in conjunction with the drawings in the embodiment of the utility model.

[0028] As Figures 1-6As shown, a bidirectional switching radio frequency power amplifier includes: input and output radio frequency ports I01, I02, a first single-pole double-throw switch SPDT1, a second single-pole double-throw switch SPDT2, a receiving channel RX1, RX2, an uplink and a downlink; the input and output radio frequency ports I01, I02 are connected to the uplink and the downlink through the first single-pole double-throw switch SPDT1 and the second single-pole double-throw switch SPDT2 respectively, realizing bidirectional peer-to-peer amplification of radio frequency signals, and the receiving channel RX1, RX2 is connected to the first single-pole double-throw switch SPDT1 and the second single-pole double-throw switch SPDT2 through a filter; the uplink and the downlink each include an attenuator, a low noise amplifier LNA, a filter, an amplifier, a power divider, and a power amplifier PA connected in sequence, and the power divider further has a power detection module and a microcontroller unit MCU connected in sequence, for detecting a power value of an input signal in real time; the microcontroller unit MCU controls switching states of the first single-pole double-throw switch SPDT1 and the second single-pole double-throw switch SPDT2 according to a feedback signal of the power detection module, and dynamically adjusts gains of the power amplifier PA and the low noise amplifier LNA, realizing automatic gain control; when the input signal power is lower than a set threshold, maximum gain amplification is enabled; when the input signal power exceeds the set threshold, the output signal power is controlled to be a fixed value. The filters are each a band-pass filter, with a passband frequency range of 400MHz to 500MHz and an out-of-band suppression greater than 40dB. The microcontroller unit MCU adjusts switching logic of the SPDT1 and the SPDT2 according to instantaneous changes of the input signal power, ensuring that uplink and downlink switching time is less than 800 microseconds. The power detection module includes a logarithmic detector and a high-speed analog-to-digital converter, with a dynamic range covering -70dBm to 30dBm and a measurement accuracy better than ±0.5dB. The power amplifier PA adopts a silicon-based laterally diffused metal oxide semiconductor LDMOS process, with a third-order intercept point (IP3) greater than 45dBm, meeting linear requirements that a third-order intermodulation distortion (IMD3) is not less than 45dBc. The first single-pole double-throw switch SPDT1 and the second single-pole double-throw switch SPDT2 are PIN diode switches, with a switching time less than 500 nanoseconds and a maximum bearing power of 30dBm at a port.

[0029] The amplifier includes a transmitting link and a receiving link, and dynamically switches paths through single-pole double-throw switches SPDT1, SPDT2, which are connected as follows:

[0030] Uplink:

[0031] Signal input: a radio frequency signal enters from an input port I01, passes through a first filter (filtering out out-of-band noise)→ a power divider (dividing into two paths)→ a power amplifier (PA) (main path amplification, gain 30dB)→ a second filter (harmonic suppression)→ SPDT2→ an output port IO2 in sequence.

[0032] Power detection: The sub-path signal of the power divider is input to the power detection module, and the input power (range -65dBm~10dBm) is monitored in real time.

[0033] Downlink:

[0034] Signal input: The radio frequency signal enters from the port IO2, and sequentially passes through the filter→low noise amplifier LNA (gain 30dB, noise coefficient <3dB)→power divider→RX2 receiving channel or return link.

[0035] Feedback control: Part of the signal is adjusted by the attenuator and fed back to the MCU by the power detection module for dynamic gain adjustment.

[0036] The following is the working mode and control logic of the amplifier of the utility model:

[0037] 1) Mode A: initialization mode

[0038] Start-up process: After the system is powered on or reset, the MCU loads the preset program and defaults to mode C (automatic working mode).

[0039] Initial configuration:

[0040] The digital attenuator is set to the maximum attenuation (such as -31.5dB), and the initial signal strength is reduced;

[0041] The single-pole double-throw switch SPDT1, SPDT2 is connected to the uplink (I01→Tx link) by default.

[0042] 2) Mode B: external control mode

[0043] Control method: Through the RS-485 interface, the external PC can perform the following operations:

[0044] Parameter setting: Manually configure the state of the radio frequency switch and adjust the attenuation value of the attenuator;

[0045] Data reading: Get the power detection voltage (such as IPDV1~IPDV5) and the limiter level indication;

[0046] Calibration configuration: Set the detection threshold under different input powers (such as IPDV1 corresponds to -70dBm).

[0047] Working process:

[0048] The MCU switches the uplink and downlink at a period of 100us, detects the power difference under the same attenuation state, and assists external debugging.

[0049] 3) Mode C: automatic working mode (main mode)

[0050] Core objective: automatically identify signal flow direction and lock the stronger link.

[0051] Workflow:

[0052] Initialization detection: attenuator set to maximum attenuation, SPDT1 switch to uplink (I01→Tx), detect 50us power value Pdout1;

[0053] Threshold judgment:

[0054] If Pdout1>IPDV1(-70dBm threshold), switch to downlink (IO2→Rx) to detect Pdout2, compare and lock the stronger signal channel, enter mode D;

[0055] If Pdout1<IPDV1, attenuator set to 0 attenuation, re-detect; if still below the threshold, switch to downlink detection.

[0056] Cyclic detection: when there is no valid signal, continuously poll between uplink and downlink.

[0057] 4) Mode D: single channel operation mode

[0058] Core objective: maximize gain in locked link while ensuring output power ≤15dBm.

[0059] Dynamic gain adjustment:

[0060] Power interpolation calculation: according to power detection value (such as OPDV1=15dBm, OPDV2=-5dBm, OPDV3=-30dBm), interpolate the current output power △P;

[0061] Attenuator adjustment: adjust the attenuator by 0.7 times of △P (such as △P=3dB→adjust attenuation value 2.1dB), gradually approach the target power;

[0062] Termination condition: stop when the adjustment step <0.5dB (minimum resolution of digital attenuator) or the output power is stable at 15dBm;

[0063] Signal loss processing: if there is no signal for 50us, return to mode C to re-scan.

[0064] The utility model has the following beneficial effects:

[0065] 1) Fast switching mechanism:

[0066] Hardware support: use PIN diode SPDT switch (switching time <500ns) and high-speed MCU (instruction cycle <100ns);

[0067] Algorithm optimization: adaptive prediction algorithm reduces switching delay, ensures uplink and downlink switching time <1ms.

[0068] 2) Automatic gain control (AGC):

[0069] Threshold trigger: when the input signal is >-15dBm, the MCU dynamically adjusts the attenuator to fix the output power at 15dBm;

[0070] Overload protection: when the input signal is >10dBm, the MCU immediately cuts off SPDT1, isolates the rear-end circuit, and prevents damage.

[0071] 3) Linearity and stability:

[0072] Linear guarantee: PA uses LDMOS technology (IP3>45dBm), combined with a bandpass filter (out-of-band rejection>40dB), to ensure IMD3≥45dBc;

[0073] Temperature compensation: LNA and PA have built-in temperature sensors, and the MCU adjusts the bias current in real time to suppress gain drift (fluctuation <±0.5dB).

[0074] 4) Interface and compatibility:

[0075] RF interface: SMA-F type interface, supporting 400MHz-500MHz frequency band, VSWR <1.5:1;

[0076] Power supply interface: DCX-005-R standard interface (12V / 1A), suitable for industrial equipment.

[0077] According to the structure and working principle of the amplifier of the utility model, the bidirectional switching radio frequency power amplifier of the utility model is an independent device, has two radio frequency ports of input and output, the two radio frequency ports can input and output commonly, and perform signal amplification. The bidirectional amplification function of the signal is equal, the system also has an automatic gain control function, if the input signal is small, the system only performs amplification, if the input signal is greater than a certain value, a fixed value is outputted; the utility model can quickly switch the amplification link mode, and the working bandwidth is not affected.

Claims

1. A bidirectional switched radio frequency power amplifier, characterized by, The application relates to a radio frequency (RF) amplifier, which comprises: input / output RF ports (I01, I02), first single-pole double-throw switches (SPDT1), second single-pole double-throw switches (SPDT2), receiving channels (RX1, RX2), uplinks and downlinks; the input / output RF ports (I01, I02) are connected with the uplinks and downlinks through the first single-pole double-throw switches (SPDT1) and the second single-pole double-throw switches (SPDT2) respectively, bidirectional peer-to-peer amplification of RF signals is realized, and the receiving channels (RX1, RX2) are connected with the first single-pole double-throw switches (SPDT1) and the second single-pole double-throw switches (SPDT2) through filters; the uplinks and the downlinks each comprise an attenuator, a low noise amplifier (LNA), a filter, an amplifier, a power divider and a power amplifier (PA) which are sequentially connected, and the power divider is further sequentially connected with a power detection module and a microcontroller unit (MCU) for detecting the power value of an input signal in real time; the microcontroller unit (MCU) controls the switching state of the first single-pole double-throw switches (SPDT1) and the second single-pole double-throw switches (SPDT2) according to the feedback signal of the power detection module, dynamically adjusts the gain of the power amplifier (PA) and the low noise amplifier (LNA), and realizes automatic gain control: when the input signal power is lower than a set threshold, the maximum gain amplification is enabled; when the input signal power is higher than the set threshold, the output signal power is controlled to be a fixed value.

2. The bidirectionally switched RF power amplifier of claim 1, wherein, The filters are all bandpass filters, the passband frequency range is 400-500 MHz, and the out-of-band suppression is greater than 40 dB.

3. The bidirectionally switched RF power amplifier of claim 1, wherein, The microcontroller unit (MCU) adjusts the switching logic of the SPDT1 and the SPDT2 according to the instantaneous change of the input signal power, and ensures that the uplink and downlink switching time is less than 800 microseconds.

4. The bidirectionally switched RF power amplifier of claim 1, wherein, The power detection module comprises a logarithmic detector and a high-speed analog-to-digital converter, the dynamic range covers-70 dBm to 30 dBm, and the measurement accuracy is better than + / -0.5 dB.

5. The bidirectionally switched RF power amplifier of claim 1, wherein, The power amplifier (PA) adopts a silicon-based lateral diffusion metal oxide semiconductor (LDMOS) process, the third-order intercept point (IP3) is greater than 45 dBm, and the linear requirement that the IMD3 is not less than 45 dBc is met.

6. The bidirectionally switched RF power amplifier of claim 1, wherein, The first single-pole double-throw switches (SPDT1) and the second single-pole double-throw switches (SPDT2) are PIN diode switches, the switching time is less than 500 nanoseconds, and the maximum bearing power of the ports is 30 dBm.

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