Display substrate and display device

Abstract

According to the display substrate and the display device, the display substrate comprises a plurality of sub-pixels, at least one sub-pixel comprises a switching transistor, the switching transistor comprises an active pattern, a gate electrode, a first electrode and a second electrode, the gate electrode of the switching transistor comprises a gate main body part and a gate connecting part which are arranged in the first direction and connected with each other, at least part of the gate connecting part extends in the first direction, the length of the gate body part in the second direction is larger than that of the gate connecting part in the second direction, and the orthographic projection of the active pattern of the at least one switching transistor on the substrate is at least partially overlapped with the orthographic projection of the gate body part on the substrate. And the orthographic projection of the data signal line connected with at least one switch transistor on the substrate is at least partially overlapped with the orthographic projection of the gate connection part on the substrate.

Description

Technical Field

[0001] This utility model relates to, but is not limited to, the field of display technology, specifically to a display substrate and a display device. Background Technology

[0002] Liquid crystal displays (LCDs), as flat panel display devices, are increasingly being used in high-performance display fields due to their small size, low power consumption, no radiation, and relatively low manufacturing cost. In recent years, three-dimensional display technology has developed rapidly and has become a research hotspot. Utility Model Content

[0003] This utility model provides a display substrate and a display device, which reduces the parasitic capacitance of the display substrate and improves the display effect of the display substrate.

[0004] This disclosure provides a display substrate and a display device.

[0005] In a first aspect, this disclosure provides a display substrate, comprising: a substrate and data signal lines, scan signal lines disposed on the substrate, and a plurality of sub-pixels defined by the intersection of the data signal lines and the scan signal lines, wherein at least one sub-pixel comprises: a switching transistor, a pixel electrode, and a common electrode, wherein the switching transistor comprises: an active pattern, a gate electrode, a first electrode, and a second electrode, the gate electrode of the switching transistor is connected to the scan signal lines, the first electrode of the switching transistor is connected to the data signal lines, and the second electrode of the switching transistor is connected to the pixel electrode;

[0006] The gate electrode of the switching transistor includes: a gate body portion and a gate connection portion arranged along the first direction and connected to each other, wherein the gate connection portion extends at least partially along the first direction, and the length of the gate body portion along the second direction is greater than the length of the gate connection portion along the second direction, wherein the first direction is the extension direction of the scan signal line, and the second direction is the extension direction of the data signal line;

[0007] The orthographic projection of the active pattern of at least one switching transistor on the substrate at least partially overlaps with the orthographic projection of the gate body portion on the substrate, and the orthographic projection of the data signal line connected to at least one switching transistor on the substrate at least partially overlaps with the orthographic projection of the gate connection portion on the substrate.

[0008] In an exemplary embodiment, on a plane parallel to the display substrate, for at least one switching transistor, the boundaries of the active pattern include: a first boundary, a second boundary, a third boundary, and a fourth boundary, and the boundaries of the gate body include: a fifth boundary and a sixth boundary.

[0009] Wherein, the first boundary is the boundary of the active pattern extending along the second direction and close to the data signal line connected to the switching transistor; the second boundary is the boundary of the active pattern extending along the second direction and far away from the data signal line connected to the switching transistor; the third boundary and the fourth boundary are two oppositely arranged boundaries of the active pattern extending along the first direction; the fifth boundary is the boundary of the gate body extending along the second direction and close to the data signal line connected to the switching transistor; and the sixth boundary is the boundary of the gate body extending along the second direction and far away from the data signal line connected to the switching transistor.

[0010] The orthographic projections of the first boundary and the second boundary onto the substrate are located within the range of the orthographic projection of the gate body onto the substrate;

[0011] Alternatively, the orthographic projection of the first target boundary on the substrate and the orthographic projection of the gate electrode of the switching transistor on the substrate do not overlap, and the orthographic projection of the second target boundary on the substrate is within the range of the orthographic projection of the gate body portion on the substrate. The first target boundary is one of the first boundary and the second boundary, and the second target boundary is the other of the first boundary and the second boundary.

[0012] Alternatively, the orthographic projections of the first boundary and the second boundary on the substrate do not overlap with the orthographic projections of the gate electrode of the switching transistor on the substrate, and the orthographic projections of at least one of the third boundary and the fourth boundary on the substrate at least partially overlap with the orthographic projections of the fifth boundary and the sixth boundary on the substrate.

[0013] The active pattern of the switching transistor has a length along the second direction ranging from 3 micrometers to 10 micrometers.

[0014] In an exemplary embodiment, at least one sub-pixel further includes: a first connection portion, wherein the first electrode of the switching transistor is connected to a data signal line through the first connection portion;

[0015] The first electrode of the switching transistor extends along the second direction, the first connection portion extends along the first direction, and the length of the first electrode of the switching transistor along the second direction is greater than the length of the active pattern along the second direction and greater than the length of the first connection portion along the second direction.

[0016] The length of the first connecting portion along the first direction is in the range of 2 micrometers to 20 micrometers.

[0017] In an exemplary embodiment, when the orthographic projections of the first boundary and the second boundary on the substrate are respectively within the range of the orthographic projection of the gate body portion on the substrate, the orthographic projection of the first pole of the switching transistor on the substrate is within the range of the orthographic projection of the gate body portion on the substrate, and at least partially overlaps with the orthographic projections of the first boundary, the third boundary and the fourth boundary on the substrate. The orthographic projection of the first connection portion on the substrate overlaps with the orthographic projection of the fifth boundary on the substrate, and there is no overlap with the orthographic projection of the gate connection portion on the substrate.

[0018] In an exemplary embodiment, the orthographic projection of the first target boundary on the substrate and the orthographic projection of the gate electrode of the switching transistor on the substrate do not overlap. The orthographic projection of the second target boundary on the substrate is within the range of the orthographic projection of the gate body portion on the substrate. When the first target boundary is the first boundary, the orthographic projection of the first electrode of the switching transistor on the substrate is within the range of the orthographic projection of the first boundary, the third boundary, the fourth boundary, and the fifth boundary on the substrate. The orthographic projection of the first connection portion on the substrate and the orthographic projection of the gate electrode of the switching transistor on the substrate do not overlap.

[0019] The orthographic projection of the first target boundary on the substrate does not overlap with the orthographic projection of the gate electrode of the switching transistor on the substrate. The orthographic projection of the second target boundary on the substrate is within the range of the orthographic projection of the gate body portion of the switching transistor on the substrate. When the first target boundary is the second boundary, the orthographic projection of the first electrode of the switching transistor on the substrate is within the range of the orthographic projection of the gate body portion on the substrate, and at least partially overlaps with the orthographic projections of the first boundary, the third boundary, and the fourth boundary on the substrate. The orthographic projection of the first connection portion on the substrate overlaps with the orthographic projection of the fifth boundary on the substrate, and does not overlap with the orthographic projection of the gate connection portion on the substrate.

[0020] In an exemplary embodiment, when the orthographic projections of the first boundary and the second boundary on the substrate do not overlap with the orthographic projections of the gate body portion on the substrate, the orthographic projection of the first electrode of the switching transistor on the substrate at least partially overlaps with the orthographic projections of the first boundary, the third boundary, the fourth boundary and the fifth boundary on the substrate, and the orthographic projection of the first connection portion on the substrate does not overlap with the orthographic projection of the gate electrode of the switching transistor on the substrate.

[0021] Alternatively, the orthographic projection of the first electrode of the switching transistor on the substrate at least partially overlaps with the orthographic projections of the first boundary, the third boundary, and the fourth boundary on the substrate, and the orthographic projection of the first connection portion on the substrate does not overlap with the orthographic projections of the fifth boundary and the gate electrode of the switching transistor on the substrate.

[0022] In an exemplary embodiment, the first electrode of the switching transistor extends along a first direction, and the length of the first electrode of the switching transistor along a second direction is less than the length of the active pattern along the second direction.

[0023] The length of the first electrode of the switching transistor along the second direction is in the range of 2 micrometers to 5 micrometers.

[0024] In an exemplary embodiment, when the orthographic projections of the first boundary and the second boundary on the substrate are respectively within the range of the orthographic projection of the gate body portion on the substrate, or when the orthographic projection of the first target boundary on the substrate does not overlap with the orthographic projection of the gate electrode of the switching transistor on the substrate, and the orthographic projection of the second target boundary on the substrate is within the range of the orthographic projection of the gate body portion of the switching transistor on the substrate, the orthographic projection of the first electrode of the switching transistor on the substrate at least partially overlaps with the orthographic projections of the first boundary and the fifth boundary on the substrate, and does not overlap with the orthographic projections of the third boundary and the fourth boundary on the substrate.

[0025] In an exemplary embodiment, when the orthographic projections of the first boundary and the second boundary on the substrate do not overlap with the orthographic projection of the gate electrode of the switching transistor on the substrate, the orthographic projection of the first electrode of the switching transistor on the substrate at least partially overlaps with the orthographic projections of the first boundary and the fifth boundary on the substrate, and does not overlap with the orthographic projections of the third boundary, the fourth boundary and the gate connection portion on the substrate, respectively. Alternatively, the orthographic projection of the first electrode of the switching transistor on the substrate at least partially overlaps with the orthographic projection of the first boundary on the substrate, and does not overlap with the orthographic projections of the third boundary, the fourth boundary, the fifth boundary and the gate electrode of the switching transistor on the substrate, respectively.

[0026] In an exemplary embodiment, at least one sub-pixel further includes: a second connecting portion and an electrode connecting block, the second connecting portion and the electrode connecting block being arranged along a first direction, the second electrode of the switching transistor being connected to the electrode connecting block through the second connecting portion, and the electrode connecting block being connected to the pixel electrode;

[0027] The second electrode of the switching transistor extends along a second direction, the second connection portion extends along a first direction, the length of the second electrode of the switching transistor along the second direction is greater than the length of the active pattern along the second direction, and greater than the length of at least one structure of the second connection portion and the electrode connection block along the second direction, the length of the electrode connection block along the second direction is greater than the length of the second connection portion along the second direction;

[0028] The length of the second connecting portion along the first direction is in the range of 2 micrometers to 20 micrometers.

[0029] In an exemplary embodiment, when the orthographic projections of the first boundary and the second boundary on the substrate are respectively within the range of the orthographic projection of the gate body portion on the substrate, the orthographic projection of the second pole of the switching transistor on the substrate is within the range of the orthographic projection of the gate body portion on the substrate, and at least partially overlaps with the orthographic projections of the second boundary, the third boundary and the fourth boundary on the substrate. The orthographic projection of the second connection portion on the substrate overlaps with the orthographic projection of the sixth boundary on the substrate, and there is no overlap with the orthographic projection of the gate connection portion on the substrate.

[0030] In an exemplary embodiment, the orthographic projection of the first target boundary on the substrate does not overlap with the orthographic projection of the gate electrode of the switching transistor on the substrate. The orthographic projection of the second target boundary on the substrate is within the range of the orthographic projection of the gate body portion of the switching transistor on the substrate. When the first target boundary is the first boundary, the orthographic projection of the second electrode of the switching transistor on the substrate is within the range of the orthographic projection of the gate body portion on the substrate, and at least partially overlaps with the orthographic projections of the second boundary, the third boundary, and the fourth boundary on the substrate. The orthographic projection of the second connection portion on the substrate overlaps with the orthographic projection of the sixth boundary on the substrate, and does not overlap with the orthographic projection of the gate connection portion on the substrate.

[0031] The orthographic projection of the first target boundary on the substrate does not overlap with the orthographic projection of the gate electrode of the switching transistor on the substrate. The orthographic projection of the second target boundary on the substrate is within the range of the orthographic projection of the gate body portion of the switching transistor on the substrate. When the first target boundary is the second boundary, the orthographic projection of the second electrode of the switching transistor on the substrate at least partially overlaps with the orthographic projections of the second boundary, the third boundary, the fourth boundary, and the sixth boundary on the substrate. The orthographic projection of the second connection portion on the substrate does not overlap with the orthographic projection of the gate electrode of the switching transistor on the substrate.

[0032] In an exemplary embodiment, when the orthographic projections of the first boundary and the second boundary on the substrate do not overlap with the orthographic projection of the gate electrode of the switching transistor on the substrate, the orthographic projection of the second electrode of the switching transistor on the substrate at least partially overlaps with the orthographic projections of the second boundary, the third boundary, the fourth boundary, and the sixth boundary on the substrate, and the orthographic projection of the second connection portion on the substrate does not overlap with the orthographic projection of the gate electrode of the switching transistor on the substrate; or, the orthographic projection of the second electrode of the switching transistor on the substrate at least partially overlaps with the orthographic projections of the second boundary, the third boundary, and the fourth boundary on the substrate, and does not overlap with the orthographic projection of the sixth boundary on the substrate, and the orthographic projection of the second connection portion on the substrate does not overlap with the orthographic projections of the sixth boundary and the gate electrode of the switching transistor on the substrate, respectively.

[0033] In an exemplary embodiment, at least one sub-pixel further includes: an electrode connection block, the second electrode of a switching transistor and the electrode connection block are arranged along a first direction, the second electrode of the switching transistor is connected to the electrode connection block, and the electrode connection block is electrically connected to a pixel electrode.

[0034] The second electrode of the switching transistor extends along the first direction, and the length of the second electrode of the switching transistor along the second direction is less than the length of the active pattern of the switching transistor along the second direction, and less than the length of the electrode connection block along the second direction.

[0035] The length of the second electrode of the switching transistor along the second direction is in the range of 2 micrometers to 5 micrometers.

[0036] In an exemplary embodiment, when the orthographic projections of the first boundary and the second boundary on the substrate are respectively within the range of the orthographic projection of the gate body portion on the substrate, or when the orthographic projection of the first target boundary on the substrate does not overlap with the orthographic projection of the gate electrode of the switching transistor on the substrate, and the orthographic projection of the second target boundary on the substrate is within the range of the orthographic projection of the gate body portion of the switching transistor on the substrate, the orthographic projection of the second electrode of the switching transistor on the substrate at least partially overlaps with the orthographic projections of the second boundary and the sixth boundary on the substrate, and does not overlap with the orthographic projections of the third boundary and the fourth boundary on the substrate.

[0037] In an exemplary embodiment, when the orthographic projections of the first boundary and the second boundary on the substrate do not overlap with the orthographic projection of the gate electrode of the switching transistor on the substrate, the orthographic projection of the second electrode of the switching transistor on the substrate at least partially overlaps with the orthographic projections of the second boundary and the sixth boundary on the substrate, and does not overlap with the orthographic projections of the third boundary, the fourth boundary and the gate connection portion on the substrate, respectively. Alternatively, the orthographic projection of the second electrode of the switching transistor on the substrate at least partially overlaps with the orthographic projection of the second boundary on the substrate, and does not overlap with the orthographic projections of the third boundary, the fourth boundary, the sixth boundary and the gate electrode of the switching transistor on the substrate, respectively.

[0038] In an exemplary embodiment, the orthographic projection of the first target boundary on the substrate and the orthographic projection of the gate electrode of the switching transistor on the substrate do not overlap. The orthographic projection of the second target boundary on the substrate is within the range of the orthographic projection of the gate body portion on the substrate. When the first target boundary is the first boundary, the distance between the orthographic projection of the first boundary on the substrate and the orthographic projection of the fifth boundary on the substrate is in the range of 1 micrometer to 10 micrometers. The distance between the orthographic projection of the fifth boundary on the substrate and the orthographic projection of the boundary of the first electrode of the switching transistor away from the data signal line connected to the switching transistor on the substrate is in the range of 1 micrometer to 8 micrometers.

[0039] When the first target boundary is the second boundary, the distance between the orthographic projection of the second boundary on the substrate and the orthographic projection of the sixth boundary on the substrate is in the range of 1 micrometer to 10 micrometers, and the distance between the sixth boundary and the boundary of the second pole of the switching transistor near the data signal line is in the range of 1 micrometer to 8 micrometers.

[0040] In an exemplary embodiment, the orthographic projections of the first boundary and the second boundary on the substrate do not overlap with the orthographic projection of the gate electrode of the switching transistor on the substrate, and the orthographic projections of the first electrode and the second electrode of the switching transistor on the substrate do not overlap with the orthographic projection of the gate electrode of the switching transistor on the substrate, respectively.

[0041] The distance between the orthographic projection of the fifth boundary on the substrate and the boundary of the first pole of the switching transistor away from the data signal line connected to the switching transistor is in the range of 1 micrometer to 20 micrometers, and the distance between the orthographic projection of the sixth boundary on the substrate and the boundary of the second pole of the switching transistor near the data signal line connected to the switching transistor is in the range of 1 micrometer to 20 micrometers.

[0042] In an exemplary embodiment, it further includes: a driving structure layer disposed on a substrate, the driving structure layer having a plurality of sub-pixels and including: a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially stacked on the substrate, the driving structure layer further including: a first insulating layer disposed between the first conductive layer and the semiconductor layer;

[0043] The first conductive layer includes at least: the gate electrode of a switching transistor;

[0044] The semiconductor layer includes at least: an active pattern of a switching transistor;

[0045] The second conductive layer includes at least: a first electrode and a second electrode of a switching transistor;

[0046] The third conductive layer includes at least one common electrode for a sub-pixel;

[0047] The fourth conductive layer includes at least one pixel electrode for a sub-pixel;

[0048] The thickness of the first conductive layer is in the range of 2000 angstroms to 8000 angstroms, the thickness of the semiconductor layer is in the range of 200 angstroms to 2000 angstroms, and the thickness of the first insulating layer is in the range of 2000 angstroms to 6000 angstroms.

[0049] In a second aspect, this disclosure also provides a display device, including: a display panel, the display panel including: a cell substrate and the aforementioned display substrate;

[0050] The matching substrate and the display substrate are matched.

[0051] This disclosure reduces the overlap area between the data signal line connected to at least one switching transistor and the gate electrode of the switching transistor by at least partially overlapping the orthographic projection of the smaller gate connection portion on the substrate. This reduces the parasitic capacitance between the data signal line and the gate electrode of the switching transistor, thereby improving the display effect of the display substrate. Attached Figure Description

[0052] The accompanying drawings are provided to further illustrate the technical solution of this utility model and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solution of this utility model and do not constitute a limitation on the technical solution of this utility model.

[0053] Figure 1 This is a schematic diagram of the structure of a display substrate;

[0054] Figure 2 for Figure 1 Top view of the provided display substrate Figure 1 ;

[0055] Figure 3 for Figure 2 A cross-sectional schematic diagram of the provided display substrate;

[0056] Figure 4 for Figure 2 Schematic diagram of the middle part of the membrane layer;

[0057] Figure 5 for Figure 1 Top view of the provided display substrate Figure 2 ;

[0058] Figure 6 for Figure 1 Top view of the provided display substrate Figure 3 ;

[0059] Figure 7 for Figure 1 Top view of the provided display substrate Figure 4 ;

[0060] Figure 8 for Figure 1 Top view of the provided display substrate Figure 5 ;

[0061] Figure 9 for Figure 1 Top view of the provided display substrate Figure 6 ;

[0062] Figure 10 for Figure 1 Top view of the provided display substrate Figure 7 ;

[0063] Figure 11 for Figure 1 Top view of the provided display substrate Figure 8 ;

[0064] Figure 12 for Figure 1 Top view of the provided display substrate Figure 9 ;

[0065] Figure 13 for Figure 1 Top view of the provided display substrate Figure 10 ;

[0066] Figure 14 for Figure 1 Top view of the provided display substrate Figure 10 one;

[0067] Figure 15 for Figure 1 Top view of the provided display substrate Figure 10 two;

[0068] Figure 16 for Figure 1 Top view of the provided display substrate Figure 10 three;

[0069] Figure 17 for Figure 1 Top view of the provided display substrate Figure 10 Four;

[0070] Figure 18 for Figure 1 Top view of the provided display substrate Figure 10 five;

[0071] Figure 19 for Figure 1 Top view of the provided display substrate Figure 10 six;

[0072] Figure 20 for Figure 1 Top view of the provided display substrate Figure 10 seven;

[0073] Figure 21 for Figure 1 Top view of the provided display substrate Figure 10 eight;

[0074] Figure 22 for Figure 1 Top view of the provided display substrate Figure 10 Nine;

[0075] Figure 23 for Figure 1 Top view of the provided display substrate Figure 2 ten. Detailed Implementation

[0076] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0077] In the accompanying drawings, the size of the constituent elements, the thickness of the layers, or the area are sometimes exaggerated for clarity. Therefore, one aspect of this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0078] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0079] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0080] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0081] In this specification, a transistor is a device that includes at least three terminals: a control electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain terminal, drain region, or drain electrode) and the source electrode (source terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0082] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0083] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0084] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0085] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0086] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple structures in a same-layer arrangement may be made of the same material, while the final materials may be the same or different.

[0087] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0088] Figure 1 This is a schematic diagram of the structure of a display substrate. Figure 1 As shown, the display substrate may include multiple scan signal lines (Gate), multiple data signal lines (Data), and multiple sub-pixels defined by the intersection of the scan signal lines (Gate) and the data signal lines (Data). At least one sub-pixel includes: a switching transistor 10, a pixel electrode 21, and a common electrode (not shown in the figure).

[0089] In an exemplary embodiment, the display device on which the display substrate is located further includes a backlight, a liquid crystal layer, and a counter substrate. The counter substrate and the display substrate are aligned, with the liquid crystal layer disposed between the display substrate and the counter substrate, and the backlight is disposed on the side of the display substrate away from the counter substrate. The liquid crystal layer includes a plurality of liquid crystal molecules, and the counter substrate is provided with a plurality of light filters and a black matrix layer. During the display process of the display device, the backlight emits light to the display substrate, and a deflection electric field is formed between the pixel electrode and the common electrode in each sub-pixel to control the deflection of the liquid crystal molecules, thereby controlling the light incident on the counter substrate. The light emitted to the counter substrate is filtered by the light filters to emit multiple colors of light, thereby realizing the display.

[0090] In an exemplary embodiment, the display substrate may include a plurality of pixel units arranged in a matrix, at least one of the plurality of pixel units including a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and a third sub-pixel emitting a third color light.

[0091] In an exemplary embodiment, the first sub-pixel may be a red sub-pixel (R) that emits red light, the second sub-pixel may be a blue sub-pixel (B) that emits blue light, and the third sub-pixel may be a green sub-pixel (G) that emits green light.

[0092] In an exemplary embodiment, a pixel unit may include three sub-pixels, which may be arranged horizontally side by side, vertically side by side, or in a triangular arrangement, without limitation herein.

[0093] Figure 2 for Figure 1 Top view of the provided display substrate Figure 1 , Figure 3 for Figure 2 A cross-sectional schematic diagram of the provided display substrate. (See attached diagram.) Figure 2 and Figure 3 As shown, the switching transistor includes: an active pattern 12, a gate electrode 11, a first electrode 13, and a second electrode 14. The gate electrode 11 of the switching transistor is connected to the scan signal line, the first electrode 13 of the switching transistor is connected to the data signal line Data, and the second electrode 14 of the switching transistor is connected to the pixel electrode 21.

[0094] In an exemplary implementation, such as Figure 2 As shown, the gate electrode 11 of the switching transistor includes a gate body portion 11A and a gate connection portion 11B arranged along a first direction D1 and connected to each other. The gate connection portion 11B extends at least partially along the first direction D1. The length H1 of the gate body portion 11A along the second direction D2 is greater than the length H2 of the gate connection portion 11B along the second direction D2. The first direction D1 is the extension direction of the scan signal line, and the second direction D2 is the extension direction of the data signal line Data.

[0095] In an exemplary embodiment, the orthographic projection of the active pattern 12 of at least one switching transistor on the substrate at least partially overlaps with the orthographic projection of the gate body portion 11A on the substrate, and the orthographic projection of the data signal line Data connected to at least one switching transistor on the substrate at least partially overlaps with the orthographic projection of the gate connection portion 11B on the substrate.

[0096] In an exemplary embodiment, the gate connection portion of the switching transistor of the i-th column sub-pixel located in the same row is connected to the gate body portion of the switching transistor of the (i+1)-th column sub-pixel, and at least a portion of the scan signal line connected to at least one sub-pixel located in the same row is multiplexed as the gate electrode of the switching transistor.

[0097] This disclosure reduces the overlap area between the data signal line connected to the switching transistor and the gate electrode of the switching transistor by at least partially overlapping the orthographic projection of the data signal line connected to the switching transistor and the gate electrode of the switching transistor. This reduces the parasitic capacitance between the data signal line connected to the switching transistor and the gate electrode of the switching transistor, avoids the screen flickering problem of the display substrate caused by the presence of parasitic capacitance, and improves the display effect of the display substrate.

[0098] In an exemplary implementation, such as Figure 3As shown, the display substrate may further include: a driving structure layer disposed on the substrate 61, the driving structure layer having a plurality of sub-pixels, and including: a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially stacked on the substrate; the driving structure layer further includes: a first insulating layer 62, a second insulating layer 63, a third insulating layer 64, and a fourth insulating layer 65; the first insulating layer 62 is disposed between the first conductive layer and the semiconductor layer, the second insulating layer 63 and the third insulating layer 64 are disposed between the second conductive layer and the third conductive layer, and the fourth insulating layer 65 is disposed between the third conductive layer and the fourth conductive layer. The first insulating layer 62 may be referred to as a gate insulating layer, the second insulating layer 63 may be referred to as a first passivation layer, the third insulating layer 64 may be referred to as a planarization layer, and the fourth insulating layer 65 may be referred to as a second passivation layer.

[0099] In an exemplary embodiment, the first conductive layer includes at least: the gate electrode of the switching transistor of at least one sub-pixel.

[0100] In an exemplary embodiment, the thickness of the first conductive layer is in the range of 2,000 angstroms to 8,000 angstroms.

[0101] In an exemplary embodiment, the material used to fabricate the first conductive layer may be a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or a conductive alloy material, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as MoNb / Cu / MoNb, etc. This disclosure does not limit it in any way.

[0102] In an exemplary embodiment, the semiconductor layer includes at least an active pattern of a switching transistor.

[0103] In an exemplary embodiment, the thickness of the semiconductor layer is in the range of 200 angstroms to 2000 angstroms.

[0104] In an exemplary embodiment, the semiconductor layer can be an amorphous silicon layer, a polycrystalline silicon layer, or a metal oxide layer. The metal oxide layer can be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer can be a single layer, a double layer, or a multilayer.

[0105] In an exemplary embodiment, the second conductive layer includes at least: a first electrode 13 and a second electrode 14 of a switching transistor.

[0106] In an exemplary embodiment, the material used to fabricate the second conductive layer can be a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or a conductive alloy material, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It can be a single-layer structure or a multi-layer composite structure, such as MoNb / Cu / MoNb, etc. This disclosure does not limit it in any way.

[0107] In an exemplary embodiment, the third conductive layer includes at least one common electrode 22 for at least one sub-pixel.

[0108] In an exemplary embodiment, the common electrode of at least one sub-pixel is a planar structure, and the common electrodes of multiple sub-pixels are connected.

[0109] In an exemplary embodiment, the fourth conductive layer includes at least: a pixel electrode 21 of at least one sub-pixel.

[0110] In an exemplary embodiment, the pixel electrode in at least one sub-pixel can be a slit electrode.

[0111] In an exemplary embodiment, the third and fourth conductive layers can be transparent conductive layers. The transparent conductive layers can be a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a multi-layer composite structure, such as ITO / Ag / ITO.

[0112] In an exemplary embodiment, the thickness of the first insulating layer is in the range of 2,000 angstroms to 6,000 angstroms.

[0113] In an exemplary embodiment, the first insulating layer, the second insulating layer, and the fourth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, multiple layers, or composite layers. For example, when the first insulating layer comprises silicon oxide (SiOx) and silicon nitride (SiNx), the thickness of the silicon nitride layer is greater than the thickness of the silicon oxide layer.

[0114] In an exemplary embodiment Figure 4 for Figure 2 A schematic diagram of the middle part of the membrane layer. (See diagram below.) Figure 4As shown, on a plane parallel to the display substrate, for at least one switching transistor, the boundaries of the active pattern 12 include: a first boundary AL1, a second boundary AL2, a third boundary AL3, and a fourth boundary AL4. The boundaries of the gate body portion 11A include: a fifth boundary GL1 and a sixth boundary GL2. Specifically, the first boundary AL1 is the boundary of the active pattern 12 extending along the second direction D2 and close to the data signal line Data connected to the switching transistor; the second boundary AL2 is the boundary of the active pattern 12 extending along the second direction D2 and away from the data signal line Data connected to the switching transistor; the third boundary AL3 and the fourth boundary AL4 are two oppositely disposed boundaries of the active pattern 12 extending along the first direction D1; the fifth boundary GL1 is the boundary of the gate body portion 11A extending along the second direction D2 and close to the data signal line connected to the switching transistor; and the sixth boundary GL2 is the boundary of the gate body portion 11A extending along the second direction D2 and away from the data signal line connected to the switching transistor.

[0115] In an exemplary embodiment, the orthographic projections of the first boundary AL1 and the second boundary AL2 on the substrate are located within the range of the orthographic projection of the gate body portion 11A on the substrate; or, the orthographic projection of the first target boundary on the substrate does not overlap with the orthographic projection of the gate electrode of the switching transistor on the substrate, and the orthographic projection of the second target boundary on the substrate is located within the range of the orthographic projection of the gate body portion 11A on the substrate, the first target boundary is one of the first boundary AL1 and the second boundary AL2, and the second target boundary is the other of the first boundary AL1 and the second boundary AL2; or, the orthographic projections of the first boundary AL1 and the second boundary AL2 on the substrate do not overlap with the orthographic projection of the gate electrode of the switching transistor on the substrate, and the orthographic projections of at least one of the third boundary AL3 and the fourth boundary AL4 on the substrate at least partially overlap with the orthographic projections of the fifth boundary GL1 and the sixth boundary GL2 on the substrate.

[0116] In an exemplary embodiment, the first electrode of the switching transistor may extend along a first direction or along a second direction. When the first electrode of the switching transistor extends along the second direction, at least one sub-pixel further includes a first connection portion, through which the first electrode of the switching transistor is connected to a data signal line. When the first electrode of the switching transistor extends along the first direction, the first electrode of the switching transistor is directly connected to the data signal line.

[0117] In an exemplary embodiment, at least one sub-pixel further includes: an electrode connection block, wherein the second electrode of the switching transistor extends along a first direction, or may extend along a second direction. When the second electrode of the switching transistor extends along the second direction, at least one sub-pixel further includes: a second connection portion, wherein the second electrode of the switching transistor is connected to the electrode connection block through the second connection portion; when the second electrode of the switching transistor extends along the first direction, the second electrode of the switching transistor is directly connected to the electrode connection block.

[0118] In an exemplary embodiment Figure 2 The explanation will be based on the example where the orthogonal projections of the first boundary AL1 and the second boundary AL2 onto the substrate are located within the range of the orthogonal projection of the gate body portion 11A onto the substrate. Figure 2 In the provided display substrate, at least one sub-pixel further includes: a first connection portion 31, wherein the first electrode 13 of the switching transistor is connected to the data signal line Data through the first connection portion 31; the first electrode 13 of the switching transistor extends along the second direction D2, the first connection portion 31 extends along the first direction D1, and the length L2 of the first electrode 13 of the switching transistor along the second direction D2 is greater than the length L1 of the active pattern 12 along the second direction D2, and is greater than the length L4 of the first connection portion 31 along the second direction D2.

[0119] In an exemplary embodiment, the length L1 of the active pattern 12 of the switching transistor along the second direction is in the range of 3 micrometers to 10 micrometers.

[0120] In an exemplary embodiment, the length W1 of the first connecting portion 31 along the first direction D1 is in the range of 2 micrometers to 20 micrometers.

[0121] In an exemplary embodiment, Figure 2 In the provided display substrate, at least one sub-pixel further includes: a second connecting portion 32 and an electrode connecting block 30. The second connecting portion 32 and the electrode connecting block 30 are arranged along a first direction D1. The second electrode 14 of the switching transistor is connected to the electrode connecting block 30 through the second connecting portion 32. The electrode connecting block 30 is connected to the pixel electrode. The second electrode 14 of the switching transistor extends along a second direction D2. The second connecting portion 32 extends along the first direction D1. The length L3 of the second electrode 14 of the switching transistor along the second direction D2 is greater than the length L1 of the active pattern 12 along the second direction D2, and greater than the length of at least one structure of the second connecting portion 32 and the electrode connecting block 30 along the second direction D2. The length L6 of the electrode connecting block 30 along the second direction D2 is greater than the length L5 of the second connecting portion 32 along the second direction D2.

[0122] In an exemplary embodiment, the length L2 of the first electrode 13 of the switching transistor along the second direction D2 and the length L3 of the second electrode 14 of the switching transistor along the second direction D2 may be the same or different, and this disclosure does not limit them in any way.

[0123] In an exemplary implementation, such as Figure 2 As shown, the length L4 of the first connecting portion 31 along the second direction D2 and the length L5 of the second connecting portion 32 along the second direction D2 may be the same or different, and this disclosure does not impose any limitation on this.

[0124] In an exemplary embodiment, combined with Figure 2 and Figure 4 As shown, the orthographic projection of the first electrode 13 of the switching transistor on the substrate is located within the orthographic projection range of the gate body portion 11A on the substrate, and at least partially overlaps with the orthographic projections of the first boundary AL1, the third boundary AL3 and the fourth boundary AL4 on the substrate. The orthographic projection of the first connection portion 31 on the substrate overlaps with the orthographic projection of the fifth boundary GL1 on the substrate, and there is no overlap with the orthographic projection of the gate connection portion 11B on the substrate.

[0125] In an exemplary embodiment, combined with Figure 2 and Figure 4 As shown, the orthographic projection of the second electrode 14 of the switching transistor on the substrate is located within the orthographic projection range of the gate body portion 11A on the substrate, and at least partially overlaps with the orthographic projections of the second boundary AL2, the third boundary AL3 and the fourth boundary AL4 on the substrate. The orthographic projection of the second connection portion 32 on the substrate overlaps with the orthographic projection of the sixth boundary GL2 on the substrate, and there is no overlap with the orthographic projection of the gate connection portion 11B on the substrate.

[0126] Figure 5 for Figure 1 Top view of the provided display substrate Figure 2 Combining Figure 2 , Figure 4 and Figure 5 As shown, Figure 5 The provided display substrate and Figure 2 The difference in the provided display substrate lies in the arrangement of the first electrode of the switching transistor. Figure 5 In the provided display substrate, the first electrode 13 of the switching transistor extends along the first direction D1, and the length L2 of the first electrode 13 along the second direction D2 is less than the length L1 of the active pattern 12 along the second direction D2. The orthographic projection of the first electrode 13 of the switching transistor on the substrate at least partially overlaps with the orthographic projections of the first boundary AL1 and the fifth boundary GL1 on the substrate, and there is no overlap with the orthographic projections of the third boundary AL3 and the fourth boundary AL4 on the substrate.

[0127] In an exemplary embodiment, the arrangement of at least one electrode in the first and second poles of the switching transistor refers to the shape of the electrode, its connection method, and its projection relationship with the gate electrode and active pattern of the switching transistor.

[0128] In an exemplary embodiment, the length L2 of the first electrode 13 of the switching transistor along the second direction D2 is in the range of 2 micrometers to 5 micrometers.

[0129] Figure 6 for Figure 1 Top view of the provided display substrate Figure 3 . Figure 6 The provided display substrate and Figure 2 The difference in the provided display substrate lies in the way the second electrode of the switching transistor is set. Figure 6 In the provided display substrate, the second electrode 14 of the switching transistor extends along the first direction D1. The length L3 of the second electrode 14 of the switching transistor along the second direction D2 is less than the length L1 of the active pattern 12 along the second direction D2, and less than the length L6 of the electrode connection block 30 along the second direction D2. The orthographic projection of the second electrode 14 of the switching transistor on the substrate at least partially overlaps with the orthographic projections of the second boundary AL2 and the sixth boundary GL2 on the substrate, and there is no overlap with the orthographic projections of the third boundary AL3 and the fourth boundary AL4 on the substrate.

[0130] In an exemplary embodiment, the length L3 of the second electrode 14 of the switching transistor along the second direction D2 is in the range of 2 micrometers to 5 micrometers.

[0131] Figure 7 for Figure 1 Top view of the provided display substrate Figure 4 . Figure 7 The provided display substrate and Figure 2 The difference in the provided display substrate lies in the arrangement of the first and second electrodes of the switching transistor. Figure 7 The arrangement of the first electrode of the switching transistor in the provided display substrate is the same as... Figure 5 The first electrode of the switching transistor in the provided display substrate is set in the same way. Figure 7 The arrangement of the second electrode of the switching transistor in the provided display substrate is the same as... Figure 6 The second electrode of the switching transistor in the provided display substrate is configured in the same way, and will not be described again in this disclosure.

[0132] In an exemplary implementation, such as Figure 7 As shown, the length L3 of the second electrode 14 of the switching transistor along the second direction D2 can be the same as or different from the length L2 of the first electrode 13 of the switching transistor along the second direction D2. This disclosure does not impose any limitations on this.

[0133] Figure 8 for Figure 1 Top view of the provided display substrate Figure 5 . Figure 8 The following is an example where the orthographic projection of the first target boundary on the substrate does not overlap with the orthographic projection of the gate electrode 11 of the switching transistor on the substrate, the orthographic projection of the second target boundary on the substrate is within the range of the orthographic projection of the gate body portion 11A on the substrate, and the first target boundary is the second boundary AL2. Figure 8 The shape and connection relationship of the switching transistors in the provided display substrate are respectively related to Figure 2 The switching transistors in the provided display substrate have the same shape and connection relationship.

[0134] In an exemplary embodiment, combined with Figure 4 and Figure 8 As shown, Figure 8 In the provided display substrate, the orthographic projection of the first electrode 13 of the switching transistor on the substrate is located within the orthographic projection range of the gate body portion 11A on the substrate, and at least partially overlaps with the orthographic projections of the first boundary AL1, the third boundary AL3 and the fourth boundary AL4 on the substrate. The orthographic projection of the first connection portion 31 on the substrate overlaps with the orthographic projection of the fifth boundary GL1 on the substrate, and there is no overlap with the orthographic projection of the gate connection portion 11B on the substrate.

[0135] In an exemplary embodiment, combined with Figure 4 and Figure 8 As shown, Figure 8 In the provided display substrate, the orthographic projection of the second electrode 14 of the switching transistor on the substrate at least partially overlaps with the orthographic projections of the second boundary AL2, the third boundary AL3, the fourth boundary AL4 and the sixth boundary GL2 on the substrate, and there is no overlap between the orthographic projection of the first connection portion 31 on the substrate and the orthographic projection of the gate electrode 11 of the switching transistor on the substrate.

[0136] In an exemplary embodiment, combined with Figure 4 and Figure 8 As shown, the distance d1 between the orthographic projection of the second boundary AL2 on the substrate and the orthographic projection of the sixth boundary GL2 on the substrate is in the range of 1 micrometer to 10 micrometers, and the distance d2 between the sixth boundary GL2 and the boundary of the second pole 14 of the switching transistor near the data signal line Data is in the range of 1 micrometer to 8 micrometers.

[0137] Figure 9 for Figure 1 Top view of the provided display substrate Figure 6 Combining Figure 4 , Figure 8 and Figure 9 As shown, Figure 9The provided display substrate and Figure 8 The difference in the provided display substrate lies in the arrangement of the first electrode of the switching transistor. Among other things, Figure 9 The shape and connection relationship of the first electrode of the switching transistor in the provided display substrate are respectively related to Figure 5 The first electrode of the switching transistor in the provided display substrate has the same shape and connection relationship.

[0138] like Figure 9 As shown, the orthographic projection of the first electrode 13 of the switching transistor on the substrate at least partially overlaps with the orthographic projections of the first boundary AL1 and the fifth boundary GL1 on the substrate, and there is no overlap with the orthographic projections of the third boundary AL3 and the fourth boundary AL4 on the substrate.

[0139] Figure 10 for Figure 1 Top view of the provided display substrate Figure 7 Combining Figure 4 , Figure 8 and Figure 10 As shown, Figure 10 The provided display substrate and Figure 8 The difference in the provided display substrate lies in the arrangement of the second electrode of the switching transistor. Specifically, Figure 10 The shape and connection relationship of the second electrode of the switching transistor in the provided display substrate are respectively related to Figure 6 The first electrode of the switching transistor in the provided display substrate has the same shape and connection relationship.

[0140] like Figure 10 As shown, the orthographic projection of the second electrode 12 of the switching transistor on the substrate at least partially overlaps with the orthographic projections of the second boundary AL2 and the sixth boundary GL2 on the substrate, and there is no overlap with the orthographic projections of the third boundary AL3 and the fourth boundary AL4 on the substrate.

[0141] Figure 11 for Figure 1 Top view of the provided display substrate Figure 8 . Figure 11 The arrangement of the first electrode of the switching transistor in the provided display substrate is the same as... Figure 9 The first electrode of the switching transistor in the provided display substrate is set in the same way. Figure 11 The arrangement of the second electrode of the switching transistor in the provided display substrate is the same as... Figure 10 The second electrode of the switching transistor in the provided display substrate is configured in the same way, and will not be described again in this disclosure.

[0142] Figure 12 for Figure 1 Top view of the provided display substrate Figure 9 . Figure 12The following description is based on the example where the orthographic projection of the first target boundary on the substrate does not overlap with the orthographic projection of the gate electrode of the switching transistor on the substrate, the orthographic projection of the second target boundary on the substrate is within the range of the orthographic projection of the gate body portion 11A on the substrate, and the first target boundary is the first boundary AL1. Figure 12 The pattern of the third conductive layer in the provided display substrate is consistent with Figure 2 The third conductive layer pattern in the provided display substrate is the same, and the third conductive layer pattern includes the following structure.

[0143] In an exemplary embodiment, combined with Figure 4 and Figure 12 As shown, Figure 12 In the provided display substrate, within the range of the orthographic projection of the first electrode 13 of the switching transistor on the substrate and the orthographic projection of the first boundary AL1, the third boundary AL3, the fourth boundary AL4 and the fifth boundary GL1 on the substrate, there is no overlap between the orthographic projection of the first connection portion 31 on the substrate and the orthographic projection of the gate electrode of the switching transistor on the substrate.

[0144] In an exemplary embodiment, combined with Figure 4 and Figure 12 As shown, Figure 12 In the provided display substrate, the orthographic projection of the second electrode 14 of the switching transistor on the substrate is located within the orthographic projection range of the gate body portion 11A on the substrate, and at least partially overlaps with the orthographic projections of the second boundary AL2, the third boundary AL3 and the fourth boundary AL4 on the substrate. The orthographic projection of the second connection portion 32 on the substrate overlaps with the orthographic projection of the sixth boundary GL2 on the substrate, and there is no overlap with the orthographic projection of the gate connection portion 11B on the substrate.

[0145] In an exemplary embodiment, combined with Figure 4 and Figure 12 As shown, the distance d3 between the orthographic projection of the first boundary AL1 on the substrate and the orthographic projection of the fifth boundary GL1 on the substrate is in the range of 1 micrometer to 10 micrometers, and the distance d4 between the orthographic projection of the fifth boundary GL1 on the substrate and the orthographic projection of the boundary of the first pole 13 of the switching transistor away from the data signal line Data connected to the switching transistor on the substrate is in the range of 1 micrometer to 8 micrometers.

[0146] Figure 13 for Figure 1 Top view of the provided display substrate Figure 10 Combining Figure 4 , Figure 12 and Figure 13 As shown, Figure 13 The provided display substrate and Figure 12 The difference in the provided display substrate lies in the arrangement of the first electrode of the switching transistor. Among other things, Figure 13 The shape and connection relationship of the first electrode of the switching transistor in the provided display substrate are respectively related to Figure 5 The first electrode shape and connection relationship of the switching transistors in the provided display substrate are the same.

[0147] like Figure 13 As shown, the orthographic projection of the first electrode 13 of the switching transistor on the substrate at least partially overlaps with the orthographic projections of the first boundary AL1 and the fifth boundary GL1 on the substrate, and there is no overlap with the orthographic projections of the third boundary AL3 and the fourth boundary AL4 on the substrate.

[0148] Figure 14 for Figure 1 Top view of the provided display substrate Figure 10 1. Combination Figure 4 , Figure 12 and Figure 14 As shown, Figure 14 The provided display substrate and Figure 12 The difference in the provided display substrate lies in the arrangement of the second electrode of the switching transistor. Specifically, Figure 14 The shape and connection method of the second electrode of the switching transistor in the provided display substrate are respectively the same as those of the second electrode of the switching transistor in the provided display substrate. Figure 6 The first electrode of the switching transistor in the provided display substrate has the same shape and connection method.

[0149] like Figure 14 As shown, the orthographic projection of the second electrode 14 of the switching transistor on the substrate at least partially overlaps with the orthographic projections of the second boundary AL2 and the sixth boundary GL2 on the substrate, and there is no overlap with the orthographic projections of the third boundary AL3 and the fourth boundary AL4 on the substrate.

[0150] Figure 15 for Figure 1 Top view of the provided display substrate Figure 10 two. Figure 15 The arrangement of the first electrode of the switching transistor in the provided display substrate is the same as... Figure 13 The first electrode of the switching transistor in the provided display substrate is set in the same way. Figure 15 The arrangement of the second electrode of the switching transistor in the provided display substrate is the same as... Figure 14 The second electrode of the switching transistor in the provided display substrate is configured in the same way, and will not be described again in this disclosure.

[0151] Figure 16 for Figure 1 Top view of the provided display substrate Figure 10 three. Figure 16The explanation is based on the example where the orthographic projections of the first boundary AL1 and the second boundary AL2 on the substrate do not overlap with the orthographic projection of the gate body portion 11A on the substrate. Figure 16 The pattern of the third conductive layer in the provided display substrate is consistent with Figure 2 The third conductive layer pattern in the provided display substrate is the same, and the third conductive layer pattern includes the following structure.

[0152] like Figure 16 As shown, the orthographic projection of the first electrode 13 of the switching transistor on the substrate at least partially overlaps with the orthographic projections of the first boundary AL1, the third boundary AL3, the fourth boundary AL4 and the fifth boundary GL1 on the substrate, and there is no overlap between the orthographic projection of the first connection portion 31 on the substrate and the orthographic projection of the gate electrode of the switching transistor on the substrate.

[0153] like Figure 16 As shown, the orthographic projection of the second electrode 14 of the switching transistor on the substrate at least partially overlaps with the orthographic projections of the second boundary AL2, the third boundary AL3, the fourth boundary AL4 and the sixth boundary GL2 on the substrate, and there is no overlap between the orthographic projection of the second connection portion 32 on the substrate and the orthographic projection of the gate electrode of the switching transistor on the substrate.

[0154] Figure 17 for Figure 1 Top view of the provided display substrate Figure 10 IV. Combining Figure 4 , Figure 16 and Figure 17 As shown, Figure 17 The provided display substrate and Figure 16 The difference in the provided display substrate lies in the arrangement of the first electrode of the switching transistor. Among other things, Figure 17 The shape and connection relationship of the first electrode of the switching transistor in the provided display substrate are respectively related to Figure 5 The first electrode shape and connection relationship of the switching transistors in the provided display substrate are the same.

[0155] like Figure 17 As shown, the orthographic projection of the first electrode 13 of the switching transistor on the substrate at least partially overlaps with the orthographic projections of the first boundary AL1 and the fifth boundary GL1 on the substrate, and there is no overlap with the orthographic projections of the third boundary AL3 and the fourth boundary AL4 on the substrate.

[0156] Figure 18 for Figure 1 Top view of the provided display substrate Figure 10 5. Combining Figure 4 , Figure 16 and Figure 18 As shown, Figure 18 The provided display substrate and Figure 16 The difference in the provided display substrate lies in the arrangement of the second electrode of the switching transistor. Specifically, Figure 18 The shape and connection relationship of the second electrode of the switching transistor in the provided display substrate are respectively related to Figure 6 The second electrode of the switching transistor in the provided display substrate has the same shape and connection relationship.

[0157] like Figure 18 As shown, the orthographic projection of the second electrode 14 of the switching transistor on the substrate at least partially overlaps with the orthographic projections of the second boundary AL2 and the sixth boundary GL2 on the substrate, and there is no overlap with the orthographic projections of the third boundary AL3 and the fourth boundary AL4 on the substrate.

[0158] Figure 19 for Figure 1 Top view of the provided display substrate Figure 10 six. Figure 19 The arrangement of the first electrode of the switching transistor in the provided display substrate is the same as... Figure 17 The first electrode of the switching transistor in the provided display substrate is set in the same way. Figure 19 The arrangement of the second electrode of the switching transistor in the provided display substrate is the same as... Figure 18 The second electrode of the switching transistor in the provided display substrate is configured in the same way, and will not be described again in this disclosure.

[0159] Figure 20 for Figure 1 Top view of the provided display substrate Figure 10 seven. Figure 20 The explanation is based on the example where the orthographic projections of the first boundary AL1 and the second boundary AL2 on the substrate do not overlap with the orthographic projection of the gate body portion 11A on the substrate. Figure 20 The pattern of the third conductive layer in the provided display substrate is consistent with Figure 2 The third conductive layer pattern in the provided display substrate is the same, and the third conductive layer pattern includes the following structure.

[0160] like Figure 20 As shown, the orthographic projection of the first electrode 13 of the switching transistor on the substrate at least partially overlaps with the orthographic projections of the first boundary AL1, the third boundary AL3 and the fourth boundary AL4 on the substrate, and there is no overlap with the orthographic projection of the fifth boundary GL1 on the substrate. The orthographic projection of the first connection portion 31 on the substrate does not overlap with the orthographic projections of the fifth boundary GL1 and the gate electrode of the switching transistor on the substrate.

[0161] like Figure 20As shown, the orthographic projection of the second electrode 14 of the switching transistor on the substrate at least partially overlaps with the orthographic projections of the second boundary AL2, the third boundary AL3 and the fourth boundary AL4 on the substrate, and there is no overlap with the orthographic projection of the sixth boundary GL2 on the substrate. The orthographic projection of the second connection portion 32 on the substrate does not overlap with the orthographic projections of the sixth boundary GL2 and the gate electrode 11 of the switching transistor on the substrate.

[0162] In an exemplary implementation, such as Figure 20 As shown, the distance d5 between the orthographic projection of the fifth boundary GL1 on the substrate and the boundary of the first pole 13 of the switching transistor away from the data signal line Data connected to the switching transistor is in the range of 1 micrometer to 20 micrometers, and the distance d6 between the orthographic projection of the sixth boundary GL2 on the substrate and the boundary of the second pole 14 of the switching transistor close to the data signal line Data connected to the switching transistor is in the range of 1 micrometer to 20 micrometers.

[0163] In an exemplary embodiment, the distance d5 between the orthographic projection of the fifth boundary GL1 on the substrate and the boundary of the first pole 13 of the switching transistor away from the data signal line Data connected to the switching transistor, and the distance d6 between the orthographic projection of the sixth boundary GL2 on the substrate and the boundary of the second pole 14 of the switching transistor close to the data signal line Data connected to the switching transistor, may be the same or different, and this disclosure does not limit this.

[0164] Figure 21 for Figure 1 Top view of the provided display substrate Figure 10 8. Combination Figure 4 , Figure 20 and Figure 21 As shown, Figure 21 The provided display substrate and Figure 20 The difference in the provided display substrate lies in the arrangement of the first electrode of the switching transistor. Among other things, Figure 20 The shape and connection relationship of the first electrode of the switching transistor in the provided display substrate are respectively related to Figure 5 The first electrode of the switching transistor in the provided display substrate has the same shape and connection relationship.

[0165] like Figure 21 As shown, the orthographic projection of the first electrode 13 of the switching transistor on the substrate at least partially overlaps with the orthographic projection of the first boundary AL1 on the substrate, and there is no overlap with the third boundary AL3, the fourth boundary AL4, the fifth boundary GL1, the gate electrode of the switching transistor, and its orthographic projection on the substrate.

[0166] Figure 22 for Figure 1 Top view of the provided display substrate Figure 109. Combination Figure 4 , Figure 20 and Figure 22 As shown, Figure 22 The provided display substrate and Figure 20 The difference in the provided display substrate lies in the arrangement of the second electrode of the switching transistor. Specifically, Figure 22 The shape and connection relationship of the second electrode of the switching transistor in the provided display substrate are respectively related to Figure 6 The second electrode of the switching transistor in the provided display substrate has the same shape and connection relationship.

[0167] like Figure 22 As shown, the orthographic projection of the second electrode 14 of the switching transistor on the substrate at least partially overlaps with the orthographic projection of the second boundary AL2 on the substrate, and there is no overlap with the orthographic projections of the third boundary AL3, the fourth boundary AL4, the sixth boundary GL2 and the gate electrode of the switching transistor on the substrate.

[0168] Figure 23 for Figure 1 Top view of the provided display substrate Figure 2 ten. Figure 23 The arrangement of the first electrode of the switching transistor in the provided display substrate is the same as... Figure 21 The first electrode of the switching transistor in the provided display substrate is set in the same way. Figure 23 The arrangement of the second electrode of the switching transistor in the provided display substrate is the same as... Figure 22 The second electrode of the switching transistor in the provided display substrate is configured in the same way, and will not be described again in this disclosure.

[0169] In an exemplary embodiment, the active pattern of each transistor may include a first region, a second region, and a channel region located between the first and second regions. The first and second regions are conductive and therefore may also be referred to as conductive regions. Figure 2 , Figures 5 to 19 The provided display substrate, in which the first and second regions of the active pattern are conductiveized, can be achieved through electric field induction. Figures 20 to 23 The first and second regions in the active pattern of the provided display substrate can be achieved through ion doping.

[0170] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0171] (1) Forming a first conductive layer pattern. In an exemplary embodiment, forming a first conductive layer pattern may include: coating a first conductive film on a substrate, and patterning the first conductive film by a patterning process to form a first conductive layer pattern.

[0172] (2) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate on which the aforementioned pattern is formed, and patterning the semiconductor film by a patterning process to form a first insulating layer covering the substrate and a semiconductor layer pattern disposed on the first insulating layer.

[0173] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: depositing a second conductive film on a substrate on which the aforementioned pattern is formed, and patterning the second conductive film by a patterning process to form a second conductive layer pattern.

[0174] (4) Forming a third conductive layer pattern. In an exemplary embodiment, forming a third conductive layer pattern may include: sequentially depositing a second insulating film, coating a third insulating film, and depositing a third conductive film on a substrate on which the aforementioned pattern is formed, and patterning the third conductive film using a patterning process to form a third conductive layer pattern.

[0175] (5) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming a fourth conductive layer pattern may include: sequentially depositing a fourth insulating film and a fourth conductive film on a substrate on which the aforementioned pattern is formed, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer pattern.

[0176] This disclosure also provides a display device, including a display panel, which comprises a cell substrate and a display substrate. The display substrate and the cell substrate are disposed opposite to each other.

[0177] In an exemplary embodiment, the display device can be any product or component with display function, such as electronic paper, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0178] The accompanying drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0179] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0180] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, characterized in that, It includes: a substrate and data signal lines and scan signal lines disposed on the substrate, and a plurality of sub-pixels defined by the intersection of the data signal lines and the scan signal lines. At least one sub-pixel includes: a switching transistor, a pixel electrode and a common electrode. The switching transistor includes: an active pattern, a gate electrode, a first electrode and a second electrode. The gate electrode of the switching transistor is connected to the scan signal line, the first electrode of the switching transistor is connected to the data signal line, and the second electrode of the switching transistor is connected to the pixel electrode. The gate electrode of the switching transistor includes: a gate body portion and a gate connection portion arranged along a first direction and connected to each other, wherein the gate connection portion extends at least partially along the first direction, and the length of the gate body portion along a second direction is greater than the length of the gate connection portion along the second direction, wherein the first direction is the extension direction of the scan signal line, and the second direction is the extension direction of the data signal line; The orthographic projection of the active pattern of at least one switching transistor on the substrate at least partially overlaps with the orthographic projection of the gate body portion on the substrate, and the orthographic projection of the data signal line connected to at least one switching transistor on the substrate at least partially overlaps with the orthographic projection of the gate connection portion on the substrate.

2. The display substrate according to claim 1, wherein, On a plane parallel to the display substrate, for at least one switching transistor, the boundaries of the active pattern include: a first boundary, a second boundary, a third boundary, and a fourth boundary, and the boundaries of the gate body include: a fifth boundary and a sixth boundary. Wherein, the first boundary is the boundary of the active pattern extending along the second direction and close to the data signal line connected to the switching transistor; the second boundary is the boundary of the active pattern extending along the second direction and far away from the data signal line connected to the switching transistor; the third boundary and the fourth boundary are two oppositely arranged boundaries of the active pattern extending along the first direction; the fifth boundary is the boundary of the gate body extending along the second direction and close to the data signal line connected to the switching transistor; and the sixth boundary is the boundary of the gate body extending along the second direction and far away from the data signal line connected to the switching transistor. The orthographic projections of the first boundary and the second boundary onto the substrate are located within the range of the orthographic projection of the gate body onto the substrate; Alternatively, the orthographic projection of the first target boundary on the substrate and the orthographic projection of the gate electrode of the switching transistor on the substrate do not overlap, and the orthographic projection of the second target boundary on the substrate is within the range of the orthographic projection of the gate body portion on the substrate. The first target boundary is one of the first boundary and the second boundary, and the second target boundary is the other of the first boundary and the second boundary. Alternatively, the orthographic projections of the first boundary and the second boundary on the substrate do not overlap with the orthographic projections of the gate electrode of the switching transistor on the substrate, and the orthographic projections of at least one of the third boundary and the fourth boundary on the substrate at least partially overlap with the orthographic projections of the fifth boundary and the sixth boundary on the substrate. The active pattern of the switching transistor has a length along the second direction ranging from 3 micrometers to 10 micrometers.

3. The display substrate according to claim 2, characterized in that, At least one sub-pixel further includes: a first connecting portion, wherein the first electrode of the switching transistor is connected to the data signal line through the first connecting portion; The first electrode of the switching transistor extends along the second direction, the first connection portion extends along the first direction, and the length of the first electrode of the switching transistor along the second direction is greater than the length of the active pattern along the second direction and greater than the length of the first connection portion along the second direction. The length of the first connecting portion along the first direction is in the range of 2 micrometers to 20 micrometers.

4. The display substrate according to claim 3, characterized in that, When the orthographic projections of the first boundary and the second boundary on the substrate are respectively within the range of the orthographic projection of the gate body portion on the substrate, the orthographic projection of the first pole of the switching transistor on the substrate is within the range of the orthographic projection of the gate body portion on the substrate, and at least partially overlaps with the orthographic projections of the first boundary, the third boundary and the fourth boundary on the substrate. The orthographic projection of the first connection portion on the substrate overlaps with the orthographic projection of the fifth boundary on the substrate, and there is no overlap with the orthographic projection of the gate connection portion on the substrate.

5. The display substrate according to claim 3, characterized in that, The orthographic projection of the first target boundary on the substrate and the orthographic projection of the gate electrode of the switching transistor on the substrate do not overlap. The orthographic projection of the second target boundary on the substrate is within the range of the orthographic projection of the gate body portion on the substrate. When the first target boundary is the first boundary, the orthographic projection of the first electrode of the switching transistor on the substrate is within the range of the orthographic projection of the first boundary, the third boundary, the fourth boundary and the fifth boundary on the substrate. The orthographic projection of the first connection portion on the substrate and the orthographic projection of the gate electrode of the switching transistor on the substrate do not overlap. The orthographic projection of the first target boundary on the substrate does not overlap with the orthographic projection of the gate electrode of the switching transistor on the substrate. The orthographic projection of the second target boundary on the substrate is within the range of the orthographic projection of the gate body portion of the switching transistor on the substrate. When the first target boundary is the second boundary, the orthographic projection of the first electrode of the switching transistor on the substrate is within the range of the orthographic projection of the gate body portion on the substrate, and at least partially overlaps with the orthographic projections of the first boundary, the third boundary, and the fourth boundary on the substrate. The orthographic projection of the first connection portion on the substrate overlaps with the orthographic projection of the fifth boundary on the substrate, and does not overlap with the orthographic projection of the gate connection portion on the substrate.

6. The display substrate according to claim 3, characterized in that, When the orthographic projections of the first boundary and the second boundary on the substrate do not overlap with the orthographic projections of the gate body portion on the substrate, the orthographic projection of the first electrode of the switching transistor on the substrate at least partially overlaps with the orthographic projections of the first boundary, the third boundary, the fourth boundary and the fifth boundary on the substrate, and the orthographic projection of the first connection portion on the substrate does not overlap with the orthographic projection of the gate electrode of the switching transistor on the substrate. Alternatively, the orthographic projection of the first electrode of the switching transistor on the substrate at least partially overlaps with the orthographic projections of the first boundary, the third boundary, and the fourth boundary on the substrate, and the orthographic projection of the first connection portion on the substrate does not overlap with the orthographic projections of the fifth boundary and the gate electrode of the switching transistor on the substrate.

7. The display substrate according to claim 2, characterized in that, The first electrode of the switching transistor extends along a first direction, and the length of the first electrode of the switching transistor along a second direction is less than the length of the active pattern along the second direction. The length of the first electrode of the switching transistor along the second direction is in the range of 2 micrometers to 5 micrometers.

8. The display substrate according to claim 7, characterized in that, When the orthographic projections of the first boundary and the second boundary on the substrate are respectively within the range of the orthographic projection of the gate body portion on the substrate, or when the orthographic projection of the first target boundary on the substrate and the orthographic projection of the gate electrode of the switching transistor on the substrate do not overlap, and the orthographic projection of the second target boundary on the substrate is within the range of the orthographic projection of the gate body portion of the switching transistor on the substrate, the orthographic projection of the first electrode of the switching transistor on the substrate at least partially overlaps with the orthographic projections of the first boundary and the fifth boundary on the substrate, and does not overlap with the orthographic projections of the third boundary and the fourth boundary on the substrate.

9. The display substrate according to claim 7, characterized in that, When the orthographic projections of the first boundary and the second boundary on the substrate do not overlap with the orthographic projection of the gate electrode of the switching transistor on the substrate, the orthographic projection of the first electrode of the switching transistor on the substrate at least partially overlaps with the orthographic projections of the first boundary and the fifth boundary on the substrate, and does not overlap with the orthographic projections of the third boundary, the fourth boundary and the gate connection portion on the substrate, or the orthographic projection of the first electrode of the switching transistor on the substrate at least partially overlaps with the orthographic projection of the first boundary on the substrate, and does not overlap with the orthographic projections of the third boundary, the fourth boundary, the fifth boundary and the gate electrode of the switching transistor on the substrate.

10. The display substrate according to claim 2, characterized in that, At least one sub-pixel further includes: a second connecting portion and an electrode connecting block, the second connecting portion and the electrode connecting block being arranged along a first direction, the second electrode of the switching transistor being connected to the electrode connecting block through the second connecting portion, and the electrode connecting block being connected to the pixel electrode; The second electrode of the switching transistor extends along a second direction, the second connection portion extends along a first direction, the length of the second electrode of the switching transistor along the second direction is greater than the length of the active pattern along the second direction, and greater than the length of at least one structure of the second connection portion and the electrode connection block along the second direction, the length of the electrode connection block along the second direction is greater than the length of the second connection portion along the second direction; The length of the second connecting portion along the first direction is in the range of 2 micrometers to 20 micrometers.

11. The display substrate according to claim 10, characterized in that, When the orthographic projections of the first boundary and the second boundary on the substrate are respectively within the range of the orthographic projection of the gate body portion on the substrate, the orthographic projection of the second pole of the switching transistor on the substrate is within the range of the orthographic projection of the gate body portion on the substrate, and at least partially overlaps with the orthographic projections of the second boundary, the third boundary and the fourth boundary on the substrate. The orthographic projection of the second connection portion on the substrate overlaps with the orthographic projection of the sixth boundary on the substrate, and there is no overlap with the orthographic projection of the gate connection portion on the substrate.

12. The display substrate according to claim 10, characterized in that, The orthographic projection of the first target boundary on the substrate does not overlap with the orthographic projection of the gate electrode of the switching transistor on the substrate. The orthographic projection of the second target boundary on the substrate is within the range of the orthographic projection of the gate body portion of the switching transistor on the substrate. When the first target boundary is the first boundary, the orthographic projection of the second electrode of the switching transistor on the substrate is within the range of the orthographic projection of the gate body portion on the substrate, and at least partially overlaps with the orthographic projections of the second boundary, the third boundary, and the fourth boundary on the substrate. The orthographic projection of the second connection portion on the substrate overlaps with the orthographic projection of the sixth boundary on the substrate, and does not overlap with the orthographic projection of the gate connection portion on the substrate. The orthographic projection of the first target boundary on the substrate does not overlap with the orthographic projection of the gate electrode of the switching transistor on the substrate. The orthographic projection of the second target boundary on the substrate is within the range of the orthographic projection of the gate body portion of the switching transistor on the substrate. When the first target boundary is the second boundary, the orthographic projection of the second electrode of the switching transistor on the substrate at least partially overlaps with the orthographic projections of the second boundary, the third boundary, the fourth boundary, and the sixth boundary on the substrate. The orthographic projection of the second connection portion on the substrate does not overlap with the orthographic projection of the gate electrode of the switching transistor on the substrate.

13. The display substrate according to claim 10, characterized in that, When the orthographic projections of the first boundary and the second boundary on the substrate do not overlap with the orthographic projection of the gate electrode of the switching transistor on the substrate, the orthographic projection of the second electrode of the switching transistor on the substrate at least partially overlaps with the orthographic projections of the second boundary, the third boundary, the fourth boundary, and the sixth boundary on the substrate, and the orthographic projection of the second connection portion on the substrate does not overlap with the orthographic projection of the gate electrode of the switching transistor on the substrate; or, the orthographic projection of the second electrode of the switching transistor on the substrate at least partially overlaps with the orthographic projections of the second boundary, the third boundary, and the fourth boundary on the substrate, and does not overlap with the orthographic projection of the sixth boundary on the substrate, and the orthographic projection of the second connection portion on the substrate does not overlap with the orthographic projections of the sixth boundary and the gate electrode of the switching transistor on the substrate, respectively.

14. The display substrate according to claim 2, characterized in that, At least one sub-pixel further includes: an electrode connection block, a second electrode of a switching transistor and the electrode connection block arranged along a first direction, the second electrode of the switching transistor being connected to the electrode connection block, and the electrode connection block being electrically connected to a pixel electrode. The second electrode of the switching transistor extends along the first direction, and the length of the second electrode of the switching transistor along the second direction is less than the length of the active pattern of the switching transistor along the second direction, and less than the length of the electrode connection block along the second direction. The length of the second electrode of the switching transistor along the second direction is in the range of 2 micrometers to 5 micrometers.

15. The display substrate according to claim 14, characterized in that, When the orthographic projections of the first boundary and the second boundary on the substrate are respectively within the range of the orthographic projection of the gate body portion on the substrate, or when the orthographic projection of the first target boundary on the substrate does not overlap with the orthographic projection of the gate electrode of the switching transistor on the substrate, and the orthographic projection of the second target boundary on the substrate is within the range of the orthographic projection of the gate body portion of the switching transistor on the substrate, the orthographic projection of the second electrode of the switching transistor on the substrate at least partially overlaps with the orthographic projections of the second boundary and the sixth boundary on the substrate, and does not overlap with the orthographic projections of the third boundary and the fourth boundary on the substrate.

16. The display substrate according to claim 14, characterized in that, When the orthographic projections of the first boundary and the second boundary on the substrate do not overlap with the orthographic projection of the gate electrode of the switching transistor on the substrate, the orthographic projection of the second electrode of the switching transistor on the substrate at least partially overlaps with the orthographic projections of the second boundary and the sixth boundary on the substrate, and does not overlap with the orthographic projections of the third boundary, the fourth boundary and the gate connection portion on the substrate, or the orthographic projection of the second electrode of the switching transistor on the substrate at least partially overlaps with the orthographic projection of the second boundary on the substrate, and does not overlap with the orthographic projections of the third boundary, the fourth boundary, the sixth boundary and the gate electrode of the switching transistor on the substrate.

17. The display substrate according to claim 2, characterized in that, There is no overlap between the orthographic projection of the first target boundary on the substrate and the orthographic projection of the gate electrode of the switching transistor on the substrate. The orthographic projection of the second target boundary on the substrate is within the range of the orthographic projection of the gate body on the substrate. When the first target boundary is the first boundary, the distance between the orthographic projection of the first boundary on the substrate and the orthographic projection of the fifth boundary on the substrate is in the range of 1 micrometer to 10 micrometers. The distance between the orthographic projection of the fifth boundary on the substrate and the orthographic projection of the boundary of the first electrode of the switching transistor away from the data signal line connected to the switching transistor on the substrate is in the range of 1 micrometer to 8 micrometers. When the first target boundary is the second boundary, the distance between the orthographic projection of the second boundary on the substrate and the orthographic projection of the sixth boundary on the substrate is in the range of 1 micrometer to 10 micrometers, and the distance between the sixth boundary and the boundary of the second pole of the switching transistor near the data signal line is in the range of 1 micrometer to 8 micrometers.

18. The display substrate according to claim 2, characterized in that, The orthographic projections of the first boundary and the second boundary on the substrate do not overlap with the orthographic projection of the gate electrode of the switching transistor on the substrate, and the orthographic projections of the first electrode and the second electrode of the switching transistor on the substrate do not overlap with the orthographic projection of the gate electrode of the switching transistor on the substrate, respectively. The distance between the orthographic projection of the fifth boundary on the substrate and the boundary of the first pole of the switching transistor away from the data signal line connected to the switching transistor is in the range of 1 micrometer to 20 micrometers, and the distance between the orthographic projection of the sixth boundary on the substrate and the boundary of the second pole of the switching transistor near the data signal line connected to the switching transistor is in the range of 1 micrometer to 20 micrometers.

19. The display substrate according to claim 1, characterized in that, Also includes: A driving structure layer disposed on a substrate, the driving structure layer having multiple sub-pixels, and including: a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially stacked on the substrate, the driving structure layer further including: a first insulating layer disposed between the first conductive layer and the semiconductor layer; The first conductive layer includes at least: the gate electrode of a switching transistor; The semiconductor layer includes at least: an active pattern of a switching transistor; The second conductive layer includes at least: a first electrode and a second electrode of a switching transistor; The third conductive layer includes at least one common electrode for a sub-pixel; The fourth conductive layer includes at least one pixel electrode for a sub-pixel; The thickness of the first conductive layer is in the range of 2000 angstroms to 8000 angstroms, the thickness of the semiconductor layer is in the range of 200 angstroms to 2000 angstroms, and the thickness of the first insulating layer is in the range of 2000 angstroms to 6000 angstroms.

20. A display device, characterized in that, include: The display panel includes: a cell substrate and a display substrate as described in any one of claims 1 to 19; The matching substrate and the display substrate are matched.

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