Display panel and display device

Abstract

The utility model provides a display panel, which comprises a substrate, a semiconductor layer, a first conductive layer, a hydrogen-resistant insulating layer and a first insulating layer, and is characterized in that the semiconductor layer is located on the substrate and comprises a plurality of channel regions; the first conductive layer is located on one side, deviating from the substrate, of the semiconductor layer, and the first conductive layer comprises a plurality of gate parts overlapped with the channel region; the hydrogen-resistant insulating layer is positioned on one side, deviating from the substrate, of the first conductive layer; the first insulating layer is located on the side, away from the substrate, of the hydrogen-resistant insulating layer; according to the invention, the hydrogen-resistant insulating layer is arranged between the first insulating layer and the first conductive layer, and the hydrogen-resistant insulating layer cannot capture hydrogen in a Hydro process, so that hydrogen ions H < + > are prevented from diffusing to a channel region of the semiconductor layer through a gate part of the transistor in a double-85 experiment test process and being stabilized to form a positive electric field; therefore, the negative offset of the threshold voltage of the transistor is avoided.

Description

Technical Field

[0001] This disclosure relates to the technical field, and more particularly to a display panel and display device. Background Technology

[0002] Currently, Low Temperature Poly-silicon (LTPS) Active-matrix Organic Light Emitting Diode (AMOLED) display panels have become the mainstream display panel material. However, during the dual 85 experimental RA reliability test, LTPS-TFTs will experience a negative VTH shift under high temperature illumination bias conditions, resulting in pitting (dark spots), AOD bright spots, or S-axis bright lines on the display panel. Utility Model Content

[0003] In view of this, the purpose of this disclosure is to provide a display panel and a display device that can solve at least one of the above-mentioned technical problems.

[0004] For the purposes described above, this disclosure discloses a display panel comprising:

[0005] Substrate,

[0006] A semiconductor layer is located on the substrate, and the semiconductor layer includes a plurality of channel regions;

[0007] A first conductive layer is located on the side of the semiconductor layer away from the substrate, and the first conductive layer includes a plurality of gate portions stacked with corresponding channel regions.

[0008] A hydrogen-barrier insulating layer is located on the side of the first conductive layer that is away from the substrate;

[0009] The first insulating layer is located on the side of the hydrogen-blocking insulating layer that is away from the substrate.

[0010] In one embodiment, the hydrogen-blocking insulating layer comprises a silicon oxide layer;

[0011] Preferably, the first insulating layer comprises a silicon nitride layer.

[0012] In one embodiment, the thickness ratio of the hydrogen-blocking insulating layer to the first insulating layer is between 0.3 and 0.35 in the direction perpendicular to the plane of the substrate.

[0013] Preferably, in the direction perpendicular to the surface of the substrate, the thickness of the first insulating layer is between 300-350 angstroms, and the thickness of the hydrogen-blocking insulating layer is between 900-1100 angstroms.

[0014] In one embodiment, the gate portion includes a columnar crystal structure, the columnar crystal structure including grain boundary defects, and a portion of the hydrogen-blocking insulating layer is located within the grain boundary defects;

[0015] Preferably, the material of the first conductive layer includes molybdenum.

[0016] In one embodiment, the display panel includes a driving transistor, and the plurality of gate portions include a first gate portion of the driving transistor.

[0017] The plurality of channel regions include a first channel region of the driving transistor, wherein the orthographic projection of the first gate portion on the substrate coincides with the orthographic projection of the first channel region of the driving transistor on the substrate;

[0018] Preferably, the semiconductor layer further includes a first source region and a first drain region located on both sides of the first channel region, the first electrode of the driving transistor is electrically connected to the first source region, and the second electrode of the driving transistor is electrically connected to the first drain region.

[0019] In one embodiment, the display panel includes a pixel capacitor, the pixel capacitor includes a first electrode plate and a second electrode plate, the first electrode plate is located on the side of the second electrode plate close to the substrate, the first electrode plate is located on the first conductive layer, and the first electrode plate and the first gate portion of the driving transistor have the same structure.

[0020] The display panel further includes a second conductive layer located on the side of the hydrogen-blocking insulating layer away from the substrate; a second electrode plate is located on the second conductive layer, and the first electrode of the driving transistor is electrically connected to the second electrode plate of the pixel capacitor.

[0021] In one embodiment, the display panel includes a first reset transistor, a plurality of gate portions including second gate portions of the first reset transistor, a plurality of channel regions including second channel regions of the first reset transistor, and the orthographic projection of the second gate portion on the substrate coincides with the orthographic projection of the second channel region on the substrate;

[0022] Preferably, the semiconductor layer further includes a second source region and a second drain region located on both sides of the corresponding second channel region, the first electrode of the first reset transistor is electrically connected to the second source region, the second electrode of the first reset transistor is electrically connected to the second drain region, and the second electrode of the first reset transistor is electrically connected to the first gate portion of the driving transistor.

[0023] In one embodiment, the display panel further includes a third conductive layer located on the side of the second conductive layer opposite to the substrate;

[0024] Preferably, the display panel further includes a power signal line and a data line, at least one of which is located in the third conductive layer, and the first electrode of the driving transistor is electrically connected to the power signal line.

[0025] Preferably, the driving transistor is a p-type transistor;

[0026] Preferably, the display panel further includes a reset signal line located in the second conductive layer, the first terminal of the first reset transistor being electrically connected to the reset signal line, and the signal on the first reset signal line being transmitted to the first gate portion of the driving transistor via the first reset transistor.

[0027] In one embodiment, the display panel includes a display area and a non-display area, the non-display area including a bonding area located on one side of the display area;

[0028] The display panel further includes a light-emitting element located in the display area and on the side of the first insulating layer away from the substrate.

[0029] Based on the same concept, this disclosure also discloses a display device including the display panel described above.

[0030] Compared with the prior art, the display panel provided in this disclosure has a hydrogen-blocking insulating layer between the first insulating layer and the first conductive layer M1 (gate portion). This hydrogen-blocking insulating layer cannot capture hydrogen during the hydrogenation process, thus preventing hydrogen ions (H+) from being trapped. + During the dual 85 experiment, a positive electric field is formed by diffusion from the gate portion of the transistor to the channel region of the semiconductor layer and stabilization, thereby avoiding the threshold voltage V of the transistor TFT. TH With the negative offset, the bias performance of the transistor TFT is improved, and the image retention performance of the display panel is significantly improved, avoiding display panel pitting, AOD bright spots or S-direction bright lines. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in this disclosure or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a cross-sectional schematic diagram of a display panel in the prior art;

[0033] Figure 2 This is a schematic cross-sectional view of a partial wiring diagram display panel provided in an embodiment of this application;

[0034] Figure 3 for Figure 2 A partial wiring diagram of the first conductive layer in the provided display panel;

[0035] Figure 4 for Figure 2 A partial wiring diagram of the provided display panel;

[0036] Figure 5 This is a schematic diagram of a columnar crystal structure;

[0037] Figure 6 S-TFT PBTS with CI Base and CI Inversion (85℃, V) GS =20V) Test result diagram. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0039] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0040] Before describing the technical solutions provided in the embodiments of this application, in order to facilitate the understanding of the embodiments of this application, this application first specifically explains the problems existing in the related technologies.

[0041] The inventors discovered that the capacitor insulating layer CI in the display panel includes a silicon nitride (SiNx) layer. This silicon nitride (SiNx) layer is located between the first conductive layer M1 (including the gate portion of the transistor) and the second conductive layer M2. An active layer is disposed on the side of the first conductive layer M1 opposite to the second conductive layer M2. The gate portion of the transistor has a columnar crystal structure and contains a large number of grain boundary defects. During the fabrication of the silicon nitride (SiNx) layer, the silicon nitride material of the silicon nitride (SiNx) layer will penetrate into the grain boundary defects of the gate portion of the transistor. At the same time, due to the hydrogenation process and its high fabrication temperature, the NH in the silicon nitride layer breaks down, forming H. + This leads to the accumulation of a large amount of H at the grain boundary defects of the gate portion. + Subsequently, during the dual 85 experiment RA reliability test, which refers to operation in an environment with a temperature of 85℃ and a humidity of 85%, the first reset transistor T4 in the pixel circuit (which controls the reset signal line to initialize the pixel capacitor) is in a PBTS (positive voltage bias and temperaturestress) state. + A positive electric field (GATE off-state electric field) diffuses into the channel region of the first reset transistor T4 under the positive electric field of the gate PBTS, causing the threshold voltage V of the driving transistor T1 to rise. TH Significant negative bias causes a severe negative offset in the driving transistor T1, preventing the reset signal line from effectively writing to the pixel capacitor. This results in an increased pixel capacitor charging rate, leading to display pinholes (dark spots). Similarly, it can also cause other transistors to experience threshold voltage V. TH Negative bias can cause problems such as AOD bright spots and S-axis bright lines, for example, the transistor threshold voltage V in the Demux circuit. TH Negative bias.

[0042] For the reasons mentioned above, this application provides a display panel that significantly improves image retention performance and avoids display panel speckles, AOD bright spots, or S-shaped bright lines.

[0043] Next, combine Figures 2-6This application describes a display panel including a substrate 10, a semiconductor layer 20, a first conductive layer M1, a hydrogen-blocking insulating layer 32, and a first insulating layer 31. The semiconductor layer 20 is located on the substrate 10 and includes multiple channel regions. The first conductive layer M1 is located on the side of the semiconductor layer 20 away from the substrate 10 and includes multiple gate portions (GATEs) stacked with the channel regions. The hydrogen-blocking insulating layer 32 is located on the side of the first conductive layer M1 away from the substrate 10. The first insulating layer 31 is located on the side of the hydrogen-blocking insulating layer 32 away from the substrate 10. In this application, a hydrogen-blocking insulating layer 32 is disposed between the first insulating layer 31 and the first conductive layer M1 (gate portion). The hydrogen-blocking insulating layer 32 cannot capture hydrogen in the hydrogenation process, that is, a large amount of H accumulates at the grain boundary defects of the gate portion (GATE). + This avoids subsequent hydrogen ion H + During the dual 85 experiment, a positive electric field is formed by the diffusion of the transistor's gate portion into the channel region of semiconductor layer 20 and stabilization, thereby preventing the transistor's threshold voltage V from being exceeded. TH The negative offset.

[0044] For example, the display panel includes a display area AA and a non-display area, the non-display area including a binding area B located on one side of the display area AA.

[0045] For example, substrate 10 can be a rigid substrate 10, which may include, but is not limited to, any one of a glass substrate, a conductive silicon (Si) substrate 10, a silicon oxide (SiOx) substrate 10, an aluminum oxide (Al2O3) substrate 10 (i.e., a sapphire substrate 10), a silicon carbide (SiC) substrate 10, and a gallium nitride (GaN) substrate 10. Substrate 10 can also be a flexible substrate 10, for example, a flexible substrate 10 made of polyimide (PI).

[0046] refer to Figures 2-4 The display panel includes a semiconductor layer 20 and multiple conductive layers on a substrate 10, and the multiple conductive layers are insulated from each other. Specifically, the multiple conductive layers are all located on the side of the semiconductor layer 20 away from the substrate 10. The multiple conductive layers include a first conductive layer M1, a second conductive layer M2 and a third conductive layer M3. The first conductive layer M1 is located on the side of the semiconductor layer 20 away from the substrate 10, the second conductive layer M2 is located on the side of the first conductive layer M1 away from the substrate 10, and the third conductive layer M3 is located on the side of the second conductive layer M2 away from the substrate 10. Further, the first conductive layer M1 is located on the side of the hydrogen barrier insulating layer 32 close to the substrate, and the second conductive layer M2 is located on the side of the hydrogen barrier insulating layer 32 away from the substrate 10.

[0047] For example, the materials of the first conductive layer M1 and the second conductive layer M2 may include molybdenum (Mo); the materials of the third conductive layer M3 may include titanium (Ti) and aluminum (Al), specifically, the third conductive layer M3 is, for example, a Ti / Al / Ti composite layer.

[0048] For example, the material of semiconductor layer 20 can be a semiconductor material such as polysilicon; preferably, semiconductor layer 20 is a polysilicon layer (pSi). Hereinafter, the semiconductor layer 20 will be described as pSi. In some embodiments, semiconductor layer 20 may include portions of the active layer of each transistor in the pixel circuit, such as semiconductor layer 20 including a first active layer of driving transistor T1 and a second active layer of first reset transistor T4.

[0049] The display panel also includes a pixel driving circuit, which includes multiple transistors, including a driving transistor T1 and a first reset transistor T4 (also referred to as a switching transistor). For example, the driving transistor is a p-type transistor.

[0050] refer to Figure 2 For example, the plurality of gate portions GATE in the first conductive layer M1 includes a first gate portion GATE1 of the driving transistor T1 and a second gate portion GATE2 of the first reset transistor T4. The semiconductor layer 20 includes a first channel region 21 of the driving transistor T1 and a second channel region 24 of the first reset transistor T4. The orthographic projection of the first gate portion GATE1 on the substrate 10 coincides with the orthographic projection of the first channel region 21 of the driving transistor T1 on the substrate 10, and the orthographic projection of the second gate portion GATE2 on the substrate 10 coincides with the orthographic projection of the second channel region 24 on the substrate 10.

[0051] Furthermore, the semiconductor layer 20 also includes a first source region 22 and a first drain region 23 located on both sides of the corresponding first channel region 21. The first source region 22, the first drain region 23, and the first channel region 21 together form the first active layer of the driving transistor T1. The semiconductor layer 20 also includes a second source region 25 and a second drain region 26 located on both sides of the corresponding second channel region 24. The second source region 25, the second drain region 26, and the second channel region 24 together form the second active layer of the first reset transistor T4. The first terminal of the driving transistor T1 is electrically connected to the first source region 22, and the second terminal of the driving transistor T1 is electrically connected to the first drain region 23. The first terminal of the first reset transistor T4 is electrically connected to the second source region 25, and the second terminal of the first reset transistor T4 is electrically connected to the second drain region 26. The first terminal of the first reset transistor T4 is electrically connected to the first gate portion GATE1 of the driving transistor T1.

[0052] refer to Figures 3-4For example, the plurality of transistors in this application also include a data writing transistor T2, a threshold compensation transistor T3, a power writing transistor T5, a light-emitting control transistor T6, and a second reset transistor T7. Similarly, the semiconductor layer 20 also includes an active layer of the data writing transistor T2, the threshold compensation transistor T3, the power writing transistor T5, the light-emitting control transistor T6, and the second reset transistor T7.

[0053] refer to Figure 5 In one embodiment, the gate portion (GATE) includes a columnar crystal structure 60 extending in a direction perpendicular to the surface of the substrate (i.e., the columnar crystal structure extends along the thickness direction of the first conductive layer (GATE)). The columnar crystal structure 60 includes grain boundary defects, and a portion of the hydrogen-blocking insulating layer 32 is located within the grain boundary defects. It should be noted that the grain boundary defects here specifically refer to the gap between two adjacent columnar crystals in the columnar crystal structure. When forming the hydrogen-blocking insulating layer 32, some of the material in the hydrogen-blocking insulating layer will penetrate into the grain boundary defects, so that during the hydrogenation process, the hydrogen-blocking insulating layer 32 located in the grain boundary defects cannot capture hydrogen. Thus, in the dual 85 experiment, hydrogen ions are prevented from diffusing to the channel region of the first reset transistor T4 to form a stable positive electric field.

[0054] refer to Figure 4 In one embodiment, the display panel further includes a power signal line ELVDD and a data line DATA, both of which are located in the third conductive layer M3, and the first terminal of the driving transistor T1 is electrically connected to the power signal line ELVDD.

[0055] Continue to refer to Figure 4 In one embodiment, the display panel further includes a reset signal line VREFN1, which is located in the second conductive layer M2. The first electrode of the first reset transistor T4 is electrically connected to the reset signal line VREFN1. The signal on the first reset signal line VREFN1 is transmitted through the first reset transistor T4 to the first gate portion GATE1 of the driving transistor T1 and the first electrode plate Cst1 in the pixel capacitor. It should be noted that in this embodiment, the reset signal line VREFN1 can also be called the "first initialization signal line". The reset signal line VREFN1 is responsible for initializing the pixel capacitor.

[0056] refer to Figures 2-5The display panel also includes a buffer layer, a gate insulating layer GI, a capacitor insulating layer, and an interlayer dielectric layer ILD; wherein, the buffer layer is located between the substrate 1001 and the semiconductor layer 2011; the gate insulating layer GI is located between the semiconductor layer 2011 and the first conductive layer M1; the capacitor insulating layer CI is located between the first conductive layer M1 and the second conductive layer M2; and the interlayer dielectric layer ILD is located between the second conductive layer M2 and the third conductive layer M3.

[0057] For example, the capacitor insulating layer CI includes a hydrogen-blocking insulating layer 32 and a first insulating layer 31. The hydrogen-blocking insulating layer 32 is located on the side of the first conductive layer M1 facing away from the substrate 10, and the first insulating layer 31 is located on the side of the hydrogen-blocking insulating layer 32 facing away from the substrate 10. For example, the hydrogen-blocking insulating layer 32 includes a silicon oxide layer (SiOx layer), and the first insulating layer 31 includes a silicon nitride layer (SiNx layer). In related technologies, the material of the capacitor insulating layer is silicon nitride (SiNx). During the formation of the silicon nitride layer (SiNx layer), the material in the silicon nitride (SiNx) can penetrate into the grain boundary defects of the gate portion of the transistor. In the hydrogenation process, the silicon nitride (SiNx) in the grain boundary defects easily captures H. + During the dual 85 experimental RA reliability test, the first reset transistor T4 in the pixel circuit (which controls the reset signal line to initialize the pixel capacitor) was in a PBTS (positive voltage bias and temperature stress) state. + Under the positive electric field of the gate PBTS, a positive electric field (gate off-state electric field) diffuses into the channel region of the transistor TFT, thereby causing the threshold voltage V driving the transistor T1TFT to be increased. TH Due to the significant negative bias, in this embodiment, the capacitor insulating layer CI is configured as a double-layer structure, and a silicon oxide layer (SiOx layer) is disposed between the silicon nitride layer (SiNx layer) and the first conductive layer M1 (the gate portion of the transistor). During the formation of the silicon oxide layer (SiOx layer), silicon oxide will penetrate into the grain boundary defects. However, the silicon oxide in the grain boundary defects cannot capture H in the hydrogenation process. + Thus avoiding H + The threshold voltage of the driving transistor T1 becomes negatively biased due to diffusion after aggregation.

[0058] It should be noted that in this embodiment, the capacitor insulating layer CI comprises a two-layer structure. However, the functions of the hydrogen-blocking insulating layer 32 and the first insulating layer 31 differ depending on their placement positions. For example, placing the hydrogen-blocking insulating layer 32 (SiOx layer) on the side of the first insulating layer 31 (SiNx layer) away from the substrate is called CI Base; placing the hydrogen-blocking insulating layer 32 (SiOx layer) on the side of the first insulating layer 31 (SiNx layer) closer to the substrate is called CI Inversion. Figure 6 As shown, Figure 6 S-TFT PBTS under CIBase and CI Inversion (85℃, V) GS The diagram shows the test results (=20V). It clearly shows that H can only be avoided when CI is inverted. + The threshold voltage of the driving transistor T1 becomes negatively biased due to diffusion after aggregation.

[0059] refer to Figure 2 For example, in the direction perpendicular to the substrate, the thickness ratio of the hydrogen-blocking insulating layer 32 to the first insulating layer 31 is between 0.3 and 0.35. For instance, the thickness ratio of the hydrogen-blocking insulating layer 32 to the first insulating layer 31 can be 0.3, 0.31, 0.32, 0.33, 0.34, or 0.35, etc. The thickness of the hydrogen-blocking insulating layer 32 and the first insulating layer 31 being within this range ensures the capacitance value of the pixel capacitor Cst. Further, in the direction perpendicular to the substrate, the thickness of the first insulating layer 31 is between 300 and 350 angstroms, and the thickness of the hydrogen-blocking insulating layer 32 is between 900 and 1100 angstroms. Preferably, the thickness of the hydrogen-blocking insulating layer 32 can be 300 angstroms, 308 angstroms, 310 angstroms, 315 angstroms, 320 angstroms, 326 angstroms, 330 angstroms, 333 angstroms, 335 angstroms, 340 angstroms, 342 angstroms or 350 angstroms, etc., and the thickness of the first insulating layer 31 can be 900 angstroms, 920 angstroms, 935 angstroms, 940 angstroms, 950 angstroms, 965 angstroms, 980 angstroms, 990 angstroms, 1000 angstroms, 1020 angstroms, 1035 angstroms, 1040 angstroms, 1050 angstroms, 1065 angstroms, 1080 angstroms, 1090 angstroms or 1100 angstroms.

[0060] Continue to refer to Figure 2In one embodiment, the pixel driving circuit further includes a pixel capacitor Cst, which includes a first electrode plate Cst1 (also the lower electrode plate) and a second electrode plate Cst2 (also the upper electrode plate). The second electrode plate Cst2 is located on the side of the first electrode plate Cst1 near the substrate 10. The first electrode plate Cst1 is located in the first conductive layer M1, and the first gate portion GATE1 of the driving transistor T1 is multiplexed as the first electrode plate Cst1 of the pixel capacitor. It can be understood that the first gate portion GATE1 of the driving transistor T1 and the first electrode plate Cst1 of the pixel capacitor share a common structure. The second electrode plate Cst2 is located in the second conductive layer M2, and the first electrode of the driving transistor T1 is electrically connected to the second electrode plate Cst2 of the pixel capacitor Cst.

[0061] Continue to refer to Figure 2 In some embodiments, the display panel further includes a planarization layer PLA, which is located on the side of the third conductive layer M3 away from the substrate 10.

[0062] Continue to refer to Figure 2 In some embodiments, the display panel further includes a pixel definition layer (PDL) located on the side of the planarization layer PLA away from the substrate 10. The pixel definition layer located in the display area AA defines pixel openings for defining the positions of the light-emitting elements 40.

[0063] Continue to refer to Figure 2 In some embodiments, the display panel further includes a light-emitting element 40 located in the display area AA and on the side of the first insulating layer 31 away from the substrate 10 (specifically, on the side of the planarization layer PLA away from the substrate 10). The light-emitting element 40 includes an anode 41, a light-emitting layer 42, and a cathode 43 sequentially stacked on the planarization layer PLA. At least a portion of the anode 41 is located within a pixel opening, and the anode 41 is connected to the third conductive layer M3 through a via penetrating the planarization layer PLA. The light-emitting layer 42 is stacked on the side of the anode 41 away from the substrate 10, and the cathode 43 is stacked on the side of the light-emitting layer 42 away from the substrate 10. A support pillar SPC is disposed between the cathode 43 and the pixel definition layer PDL.

[0064] Continue to refer to Figure 2 In some embodiments, the display panel further includes conductive gold balls 52 located in the bonding area and gold fingers 51 located on the conductive gold balls 52. The conductive gold balls 52 are electrically connected to a first conductive layer M1 (e.g., M1Connector and IC Pad-M1) located in the bonding area; the material of the conductive gold balls 52 may include metal, such as gold (Au); correspondingly, the solder pads are located in the bonding area and in a third conductive layer M3. Of course, in other embodiments, the conductive gold balls 52 may be replaced with conductive adhesive.

[0065] Based on the same inventive concept, this disclosure also provides a display device, which includes the display panel in any of the above embodiments. The display device can be a mobile phone, a computer, a television, a smart wearable display device, etc., and the embodiments of this application do not make any special limitations in this regard. The beneficial effects of the display device are the same as those of the display panel, and will not be repeated here.

[0066] It should be noted that the above description describes some embodiments of this disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0067] This disclosure is intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A display panel, characterized by, The display panel comprises: a substrate, a semiconductor layer located on the substrate, the semiconductor layer comprising a plurality of channel regions; a first conductive layer located on a side of the semiconductor layer away from the substrate, the first conductive layer comprising a plurality of gate portions superposed with corresponding channel regions; a hydrogen-blocking insulating layer located on a side of the first conductive layer away from the substrate; a first insulating layer located on a side of the hydrogen-blocking insulating layer away from the substrate.

2. The display panel of claim 1, wherein: the hydrogen-blocking insulating layer comprises a silicon oxide layer; and the first insulating layer comprises a silicon nitride layer.

3. The display panel of claim 1, wherein: in a direction perpendicular to a plane on which the substrate lies, a thickness ratio of the hydrogen-blocking insulating layer to the first insulating layer is between 0.3 and 0.

35.

4. The display panel of claim 1, wherein: in a direction perpendicular to a plane on which the substrate lies, a thickness of the first insulating layer is between 300 and 350 angstroms, and a thickness of the hydrogen-blocking insulating layer is between 900 and 1100 angstroms.

5. The display panel of claim 1, wherein: the gate portions comprise columnar crystal structures, the columnar crystal structures comprise grain boundary defects, and part of the hydrogen-blocking insulating layer is located in the grain boundary defects.

6. The display panel of claim 1, wherein: a material of the first conductive layer comprises molybdenum.

7. The display panel of claim 1, wherein: the display panel comprises a drive transistor, a plurality of the gate portions comprises a first gate portion of the drive transistor, a plurality of the channel regions comprises a first channel region of the drive transistor, and a footprint of the first gate portion on the substrate coincides with a footprint of the first channel region of the drive transistor on the substrate.

8. The display panel of claim 7, wherein: the semiconductor layer further comprises a first source region and a first drain region located on two sides of the first channel region, a first electrode of the drive transistor is electrically connected to the first source region, and a second electrode of the drive transistor is electrically connected to the first drain region.

9. The display panel of claim 8, wherein: the display panel comprises a pixel capacitor, the pixel capacitor comprises a first electrode plate and a second electrode plate, the first electrode plate is located on a side of the second electrode plate away from the substrate, the first electrode plate is located on the first conductive layer, and the first electrode plate and the first gate portion of the drive transistor are the same structure; the display panel further comprises a second conductive layer located on a side of the hydrogen-blocking insulating layer away from the substrate, and the second electrode plate is located on the second conductive layer, the first electrode of the drive transistor is electrically connected to the second electrode plate of the pixel capacitor.

10. The display panel of claim 9, wherein: The display panel comprises a first reset transistor, the plurality of gate portions comprises a second gate portion of the first reset transistor, the plurality of channel regions comprises a second channel region of the first reset transistor, and a projection of the second gate portion on the substrate overlaps a projection of the second channel region on the substrate. 11.The display panel of claim 10, wherein, The semiconductor layer further comprises a second source region and a second drain region located on both sides of the second channel region, a first electrode of the first reset transistor is electrically connected to the second source region, a second electrode of the first reset transistor is electrically connected to the second drain region, and the second electrode of the first reset transistor is electrically connected to the first gate portion of the driving transistor. 12.The display panel of claim 11, wherein, The display panel further comprises a third conductive layer, and the third conductive layer is located on a side of the second conductive layer away from the substrate. 13.The display panel of claim 12, wherein, The display panel further comprises a power signal line and a data line, and at least one of the power signal line and the data line is located on the third conductive layer, and a first electrode of the driving transistor is electrically connected to the power signal line. 14.The display panel of claim 11, wherein, The driving transistor is a p-type transistor. 15.The display panel of claim 11, wherein, The display panel further comprises a reset signal line, the reset signal line is located on the second conductive layer, a first electrode of the first reset transistor is electrically connected to the reset signal line, and a signal on the reset signal line is transmitted to the first gate portion of the driving transistor through the first reset transistor. 16.The display panel of claim 1, wherein, The display panel comprises a display area and a non-display area, and the non-display area comprises a binding area located on a side of the display area. The display panel further comprises a light emitting element, and the light emitting element is located on the display area and on a side of the first insulating layer away from the substrate.

17. A display device comprising: The display panel comprises the display panel of any one of claims 1-16.

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