Display device and electronic device including the same

Abstract

A display device and an electronic device including the same are disclosed. The display device includes: a light emitting diode; a transistor disposed on and electrically connected to the light emitting diode; and a substrate disposed under the transistor and including a central region and a hole region adjacent to the central region, in which the substrate includes an organic material and a first substrate, and a first hole disposed in the hole region in the first substrate. Since the hole is provided in the hole region of the substrate, curl of the substrate may be prevented or reduced without excessively deteriorating durability of the substrate.

Description

Technical Field

[0001] This disclosure relates to a display device, a method of manufacturing the display device, and an electronic device including the display device. More specifically, this disclosure relates to a display device for providing visual information, a method of manufacturing the display device, and an electronic device including the display device. Background Technology

[0002] Recently, foldable displays have emerged rapidly as the next generation of displays. Foldable displays can use a polyimide substrate instead of a glass substrate for the display device and can maintain display performance even when bent or folded.

[0003] Typically, to manufacture display devices such as foldable, rollable, or stretchable displays, a polyimide substrate is attached to a carrier substrate. The carrier substrate should then be separated from the polyimide substrate. However, if the carrier substrate cannot be successfully separated from the polyimide substrate, the polyimide substrate may be damaged, or the separation process may need to be repeated, resulting in reduced process yield. Therefore, various methods for manufacturing display devices are currently being developed. Utility Model Content

[0004] The purpose of this invention is to provide a display device in which holes are provided in the hole area of ​​the substrate to prevent the substrate from curling.

[0005] According to an embodiment of the present disclosure, a display device includes: a light-emitting diode; a transistor disposed below the light-emitting diode and electrically connected to the light-emitting diode; and a substrate disposed below the transistor and including a central region and a hole region adjacent to the central region, wherein the substrate includes an organic material and a first substrate, and a first hole is disposed in the hole region in the first substrate.

[0006] In embodiments of this disclosure, the hole region is adjacent to the edge of the substrate.

[0007] In embodiments of this disclosure, the substrate further includes a first barrier layer disposed on the first substrate and filling the first hole.

[0008] In embodiments of this disclosure, the substrate further includes: a second substrate disposed on the first barrier layer and comprising an organic material, wherein the second substrate has a second pore disposed in the pore region; and a second barrier layer disposed on the second substrate and filling the second pore.

[0009] In embodiments of this disclosure, the second hole exposes at least a portion of the first barrier layer.

[0010] In embodiments of this disclosure, the first hole and the second hole do not overlap in a plan view.

[0011] In embodiments of this disclosure, in a plan view, at least one of the first holes is partially overlapped with at least one of the second holes.

[0012] In embodiments of this disclosure, in a plan view, at least one of the first holes is completely overlapped with at least one of the second holes.

[0013] In embodiments of this disclosure, each of the first holes has a first planar area, and each of the second holes has a second planar area, wherein the first planar area and the second planar area are the same as each other.

[0014] In embodiments of this disclosure, each of the first holes has a first planar area, and each of the second holes has a second planar area, wherein the first planar area and the second planar area are different from each other.

[0015] In embodiments of this disclosure, the area of ​​the first plane is greater than the area of ​​the second plane.

[0016] In embodiments of this disclosure, the area of ​​the first plane is smaller than the area of ​​the second plane.

[0017] In embodiments of this disclosure, each of the first and second holes has a circular planar shape.

[0018] In embodiments of this disclosure, the hole region includes: a first corner region to a fourth corner region extending from the corner of the central region; a first connecting region connecting the first corner region and the second corner region to each other; a second connecting region connecting the second corner region and the third corner region to each other; a third connecting region connecting the third corner region and the fourth corner region to each other; and a fourth connecting region connecting the fourth corner region and the first corner region to each other.

[0019] In embodiments of this disclosure, the first hole and the second hole are located in the first corner region to the fourth corner region.

[0020] In embodiments of this disclosure, the first hole and the second hole are located in the first connection region to the fourth connection region.

[0021] According to embodiments of the present disclosure, a method of manufacturing a display device includes: forming a first substrate on a carrier substrate, the first substrate including an organic material, a central region, and a hole region at least partially surrounding the central region; forming a first hole in the hole region of the first substrate; forming a first barrier layer in the first hole and on the first substrate; forming a second substrate including an organic material on the first barrier layer; forming a second hole in the second substrate exposing the first barrier layer; and forming a second barrier layer in the second hole and on the second substrate.

[0022] In embodiments of this disclosure, the method further includes: separating the first substrate and the carrier substrate from each other after forming the second barrier layer.

[0023] In embodiments of this disclosure, each of the first and second holes is formed by an etching process in the steps of forming the first hole and forming the second hole.

[0024] In the embodiments of this disclosure, the etching process is a dry etching process.

[0025] According to embodiments of the present disclosure, an electronic device includes a housing and a display device housed within the housing. The display device displays an image and includes a light-emitting diode (LED), a transistor disposed below the LED and electrically connected to the LED, and a substrate disposed below the transistor and including a central region and a hole region adjacent to the central region. The substrate includes an organic material and a first substrate, and a first hole is disposed in the hole region of the first substrate.

[0026] In embodiments of this disclosure, since the holes are located in the hole region of the substrate, substrate curling can be prevented or reduced without causing excessive degradation of the substrate's durability. Attached Figure Description

[0027] The above and other features of this disclosure will become more apparent from the detailed description of embodiments thereof with reference to the accompanying drawings.

[0028] Figure 1 This is a perspective view showing a display device according to an embodiment of the present disclosure.

[0029] Figure 2 It is along Figure 1 A sectional view taken from line I-I'.

[0030] Figure 3 It is shown Figure 2 A cross-sectional view of the display panel.

[0031] Figure 4 It is shown Figure 3 A plan view of an embodiment of the substrate.

[0032] Figure 5 It is shown Figure 4 An enlarged plan view of an example of region A.

[0033] Figure 6 It is along Figure 5 The sectional view taken from line II-II'.

[0034] Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16, Figure 17 and Figure 18 This illustrates an embodiment of the present disclosure for manufacturing Figure 6 The view of the base method.

[0035] Figure 19 According to embodiments of this disclosure Figure 4 A magnified plan view of region A.

[0036] Figure 20 It is along Figure 19 The sectional view taken from line III-III'.

[0037] Figure 21 According to embodiments of this disclosure Figure 4 A magnified plan view of region A.

[0038] Figure 22 According to embodiments of this disclosure Figure 4 A magnified plan view of region A.

[0039] Figure 23 According to embodiments of this disclosure Figure 3 An enlarged planar view of the base.

[0040] Figure 24 According to embodiments of this disclosure Figure 3 An enlarged planar view of the base.

[0041] Figure 25 According to embodiments of this disclosure Figure 3 An enlarged planar view of the base.

[0042] Figure 26 According to embodiments of this disclosure Figure 3 An enlarged planar view of the base.

[0043] Figure 27 According to embodiments of this disclosure Figure 4 A magnified plan view of region A.

[0044] Figure 28 It is along Figure 27 A sectional view taken from line IV-IV'.

[0045] Figure 29 This is a block diagram illustrating an electronic device according to an embodiment of the present disclosure.

[0046] Figure 30 This is a perspective view illustrating an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0047] The illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0048] In this specification, a plane may be defined by a first direction D1 and a second direction D2 intersecting the first direction D1. For example, the second direction D2 may be substantially perpendicular to the first direction D1. Additionally, a third direction D3 may be the normal direction of the plane. For example, the third direction D3 may be substantially perpendicular to the plane formed by the first direction D1 and the second direction D2.

[0049] Figure 1 This is a perspective view showing a display device according to an embodiment of the present disclosure.

[0050] Reference Figure 1 The display device DD may include a display area DA and a peripheral area SA. The display area DA may be adjacent to the peripheral area SA. For example, the display area DA may be surrounded by the peripheral area SA.

[0051] The display area DA can be an area that displays an image by generating light or adjusting the transmittance of light provided from an external light source. The peripheral area SA can be an area where no image is displayed. However, embodiments of this disclosure are not limited to this; at least a portion of the peripheral area SA can display an image.

[0052] The display area DA can display multiple image IMs. Users can receive information from the display device DD through multiple image IMs.

[0053] Figure 2 It is along Figure 1 A sectional view taken from line I-I'.

[0054] Reference Figure 2 The display device DD may include a cover film CF, a plate PT, a display panel DP, an adhesive component AD, a light-blocking component BM, a window layer WL, and a protective film PL.

[0055] A cover film CF can be disposed at the rear end of the display device DD to protect the display device DD from external impacts. For example, the cover film CF can be formed on the rear surface of the display device DD. For example, the cover film CF can include at least one of polyurethane (PU), thermoplastic polyurethane (TPU), silicone (Si), and polydimethylacrylamide (PDMA). These materials can be used alone or in combination with each other. However, the embodiments disclosed herein are not limited thereto.

[0056] The plate PT can be disposed on the cover film CF. The plate PT can support the display panel DP and protect the display device DD from external impacts. For example, even when an external force is applied from outside the display device DD, the plate PT can keep the display panel DP in a relatively flat state. The plate PT can include rigid or semi-rigid materials. For example, the plate PT can include at least one of iron, chromium, carbon, nickel, silicon, manganese, and molybdenum. These materials can be used alone or in combination with each other. However, the embodiments of this disclosure are not limited thereto.

[0057] The display panel DP can be disposed on the board PT. The display panel DP can receive electrical signals and emit light, enabling the display device DD to provide visual information to the user. For example, the display panel DP can be an organic light-emitting display panel or an inorganic light-emitting display panel. However, the embodiments of this disclosure are not limited thereto. Referring later... Figure 3 Detailed description of the Display Panel (DP).

[0058] An adhesive member AD can be disposed on the display panel DP. The adhesive member AD can bond the display panel DP and components disposed thereon to each other. For example, the adhesive member AD can bond the display panel DP and the window layer WL to each other. For example, the adhesive member AD can include pressure-sensitive adhesive (PSA), optically clear adhesive (OCA), or optically clear resin (OCR). However, the embodiments disclosed herein are not limited to this.

[0059] A light-blocking component BM can be disposed on the adhesive component AD. The light-blocking component BM provides convenience to the user by blocking light from the rear of the display device DD. For example, the light-blocking component BM may include a light-absorbing material. For example, the light-blocking component BM may include an inorganic black pigment or an organic black pigment. The inorganic black pigment may be carbon black, and the organic black pigment may include at least one of lactam black, perylene black, and aniline black. These materials may be used alone or in combination with each other. However, the embodiments disclosed herein are not limited thereto.

[0060] The window layer WL can be disposed on the adhesive member AD. The window layer WL can include a substantially transparent material. For example, the window layer WL can be glass or plastic. However, the embodiments of this disclosure are not limited thereto.

[0061] A protective film PL can be disposed on the window layer WL. The protective film PL can protect the window layer WL from effects such as frontal impacts and scratches. The protective film PL can include a single-layer and / or multi-layer structure. For example, the protective film PL can include at least one of a substrate layer, a hard coating layer, a low refractive index layer, and an anti-fingerprint layer. However, the embodiments disclosed herein are not limited to this.

[0062] Figure 3 It is shown Figure 2 A cross-sectional view of the display panel.

[0063] Reference Figure 1 and Figure 3 The display panel DP may include a substrate SUB, a buffer layer BUF, a gate insulating layer GI, a transistor TR, an interlayer insulating layer IL, a connection electrode CNE, a first via layer VIA1, a second via layer VIA2, a light-emitting diode LED, a pixel limiting layer PDL, and a packaging layer ENC.

[0064] A transistor (TR) may include an active layer (ACT), a gate electrode (GE), a source electrode (SE), and a drain electrode (DE). A light-emitting diode (LED) may include a pixel electrode (PE), an emissive layer (EL), and a common electrode (CE).

[0065] The substrate SUB can include, for example, a glass substrate, a metal substrate, a plastic substrate, etc. However, the embodiments of this disclosure are not limited to this, and the substrate SUB can be an inorganic layer, an organic layer, or a composite material layer.

[0066] A buffer layer (BUF) can be disposed on the substrate SUB. The buffer layer BUF prevents impurities such as oxygen and moisture from penetrating into the upper part of the substrate SUB. The buffer layer BUF may include inorganic insulating material.

[0067] The active layer ACT can be disposed on the buffer layer BUF. The active layer ACT can include, for example, oxide semiconductors, silicon semiconductors, organic semiconductors, etc. For example, oxide semiconductors can include at least one of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). For example, silicon semiconductors can include amorphous silicon, polycrystalline silicon, etc. The active layer ACT can include a source region, a drain region, and a channel region located between the source and drain regions.

[0068] The gate insulating layer GI can be disposed on the buffer layer BUF. For example, the gate insulating layer GI can be disposed on the buffer layer BUF and cover the active layer ACT. The gate insulating layer GI may include an inorganic insulating material. In embodiments of this disclosure, the gate insulating layer GI can be formed entirely in the display area DA and the peripheral area SA.

[0069] The gate electrode GE can be disposed on the gate insulating layer GI. The gate electrode GE can be at least partially stacked with the channel region of the active layer ACT. The gate electrode GE can include a conductive material such as a metal, alloy, conductive metal nitride, conductive metal oxide, or transparent conductive material. Examples of conductive materials that can be used in the gate electrode (GE) include gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), tungsten (W), copper (Cu), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), alloys containing aluminum, alloys containing silver, alloys containing copper, alloys containing molybdenum, aluminum nitride (AlN), tungsten nitride (WN), titanium nitride (TiN), chromium nitride (CrN), tantalum nitride (TaN), strontium ruthenium oxide (SrRuO), zinc oxide (ZnO), indium tin oxide (ITO), tin oxide (SnO), indium oxide (InO), gallium oxide (GaO), indium zinc oxide (IZO), etc. These materials can be used alone or in combination with each other. Optionally, the gate electrode (GE) can have a single-layer structure or a multilayer structure including multiple conductive layers.

[0070] An interlayer insulating layer IL can be disposed on the gate electrode GE. For example, the interlayer insulating layer IL can be disposed on the gate insulating layer GI and cover the gate electrode GE. The interlayer insulating layer IL may include an inorganic insulating material.

[0071] The source electrode SE and drain electrode DE can be disposed on the interlayer insulating layer IL. The source electrode SE and drain electrode DE can be connected to the active layer ACT. For example, the source electrode SE can contact the source region of the active layer ACT, and the drain electrode DE can contact the drain region of the active layer ACT. Each of the source electrode SE and drain electrode DE may include a conductive material.

[0072] The first via layer VIA1 can be disposed on the source electrode SE and the drain electrode DE. For example, the first via layer VIA1 can be disposed on the interlayer insulating layer IL, and the source electrode SE and the drain electrode DE can be covered on the interlayer insulating layer IL. The first via layer VIA1 may include an organic insulating material. In embodiments of this disclosure, the first via layer VIA1 can be formed in the portion of the display area DA and the peripheral area SA adjacent to the display area DA.

[0073] The connection electrode CNE can be disposed on the first via layer VIA1. The connection electrode CNE can transmit the signal from the transistor TR to the light-emitting diode (LED). For example, the connection electrode CNE can include metals, alloys, metal nitrides, conductive metal oxides, transparent conductive materials, etc. These materials can be used alone or in combination with each other. However, the embodiments disclosed herein are not limited thereto.

[0074] The second via layer VIA2 can be disposed on the connecting electrode CNE. For example, the second via layer VIA2 can be disposed on the first via layer VIA1 and cover the connecting electrode CNE. The second via layer VIA2 can include a material that is substantially the same as or the same as the first via layer VIA1.

[0075] The pixel electrode PE can be disposed on the second via layer VIA2. The pixel electrode PE may include a conductive material. The pixel electrode PE can be connected to the drain electrode DE via the connection electrode CNE. Therefore, the pixel electrode PE can be electrically connected to the transistor TR.

[0076] A pixel defining layer (PDL) may be disposed on a pixel electrode (PE). For example, the pixel defining layer (PDL) may expose at least a portion of the pixel electrode (PE). The pixel defining layer (PDL) may comprise an inorganic insulating material or an organic insulating material.

[0077] The light-emitting layer EL can be disposed on the pixel electrode PE. For example, the light-emitting layer EL can be disposed within an opening formed in the pixel defining layer PDL. For example, the light-emitting layer EL can be at least partially surrounded by the pixel defining layer PDL. The light-emitting layer EL can include at least one of organic light-emitting materials and quantum dots. However, the embodiments disclosed herein are not limited to this.

[0078] The common electrode CE can be disposed on the light-emitting layer EL. The common electrode CE can also be disposed on the pixel-defining layer PDL. For example, the common electrode CE can be continuously disposed on the light-emitting layer EL and the pixel-defining layer PDL. The common electrode CE may include a conductive material. The light-emitting layer EL can emit light based on the voltage difference between the pixel electrode PE and the common electrode CE.

[0079] An encapsulation layer ENC can be disposed on the common electrode CE. The encapsulation layer ENC may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In embodiments of this disclosure, the inorganic and organic encapsulation layers may be disposed alternately. For example, the organic encapsulation layer may include a cured polymer such as polyacrylate, epoxy resin, or silicone resin. For example, the inorganic encapsulation layer may include silicon oxide, silicon nitride, silicon carbide, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc.

[0080] Figure 4 It is shown Figure 3 A plan view of an embodiment of the substrate.

[0081] Reference Figure 3 and Figure 4 The substrate SUB may include a central region CA and a hole region HA that at least partially surrounds the central region CA. For example, the hole region HA may be configured to be adjacent to the edge of the substrate SUB.

[0082] Multiple holes HL can be set in the hole region HA. Holes HL can be set in the hole region HA along a first direction D1 and / or a second direction D2. Figure 4 In this embodiment, the holes HL are arranged throughout the hole region HA, but embodiments of this disclosure are not necessarily limited to this. For example, the holes HL may be formed only in a portion of the hole region HA. This will be referred to later. Figures 11 to 14 describe.

[0083] In embodiments of this disclosure, the hole region HA may include a corner region CNA and a connecting region LA. The corner region CNA may extend from the corner of the central region CA. The corner region CNA may include a first corner region CNA1, a second corner region CNA2, a third corner region CNA3, and a fourth corner region CNA4. The connecting region LA may include a first connecting region LA1, a second connecting region LA2, a third connecting region LA3, and a fourth connecting region LA4.

[0084] For example, the first corner region CNA1, the second corner region CNA2, the third corner region CNA3, and the fourth corner region CNA4 can be positioned sequentially at the corresponding corners of the base SUB in a counterclockwise direction. For example, the second corner region CNA2 can be positioned spaced apart from the first corner region CNA1 in the second direction D2. The third corner region CNA3 can be positioned spaced apart from the second corner region CNA2 in the first direction D1. The fourth corner region CNA4 can be positioned spaced apart from the third corner region CNA3 in a direction opposite to the second direction D2. The first corner region CNA1 can be positioned spaced apart from the fourth corner region CNA4 in a direction opposite to the first direction D1.

[0085] The first connecting region LA1 connects the first corner region CNA1 and the second corner region CNA2 to each other and extends in the second direction D2. The second connecting region LA2 connects the second corner region CNA2 and the third corner region CNA3 to each other and extends in the first direction D1. The third connecting region LA3 connects the third corner region CNA3 and the fourth corner region CNA4 to each other and extends in the second direction D2. The fourth connecting region LA4 connects the fourth corner region CNA4 and the first corner region CNA1 to each other and extends in the first direction D1.

[0086] The substrate SUB can have a multilayer structure. For example, the substrate SUB can have a two-layer structure comprising an organic material layer and an inorganic material layer. As another example, the substrate SUB can have a multilayer structure comprising at least two organic layers and at least one inorganic layer. (Refer to the following...) Figures 5 to 14 The base SUB is described in detail.

[0087] Figure 5 It is shown Figure 4An enlarged plan view of an example of region A. Figure 6 It is along Figure 5 A sectional view taken along line II-II'. Specifically, Figure 5 and Figure 6 The substrate SUB in the figure shows an example of a substrate SUB with a multi-layer structure.

[0088] Reference Figure 5 and Figure 6 In embodiments of this disclosure, the substrate SUB may include a first substrate SUB1, a first barrier layer BL1, a second substrate SUB2, and a second barrier layer BL2.

[0089] Each of the first substrate SUB1 and the second substrate SUB2 may comprise an organic material. For example, each of the first substrate SUB1 and the second substrate SUB2 may comprise a polyimide resin. However, embodiments of this disclosure are not limited thereto. Each of the first substrate SUB1 and the second substrate SUB2 may comprise at least one selected from acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, silicone resin, polyamide resin, and perylene resin.

[0090] In embodiments of this disclosure, a first hole HL1 may be disposed in the region where a first substrate SUB1 and a hole region HA overlap. A second hole HL2 may be disposed in the region where a second substrate SUB2 and a hole region HA overlap. That is, in embodiments of this disclosure, located at reference... Figure 4 The holes HL in the hole region HA of the substrate SUB described can be a set of first holes HL1 and second holes HL2, with the first holes HL1 disposed in the first substrate SUB1 and the second holes HL2 disposed in the second substrate SUB2.

[0091] A first barrier layer BL1 may be disposed on a first substrate SUB1. The first barrier layer BL1 may fill the first pore HL1 of the first substrate SUB1. The first barrier layer BL1 may comprise inorganic materials, organic materials, or organic-inorganic composites such as oxides or nitrides, and may have a single-layer or multi-layer structure of inorganic and organic materials. However, the embodiments disclosed herein are not limited thereto.

[0092] The second substrate SUB2 can be disposed on the first barrier layer BL1. At least a portion of the first barrier layer BL1 can be exposed by the second hole HL2 of the second substrate SUB2.

[0093] A second barrier layer BL2 may be disposed on a second substrate SUB2. The second barrier layer BL2 may fill the second pore HL2 of the second substrate SUB2. The second barrier layer BL2 may comprise inorganic materials, organic materials, or organic-inorganic composites such as oxides or nitrides, and may have a single-layer or multi-layer structure of inorganic and organic materials. However, the embodiments disclosed herein are not limited thereto.

[0094] In embodiments of this disclosure, such as Figure 5 As shown, the first hole HL1 and the second hole HL2 may not overlap in the plan view. For example, the first hole HL1 and the second hole HL2 may be defined as alternating with each other in the second direction D2 in the plan view. However, this disclosure is not limited to this. For example, the first hole HL1 and the second hole HL2 may be defined as alternating with each other in the first direction D1 in the plan view, or alternating with each other in both the first direction D1 and the second direction D2. Because the first hole HL1 and the second hole HL2 are alternately located in the hole region HA of the substrate SUB, the direction of the stress that may be generated in the first substrate SUB1 and the direction of the stress that may be generated in the second substrate SUB2 may be different from each other. Therefore, curling of the substrate SUB can be prevented or reduced.

[0095] In embodiments of this disclosure, the planar shape of the hole HL can be circular. For example, the planar shape of each of the first hole HL1 and the second hole HL2 can be circular. However, embodiments of this disclosure are not limited to this. For example, the planar shape of the hole HL can be elliptical, polygonal, etc.

[0096] Each of the first holes HL1 may have a first planar area in the plan view. Each of the second holes HL2 may have a second planar area in the plan view. In embodiments of this disclosure, the first planar area of ​​each of the first holes HL1 may be substantially the same as or identical to the second planar area of ​​each of the second holes HL2. However, this disclosure is not limited thereto.

[0097] Figures 7 to 18 This illustrates an embodiment of the present disclosure for manufacturing Figure 6 The view of the base method.

[0098] Reference Figure 6 and Figure 7 The first substrate SUB1 can be formed on the carrier substrate CSUB. The first substrate SUB1 can be formed by depositing an organic material including polyimide on the carrier substrate CSUB.

[0099] When forming the display device DD, the carrier substrate CSUB can temporarily support the components included in the display device DD. The carrier substrate CSUB can include materials with excellent rigidity and heat resistance. For example, the carrier substrate CSUB can include at least one of glass and quartz. These materials can be used alone or in combination with each other. However, the embodiments disclosed herein are not limited thereto.

[0100] Further reference Figures 8 to 10 A first photoresist PR1 can be formed on a first substrate SUB1. At least a portion of the first photoresist PR1 can be removed by an exposure process. For example, at least a portion of the first photoresist PR1 can be exposed by an exposure process. An etching process can be performed on the exposed upper surface of the first substrate SUB1 using the first photoresist PR1 patterned via an exposure process. For example, the etching process can be a dry etching process. However, embodiments of this disclosure are not limited to this.

[0101] After the etching process, a first hole HL1 can be formed in the first substrate SUB1. After the first hole HL1 is formed in the first substrate SUB1, the first photoresist PR1 can be removed.

[0102] Further reference Figure 11 A first barrier layer BL1 can be formed on a first substrate SUB1. The first barrier layer BL1 can be formed by depositing an inorganic material on the first substrate SUB1. However, this disclosure is not limited to this. For example, the first barrier layer BL1 can be formed on the first substrate SUB1 while simultaneously filling the first pore HL1.

[0103] Further reference Figure 12 A second substrate SUB2 can be formed on the first barrier layer BL1. The second substrate SUB2 can be formed by depositing an organic material including polyimide on the first barrier layer BL1.

[0104] Further reference Figure 13 , Figure 14 and Figure 15 A second photoresist PR2 can be applied to a second substrate SUB2. At least a portion of the second photoresist PR2 can be removed by an exposure process. That is, at least a portion of the second photoresist PR2 can be exposed by an exposure process. An etching process can be performed on the exposed upper surface of the second substrate SUB2 using the second photoresist PR2 patterned via the exposure process. Therefore, at least a portion of the second substrate SUB2 can be removed by the etching process. That is, a second hole HL2 can be formed in the second substrate SUB2. Thereafter, the second photoresist PR2 can be removed.

[0105] Further reference Figure 16 A second barrier layer BL2 can be formed on the second substrate SUB2. The second barrier layer BL2 can be formed by depositing an inorganic material on the second substrate SUB2. However, this disclosure is not limited to this. Specifically, the second barrier layer BL2 can be formed on the second substrate SUB2 while simultaneously filling the second pore HL2.

[0106] Further reference Figure 17 and Figure 18 The carrier substrate CSUB can be removed after the second hole HL2 is formed in the second substrate SUB2. Specifically, the carrier substrate CSUB can be removed and separated from the first substrate SUB1. For example, the carrier substrate CSUB can be separated from the first substrate SUB1 by means of a laser emitted from the laser device LS, etc. As a result, a... Figure 18 The base SUB shown.

[0107] Figure 19 According to embodiments of this disclosure Figure 4 A magnified plan view of region A. Figure 20 It is along Figure 19 The sectional view taken from line III-III'.

[0108] Reference Figure 19 and Figure 20 Description and reference Figure 5 and Figure 6 The difference in the description may lie only in the location of the first hole HL1 and the second hole HL2. Therefore, repeated descriptions can be omitted or simplified.

[0109] In addition, besides the difference in the positions of the first hole HL1 and the second hole HL2, according to the reference Figure 19 and Figure 20 The method for manufacturing the substrate SUB in the embodiments of the present invention can be compared with that in the reference embodiment. Figures 7 to 18 The manufacturing methods described are basically the same. Therefore, the manufacturing process based on the reference can be omitted. Figure 19 and Figure 20 The method of the base SUB in the embodiment.

[0110] Reference Figure 19 and Figure 20 At least one of the first holes HL1 and at least one of the second holes HL2 can be stacked on top of each other in the plan view.

[0111] In embodiments of this disclosure, such as Figure 19As shown, at least one of the first holes HL1 can be completely overlapped with at least one of the second holes HL2 in a plan view. For example, the first holes HL1 and the second holes HL2 can correspond to each other in a one-to-one manner, and any one of the first holes HL1 can be completely overlapped with the corresponding second hole in the second hole HL2 in a plan view.

[0112] However, this disclosure is not limited thereto. In embodiments of this disclosure, at least one of the first holes HL1 may partially overlap with at least one of the second holes HL2 in a plan view. For example, the first holes HL1 and the second holes HL2 may correspond to each other in a one-to-one manner, and one of the first holes HL1 may partially overlap with the corresponding second hole in the second hole HL2 in a plan view.

[0113] Figure 21 According to embodiments of this disclosure Figure 4 A magnified plan view of region A. Figure 22 According to embodiments of this disclosure Figure 4 A magnified plan view of region A.

[0114] Reference Figure 21 and Figure 22 Description and reference Figure 5 The differences between the descriptions may lie only in the positions of the first hole HL1 and the second hole HL2, and the planar areas of the first hole HL1 and the second hole HL2. Therefore, repeated descriptions can be omitted or simplified.

[0115] Reference Figure 21 and Figure 22 In embodiments of this disclosure, the first planar area of ​​each of the first holes HL1 may be different from the second planar area of ​​each of the second holes HL2.

[0116] In embodiments of this disclosure, such as Figure 21 As shown, the area of ​​the first plane can be larger than the area of ​​the second plane. In this case, each of the first holes HL1 can overlap with at least two of the second holes HL2 in the planar view. However, this disclosure is not limited to this. For example, even when the area of ​​the first plane is larger than the area of ​​the second plane, each of the first holes HL1 can overlap with one of the second holes HL2 in the planar view, or can be not overlapped with the second holes HL2 in the planar view. Additionally, in Figure 21 In the diagram, each of the first holes HL1 is shown as partially superimposed on each of the corresponding second holes HL2 in a plan view, but this disclosure is not limited thereto, and each of the first holes HL1 may be completely superimposed on each of the corresponding second holes HL2 in a plan view.

[0117] In embodiments of this disclosure, such as Figure 22As shown, the first planar region may be smaller than the second planar region. In this case, each of the second holes HL2 may overlap with at least two of the first holes HL1 in the planar view. However, this disclosure is not limited to this. For example, even when the first planar region is smaller than the second planar region, each of the second holes HL2 may overlap with one of the first holes HL1 in the planar view, or may not overlap with the first holes HL1 in the planar view. Additionally, in Figure 22 In the diagram, each of the second holes HL2 is shown as overlapping a portion of the corresponding first hole HL1 in a plan view; however, this disclosure is not limited thereto, and each of the second holes HL2 may be completely overlapping each of the corresponding first holes HL1 in a plan view.

[0118] Figure 23 According to embodiments of this disclosure Figure 3 An enlarged planar view of the base. Figure 24 According to embodiments of this disclosure Figure 3 An enlarged planar view of the base.

[0119] Reference Figure 23 and Figure 24 In embodiments of this disclosure, the hole HL may be provided only in the corner region CNA of the substrate SUB. For example, as Figure 23 As shown, two or more holes HL can be set in each of the corner regions CNA. For another example, as... Figure 24 As shown, one of the holes HL can be located in each of the corner regions CNA. For example, the hole HL can be located only in the corner regions CNA of the substrate SUB, and the hole HL can be omitted from the connection region LA. By providing the hole HL only in the corner regions CNA, curling of the substrate SUB can be prevented or reduced without excessively degrading the durability of the substrate SUB.

[0120] Figure 25 According to embodiments of this disclosure Figure 3 An enlarged planar view of the base. Figure 26 According to embodiments of this disclosure Figure 3 An enlarged planar view of the base.

[0121] Reference Figure 25 and Figure 26 In embodiments of this disclosure, the hole HL may be provided only in the connection region LA of the substrate SUB. For example, as Figure 25 As shown, two or more holes HL can be set in each of the connection areas LA. For another example, as... Figure 26As shown, holes HL can be provided in a one-to-one correspondence within the connection regions LA. For example, a single hole HL can be provided in each of the connection regions LA. Alternatively, holes HL can be provided only in the connection regions LA of the substrate SUB, and holes HL may not be provided in the corner regions CNA. By providing holes HL only in the connection regions LA, curling of the substrate SUB can be prevented or reduced without excessively degrading the durability of the substrate SUB.

[0122] Figure 27 According to embodiments of this disclosure Figure 4 A magnified plan view of region A. Figure 28 It is along Figure 27 A sectional view taken from line IV-IV'.

[0123] Specifically, in addition to the layered structure of the base SUB, refer to Figure 27 and Figure 28 The description can be compared with the reference. Figure 5 and Figure 6 The descriptions are basically the same. Therefore, repeated descriptions can be omitted or simplified.

[0124] In addition to the layered structure of the substrate SUB, according to the reference Figure 27 and Figure 28 The method for manufacturing the substrate SUB in the embodiment can be compared with that in the reference embodiment. Figures 7 to 11 The manufacturing methods described are basically the same. Therefore, the manufacturing process based on the reference can be omitted. Figure 27 and Figure 28 The method of the base SUB in the embodiment.

[0125] Reference Figure 27 and Figure 28 The substrate SUB can have a single-layer structure including a first substrate SUB1 and a first barrier layer BL1. A first hole HL1 can be disposed in the first substrate SUB1 having a single-layer structure.

[0126] A first barrier layer BL1 may be disposed on a first substrate SUB1. The first barrier layer BL1 may fill the first hole HL1 disposed in the first substrate SUB1.

[0127] According to embodiments of this disclosure, since the hole HL is located in the hole region HA of the substrate SUB, stress that may occur near the edge of the substrate SUB can be reduced. Therefore, during the manufacturing process of the substrate SUB, when the substrate SUB and the carrier substrate CSUB are separated from each other, curling caused by stress around the edge of the substrate SUB can be prevented. Thus, the manufacturing yield of the substrate SUB can be increased, and the manufacturing process cost can be reduced accordingly.

[0128] Figure 29This is a block diagram illustrating an electronic device according to an embodiment of the present disclosure. Figure 30 This is a perspective view illustrating an electronic device according to an embodiment of the present disclosure.

[0129] Reference Figure 29 and Figure 30 An electronic device (ED) may include a processor, a memory device, a storage device, an input / output device, a power supply, and a display device. The display device included in the electronic device (ED) may be... Figure 1 The display device DD. Additionally, the electronic device ED may include several ports capable of communicating with video cards, sound cards, memory cards, USB devices, etc., or with other systems.

[0130] A processor can perform specific calculations or tasks. In embodiments, the processor can be a microprocessor, a central processing unit, an application processor, etc. The processor can be connected to other components via address buses, control buses, data buses, etc. In embodiments, the processor can also be connected to an expansion bus such as a peripheral component interconnect (PCI) bus. The processor can output data control signals and image data to a timing controller.

[0131] Memory devices can store data required for the operation of electronic devices (ED). For example, memory devices can include non-volatile memory devices (such as erasable programmable read-only memory (EPROM) devices, electrically erasable programmable read-only memory (EEPROM) devices, flash memory devices, phase-change random access memory (PRAM) devices, resistive random access memory (RRAM) devices, nano-floating gate memory (NFGM) devices, polymer random access memory (PoRAM) devices, magnetic random access memory (MRAM) devices, ferroelectric random access memory (FRAM) devices) and / or volatile memory devices (such as dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, mobile DRAM devices), etc.

[0132] Storage devices may include solid-state drives (SSDs), hard disk drives (HDDs), CD-ROMs, etc. Input / output devices may include input devices (such as keyboards, keypads, touchpads, touchscreens, mice, etc.) and output devices (such as speakers, printers, etc.). In an embodiment, a display device may be included in the input / output devices. A power supply may provide the electrical power required for the operation of the electronic device ED. The display device may be connected to other components via a bus or other communication link.

[0133] In an embodiment, such as Figure 30 As shown, the electronic device ED can be implemented as a smartphone. The electronic device ED may include a window layer WL, a display device DD, and a housing HS.

[0134] The window layer WL can cover the display device DD. For example, the window layer WL can be set in the display area of ​​the display device DD (e.g., Figure 1 The window layer WL covers the display area DA of the display device DD. Therefore, the window layer WL can protect the display area of ​​the display image of the display device DD.

[0135] The housing HS can surround the display device DD. For example, the display device DD can be housed within the housing HS. The housing HS can cover the sides and bottom of the display device DD. Therefore, the housing HS can increase the rigidity of the display device DD and protect the display device DD from external impacts.

[0136] Functional modules, such as camera modules or sensor modules, can be housed within the housing HS. Therefore, the functional modules can be electrically connected to the display device DD and perform specific functions. However, the type or arrangement of functional modules according to embodiments of this disclosure is not necessarily limited thereto.

[0137] However, this is exemplary, and the electronic device ED according to embodiments of this disclosure is not necessarily limited thereto. For example, the electronic device ED can be implemented as a mobile phone, video phone, smart tablet, smartwatch, tablet PC, vehicle display, computer monitor, laptop computer, head-mounted display device, etc. Additionally, the electronic device ED can be a television, monitor, laptop computer, or tablet computer. Furthermore, the electronic device ED can be an automobile.

[0138] This disclosure can be applied to display devices and electronic devices including such display devices. For example, this disclosure can be applied to high-resolution smartphones, mobile phones, smart tablets, smartwatches, tablet PCs, vehicle navigation systems, televisions, computer monitors, laptops, etc.

[0139] Although this disclosure has been described with reference to embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure.

Claims

1. A display device, characterized by comprising: The display device includes: a light emitting diode; a transistor disposed under the light emitting diode and electrically connected to the light emitting diode; and a substrate disposed under the transistor and including a central area and a hole area adjacent to the central area, wherein the substrate includes a first substrate in which a first hole is disposed in the hole area.

2. The display device of claim 1, wherein, The hole area is adjacent to an edge of the substrate.

3. The display device of claim 1, wherein The substrate further includes a first barrier layer disposed on the first substrate and filling the first hole.

4. The display device of claim 3, wherein, The substrate further includes: a second substrate disposed on the first barrier layer, wherein the second substrate has a second hole disposed in the hole area; and a second barrier layer disposed on the second substrate and filling the second hole.

5. The display device of claim 4, wherein, The second hole exposes at least a portion of the first barrier layer.

6. The display device of claim 4, wherein, The first hole and the second hole do not overlap each other in a plane.

7. The display device according to claim 4, wherein Each of the first holes has a first planar area, and each of the second holes has a second planar area, wherein the first planar area and the second planar area are identical to each other.

8. The display device of claim 1, wherein, The hole area includes: first to fourth corner areas extending from corners of the central area; a first connection area connecting the first and second corner areas to each other; a second connection area connecting the second and third corner areas to each other; a third connection area connecting the third and fourth corner areas to each other; and a fourth connection area connecting the fourth and first corner areas to each other.

9. The display device according to claim 4, wherein At least one of the first holes and at least one of the second holes overlap each other in a plane.

10. An electronic device, comprising: The electronic device includes: a housing; and a display device housed in the housing, the display device displaying an image and including: a light emitting diode; a transistor disposed under the light emitting diode and electrically connected to the light emitting diode; and a substrate disposed under the transistor and including a central area and a hole area adjacent to the central area, wherein the substrate includes a first substrate in which a first hole is disposed in the hole area.

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