Circuit board, embedded memory and solid state disk

Abstract

The utility model provides a circuit board, an embedded memory and a solid state disk. The circuit board comprises a base body and multiple layers of wires arranged on the base body, the wires in different layers are coupled through via holes formed in the base body, the multiple layers of wires form a topological structure, and the topological structure comprises a first transmission path, at least two second transmission paths and multiple third transmission paths. One end of each second transmission path is coupled with the first transmission path, the other end of each second transmission path is coupled with at least two third transmission paths, and the wires of each second transmission path are located on the same layer; wherein the length of the first transmission path is greater than that of the second transmission path, and the length of the second transmission path is greater than that of the third transmission path. Therefore, the signal attenuation and the transmission delay can be improved, and the reliability, the stability and the high efficiency of signal transmission can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of storage, in particular to a circuit board, embedded memory and solid state disk. BACKGROUND

[0002] With the continuous improvement of the performance requirements of memory systems, especially in the scene of high-bandwidth and high-frequency data transmission, the traditional memory signal transmission method has been difficult to meet the needs of modern computing systems. When high-speed data transmission is performed between the storage module and the controller, in order to ensure the reliability, stability and efficiency of signal transmission, the signal trace needs to be accurately designed to avoid signal attenuation, time delay difference and other problems. CONTENT

[0003] In view of this, the present application provides a circuit board, embedded memory and solid state disk, which can improve the signal reflection interference between the traces, and the problems of poor reliability, stability and efficiency of signal transmission.

[0004] The circuit board provided by the present application comprises a base body and a plurality of layers of traces provided on the base body, the traces in different layers are coupled through vias provided by the base body, the plurality of layers of traces form a topological structure, the topological structure comprises a first transmission path, at least two second transmission paths and a plurality of third transmission paths, one end of each of the second transmission paths is coupled to the first transmission path, the other end of each of the second transmission paths is coupled to at least two of the third transmission paths, and the traces of each of the second transmission paths are located in the same layer; wherein the length of the first transmission path is greater than the length of the second transmission path, and the length of the second transmission path is greater than the length of the third transmission path.

[0005] Optionally, the traces of the third transmission path and the traces of the second transmission path are located in the same layer.

[0006] Optionally, the traces of the first transmission path and at least a part of the traces of the third transmission path are located in the same layer.

[0007] Optionally, the maximum length of the first transmission path is less than or equal to 2000 mils.

[0008] Optionally, the maximum length of the second transmission path is less than or equal to 400 mils.

[0009] Optionally, the maximum length of the third transmission path is less than or equal to 100 mils.

[0010] Optionally, the difference between the lengths of the second transmission paths is less than or equal to 50 mils.

[0011] Optionally, the length difference between the third transmission paths is less than or equal to 5 mils.

[0012] The embedded memory provided by the present application comprises the circuit board as any one of the above.

[0013] The solid state disk provided by the present application comprises the circuit board as any one of the above.

[0014] As described above, in the circuit board, the embedded memory and the solid state disk provided by the present application, the first transmission path, the second transmission path and the third transmission path of the topology structure are connected in series, and the length of the first transmission path is greater than the length of the second transmission path, and the length of the second transmission path is greater than the length of the third transmission path, which means that the main trunk is longer than each branch, and each branch is longer than the end, so as to ensure that the signal is transmitted through the longer main trunk first, reduce the signal reflection interference between each branch and between each end, and improve the signal attenuation and transmission delay, so as to improve the reliability, stability and efficiency of signal transmission. In addition, the wires of each second transmission path are located in the same layer, which can avoid the need for vias to realize the coupling when each second transmission path is arranged in different layers, and the impedance mutation caused by the vias, so as to further improve the reliability, stability and efficiency of signal transmission. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 is a coupling structure schematic diagram of a circuit board provided by an embodiment of the present application;

[0016] Figure 2 is a structure cross-section schematic diagram of a circuit board provided by an embodiment of the present application;

[0017] Figure 3 is a structure schematic diagram of an embedded memory provided by an embodiment of the present application;

[0018] Figure 4 is a structure schematic diagram of a solid state disk provided by an embodiment of the present application;

[0019] Figure 5 is an internal structure schematic diagram of a solid state disk provided by an embodiment of the present application;

[0020] Figure 6 is an internal structure schematic diagram of another solid state disk provided by an embodiment of the present application;

[0021] Figure 7 is a schematic diagram of two adjacent columns of solid state disks fixed relative to each other through a connecting piece.

[0022] Circuit board 100, base body 1, wire 2, conductive pattern layer 201, insulating layer 202, via hole 203, conductive column 204, first transmission path 31, second transmission path 32, third transmission path 33, second transmission path 321, second transmission path 322, third transmission path 331, third transmission path 332, third transmission path 333, third transmission path 334, controller 4, controlled device 5, controlled device 51, controlled device 52, controlled device 53, controlled device 54, embedded memory 5, controller 51, NAND flash chip 52, flash bare die 521, flying wire 53, solid state disk 6, controller 61, NAND flash chip 62, external terminal 101, package 102, circuit module 103, positioning hole 104, connecting piece 105, bolt 106. DETAILED DESCRIPTION

[0023] To solve the above problems of the prior art, the present application provides a circuit board with a topology structure. The first transmission path, the second transmission path and the third transmission path of the topology structure are connected in series, and the length of the first transmission path is greater than the length of the second transmission path, and the length of the second transmission path is greater than the length of the third transmission path. In this way, it is ensured that the signal is preferentially transmitted through the longer first transmission path, and the reflection interference between the signals in the shorter second transmission paths and the third transmission paths is reduced. In addition, the wires of each second transmission path are located on the same layer, avoiding impedance discontinuity caused by via holes.

[0024] Among them, the shape, number and other forms of each main body such as the first transmission path, the second transmission path and the third transmission path can be adapted according to actual needs, and the present application is not limited.

[0025] In order to make the purpose, technical scheme and advantages of the present application clearer, the technical scheme of the present application will be described in detail below combined with specific embodiments and corresponding drawings. Obviously, the following described embodiments are only part of the embodiments of the present application, not all the embodiments. In the case of no conflict, each of the following embodiments and its technical features can be combined with each other, and also belong to the technical scheme of the present application.

[0026] Figure 1 is a coupling structure schematic diagram of a circuit board provided by an embodiment of the present application, Figure 2 is a structure cross-sectional schematic diagram of a circuit board provided by an embodiment of the present application. Referring to Figure 1 and Figure 2 shown, the circuit board 100 includes a base body 1 and a plurality of wires 2.

[0027] The circuit board 100 includes but is not limited to a PCB (Printed Circuit Board) and the like. The base body 1 has a first surface 1a and a second surface 1b arranged opposite along the thickness direction of the base body 1. According to the placement orientation of the base body 1 in the actual scene, the first surface 1a can be referred to as an upper surface 11a, and the second surface 1b can be referred to as a lower surface 11b. For the circuit board 100 with double-sided printing, the sides corresponding to the first surface 1a and the second surface 1b are both provided with traces 2.

[0028] As shown in Figure 2 , on the corresponding surfaces of the base body 1, the conductive pattern layer 201 and the insulating layer 202 are alternately laminated and bonded, and finally an integrated structure is formed, which is the circuit board 100. Any conductive pattern layer 201 is a layer of traces 2 arranged as required. In the actual scene, the conductive pattern layer 201 can be manifested as the commonly called copper clad layer. Adjacent two layers of traces 2 are electrically isolated by the insulating layer 202. Different layers of traces 2 are coupled by the via hole 203 opened in the corresponding insulating layer 202 and the conductive column 204 arranged in the via hole 203, that is, the so-called interlayer coupling. Among them, the conductive column 204 can be the conductive material used to prepare the conductive pattern layer 201 flowing into the via hole 202 and solidified.

[0029] In the circuit board 100, multiple layers of traces 2 form a topology structure as shown in Figure 1 , which includes a first transmission path 31, at least two second transmission paths 32, and multiple third transmission paths 33. One end of each second transmission path 32 is coupled to the first transmission path 31, and the other end of each second transmission path 32 is coupled to at least two third transmission paths 33. The topology structure in the figure includes two second transmission paths 32 and four third transmission paths 33, a single second transmission path 32 coupled to two third transmission paths 33, which is only an exemplary display and does not constitute a limitation on the protection scope of the present application.

[0030] The first transmission path 31, the second transmission path 32 and the third transmission path 33 of the topology structure are connected in series. For Figure 1For the purpose of distinguishing and describing, the two second transmission paths 32 are respectively marked as second transmission path 321 and 322, and the four third transmission paths 33 are respectively marked as third transmission path 331, 332, 333 and 334. The first transmission path 31 is coupled with one end of the second transmission path 321, and the other end of the second transmission path 321 is divided into two sub-ends, one of which is coupled with one end of the third transmission path 331 to form a first signal transmission chain comprising the first to third transmission paths 331, and the other is coupled with one end of the third transmission path 332 to form a second signal transmission chain comprising the first to third transmission paths 332. The first transmission path 31 is also coupled with one end of the second transmission path 322, and the other end of the second transmission path 322 is also divided into two sub-ends, one of which is coupled with one end of the third transmission path 333 to form a third signal transmission chain comprising the first to third transmission paths 333, and the other is coupled with one end of the third transmission path 334 to form a fourth signal transmission chain comprising the first to third transmission paths 334.

[0031] Continuing to refer to Figure 1 In the example where the circuit board 100 is provided with a controller 4 and controlled devices 5, the first transmission path 31 can be coupled with the controller 4, and the other ends of the third transmission paths 331, 332, 333 and 334 can be respectively coupled with controlled devices 5. Specifically, the other end of the third transmission path 331 is coupled with a controlled device 51, the other end of the third transmission path 332 is coupled with a controlled device 52, the other end of the third transmission path 333 is coupled with a controlled device 53, and the other end of the third transmission path 334 is coupled with a controlled device 54. The controller 4 issues an instruction, which at least contains information of a specified controlled device 5. Taking the first signal transmission chain as an example, if the instruction specifies the controlled device 51, the circuit board 100 converts the instruction into a corresponding signal (in the form of an electrical signal), which is transmitted to the controlled device 51 via the first transmission path 31, the second transmission path 322 and the third transmission path 331. The transmission process of other signal transmission chains can be referred to.

[0032] Any transmission path of the topology is composed of a trace 2. Whether a transmission path is composed of a single trace 2 on the same layer, or is composed of multiple traces 2 coupled on the same layer, or is composed of traces 2 coupled on different layers, can be determined according to actual needs.

[0033] For example, the first transmission path 31 can be formed by one trace 2 of the circuit board 100, and the trace 2 can be a digital quantity (DQ) bus. For another example, each third transmission path 331 can be one trace 2 of the circuit board 100, and the four traces 2 forming the four third transmission paths 331 for the same type of controlled element 5 can be located on the same layer. For another example, the traces 2 forming the corresponding third transmission paths 331 for different types of controlled elements 5 can be located on different layers. For another example, the traces 2 forming the third transmission paths 33 coupled to the same second transmission path 32 are located on the same layer. For another example, the traces 2 forming the third transmission paths 33 and the traces 2 forming the second transmission paths 32 can be located on the same layer. For another example, the traces 2 forming the first transmission paths 31 and the traces 2 forming at least part of the third transmission paths 33 are located on the same layer. The traces 2 of two transmission paths located on the same layer can reduce the layer difference between the two transmission paths, thereby reducing the number of vias 202 required for the coupling of the traces 2, reducing the impedance discontinuity caused by the vias 202, improving signal attenuation and transmission delay, and improving the reliability, stability, and efficiency of signal transmission.

[0034] It should be emphasized that the one or more traces 2 of each second transmission path 32 must be located on the same layer, which can avoid the need for vias 202 to achieve coupling when the traces 2 of each second transmission path 32 are arranged on different layers, and the impedance discontinuity caused by the vias 202, thereby improving signal attenuation and transmission delay, and improving the reliability, stability, and efficiency of signal transmission.

[0035] In addition, the length of the first transmission path 31 is greater than the length of any second transmission path 22, and the length of any second transmission path 22 is greater than the length of any third transmission path 23, which means that the main trunk is longer than the branches and the branches are longer than the terminals, which can ensure that the signal passes through the longer main trunk path first, reducing signal reflection interference between the branch traces and between the terminal traces, thereby further improving signal attenuation and transmission delay, and further improving the reliability, stability, and efficiency of signal transmission.

[0036] In order to ensure stable transmission of signals in each signal transmission chain, the maximum length of each transmission path can be optionally limited. In one example, the maximum length of each transmission path can satisfy at least one of the following: the maximum length of the first transmission path 31 is less than or equal to 2000 mils; the maximum length of any second transmission path 32 is less than or equal to 400 mils; and the maximum length of any third transmission path 33 is less than or equal to 100 mils.

[0037] Further, in an example, the length difference between the second transmission paths 32 is less than or equal to 50 mil, i.e. the length difference between any two branches is small, so that the signal transmission delay between any two branches can be accurately controlled within a small range, thereby effectively improving the synchronization of signal transmission between multiple branches and avoiding data errors or loss caused by delay difference.

[0038] Similarly, optionally, the length difference between the third transmission paths 33 is less than or equal to 5 mil, by accurately controlling the delay between any two end paths, effectively improving the synchronized transmission of signals between multiple end paths and avoiding data errors or loss caused by delay difference.

[0039] The embodiments of the present application also provide an embedded memory, including but not limited to a UFS (Universal Flash Storage) or an EMMC (Embedded Multi Media Card). As shown in the figure, the embedded memory 5 includes the circuit board 100 of any of the preceding examples, so it can produce the beneficial effects of the corresponding example of the circuit board 100. Figure 3

[0040] The embedded memory 5 also includes a controller 51 and a NAND flash chip 52, and the NAND flash chip 52 is provided with a plurality of flash dies 521, of which four flash dies 521 are exemplarily shown in the figure. The controller 51 is coupled with the first transmission path 31 of the aforementioned topology, and each third transmission path 33 of the aforementioned topology is coupled with a respective pin of the NAND flash chip 52, which can be coupled with the corresponding pin through a flying wire 53, so that the controller 51 can be coupled with each flash die 521.

[0041] The embodiments of the present application also provide a solid state disk (SSD for short), which can be a SATA hard disk. As shown in the figure, the solid state disk 6 includes the circuit board 100 of any of the preceding examples, so it can produce the beneficial effects of the corresponding example of the circuit board 100. Figure 4

[0042] ​​The solid state disk 6 further comprises a controller 61 and NAND flash chips 62, two of which are exemplarily shown in the figure, each of which is arranged on the same side of the circuit board 100, and of course can be arranged on opposite sides. Each of the NAND flash chips 52 can be arranged on the circuit board 100 by SMT (Surface Mount Technology). At this time, the controller 61 is coupled with the first transmission path 31 of the aforementioned topology, and each pin of the NAND flash chip 62 is coupled with the third transmission path 33 of the aforementioned topology, so that the controller 61 can be coupled with the flash bare die of each NAND flash chip 52.

[0043] Figure 5 An internal structure diagram of a solid state disk provided by an embodiment of the present application is shown in the figure. Figure 4 and Figure 5 As shown in the figure, the circuit board 100 is a printed circuit board and is generally rectangular; one end of the circuit board 100 is provided with an external terminal 101, which is used for plugging with an external device such as a computer, so as to establish a data transmission connection between the solid state disk 6 and the external device. The external terminal 101 includes but is not limited to an M.2 interface and is provided with a plurality of pins (also referred to as "gold fingers" or "pins"), each of which can be in contact with the corresponding pin of the external device to realize electrical connection.

[0044] The circuit board 100 is provided with various electronic components, part of which is directly electrically connected with the external terminal 101 through the wiring 2 in the circuit board 100, and the other part can be indirectly electrically connected with the external terminal 101 through certain electronic components and the corresponding wiring 2 in the circuit board 100.

[0045] The electronic components include but are not limited to the aforementioned controller 61 and NAND flash chips 62, and of course also include related protection circuits and related capacitors and inductors. These electronic components can be covered on the circuit board 100 by the packaging body 102, so as to be wrapped in the insulating and sealed space formed by the packaging body 102 to form an integrally encapsulated circuit module 103. The packaging body 102 includes but is not limited to an insulating material such as resin, which can be formed by injection molding after the related electronic components are SMT mounted on the circuit board 100, or the related electronic components can be packaged by injection molding to form the packaging body 102 and the circuit module 103, and the corresponding pins of these electronic components are exposed to the packaging body 102, and then the corresponding pins are SMT mounted on the circuit board 100.

[0046] In an example, as shown in the figure, Figure 5As shown, for the electronic components such as the controller 61 which are actually chips in the actual scene, they themselves have an insulating packaging layer, so the application can be set outside the packaging body 102.

[0047] In an example, as shown, the electronic components of the solid state disk 6 can be arranged on the same surface of the circuit board 100, so as to facilitate the thin design of the entire solid state disk 6. In other examples, the electronic components of the solid state disk 6 can be arranged on two large surfaces of the circuit board 100, respectively, so as to facilitate the small design of the entire solid state disk 6. Figure 5

[0048] The solid state disk 6 as a complete device that can be produced, transported and applied alone, can also have other necessary structural elements of the device or structural elements that can be applied, which are not described here. For example, the solid state disk 6 can also be provided with a shell, which covers the internal structure as shown Figure 5 as shown, but exposes the external terminal 101, which can not only protect the various structural elements of the solid state disk 6, but also beautify the appearance of the entire product.

[0049] Figure 6 is another internal structure diagram of a solid state disk provided by an embodiment of the application. As shown in Figure 6 The circuit board 100 of the solid state disk 6 of the present example is also provided with a positioning hole 104, which is a through hole penetrating the circuit board 100 and is arranged outside the circuit module 103. The number, shape, size and position of the positioning hole 104 can be determined according to the size of the entire circuit board 100 and the actual demand adaptability, and the two positioning holes 104 in the figure are only exemplary and do not constitute a limitation on the protection scope of the application.

[0050] In an example, the positioning hole 104 can be used for assembly with the shell of the solid state disk 6, for example, the positioning hole 104 can be a threaded hole, and the assembly is achieved by screwing with a bolt.

[0051] In another example, the positioning hole 104 can be used for assembly with other solid state disks 6, so that the plurality of solid state disks 6 are fixed to form a hard disk device with a larger storage space. For example, the hard disk device includes a plurality of solid state disks 6 arranged side by side and a plurality of solid state disks 6 stacked; in combination Figure 7 ​As shown, two adjacent columns of solid state disks 6 can be relatively fixed by a connecting piece 105, which can be parallel to the column direction, a bolt 106 penetrates the connecting piece 105 and is inserted and screwed in a positioning hole 104 of a solid state disk 6, and another bolt 106 penetrates the connecting piece 105 and is inserted and screwed in a positioning hole 104 of an adjacent solid state disk 6, so as to relatively fix the two adjacent columns of solid state disks 6; for two adjacent stacked solid state disks 6, two bolts can be respectively inserted and screwed in the aligned positioning holes 104, so as to realize relative fixation.

[0052] The above only describes some embodiments of the present application, and does not limit the patent scope of the present application. For those skilled in the art, any equivalent structural transformation based on the content of the specification and the drawings is also included in the patent protection scope of the present application.

[0053] In the description of the embodiments of the present application, the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" and the like indicate the orientation or positional relationship shown in the drawings, which are only for the convenience of describing the technical solutions of the corresponding embodiments, and do not indicate or imply that the device or element must have a particular orientation, be constructed and operated in a particular orientation, and cannot be understood as a limitation of the present application.

[0054] Although the terms "first", "second", and the like are used herein to describe various information, these information should not be limited to these terms. These terms are only used to distinguish one type of information from another. In addition, the singular forms "a", "an" and "the" are intended to include plural forms. The terms "or" and "and / or" are interpreted as inclusive, or mean any one or any combination. Only when the combination of elements, functions, steps or operations is inherently mutually exclusive in some way, will there be an exception to this definition.

Claims

1. A circuit board, comprising a substrate and multilayer traces disposed on the substrate, wherein traces of different layers are coupled through vias disposed on the substrate, characterized in that: The multi-layer routing forms a topology, which includes a first transmission path, at least two second transmission paths, and multiple third transmission paths. One end of each second transmission path is coupled to the first transmission path, and the other end of each second transmission path is coupled to at least two of the third transmission paths. The routing of each second transmission path is located on the same layer. Wherein, the length of the first transmission path is greater than the length of the second transmission path, and the length of the second transmission path is greater than the length of the third transmission path.

2. The circuit board according to claim 1, characterized in that, The routing of the third transmission path is located on the same layer as the routing of the second transmission path.

3. The circuit board according to claim 1 or 2, characterized in that, The traces of the first transmission path and at least a portion of the traces of the third transmission path are located on the same layer.

4. The circuit board according to claim 1, characterized in that, The maximum length of the first transmission path is less than or equal to 2000 mils.

5. The circuit board according to claim 1, characterized in that, The maximum length of the second transmission path is less than or equal to 400 mils.

6. The circuit board according to claim 1, characterized in that, The maximum length of the third transmission path is less than or equal to 100 mils.

7. The circuit board according to claim 1 or 5, characterized in that, The length difference between the second transmission paths is less than or equal to 50 mils.

8. The circuit board according to claim 1 or 6, characterized in that, The length difference between the third transmission paths is less than or equal to 5 mils.

9. An embedded memory, characterized in that, The circuit board includes any one of claims 1 to 8.

10. A solid-state drive, characterized in that, The circuit board includes any one of claims 1 to 8.

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