In-memory computing array, in-memory computing macro circuit and in-memory computing device

Abstract

The utility model provides an in-memory computing array, an in-memory computing macro circuit and in-memory computing equipment, and the in-memory computing array comprises a memory unit group which can store data for computing; a calculation unit for performing a calculation operation; a latch capable of storing data read from the memory cell group; the global bit line switch is connected between a global bit line and the memory unit group, the global bit line can realize data interaction between the in-memory computing array and the outside, and the global bit line switch is configured to be switched off in response to a computing operation instruction, and the global bit line switch is configured to be switched off in response to the computing operation instruction. And reading data from the memory unit group to the latch for executing calculation operation, and closing the latch after the latch finishes data latching, so that the memory unit group reads / writes data through the global bit line, and the calculation operation and the read-write operation are parallel.

Description

TECHNICAL FIELD

[0001] The utility model relates to chip technology field, specifically to a kind of in-memory computing array, in-memory computing macro circuit and in-memory computing device. BACKGROUND

[0002] With the rapid development of artificial intelligence, the algorithm data and computation of neural network increase significantly. Among them, matrix-vector multiplication operation accounts for the vast majority of the computational demand of generative artificial intelligence model, and the requirement for parallel computation is greatly improved. Due to the separation of storage and computation in traditional processors, there is a large amount of data transfer between the memory and the operator, which results in the power consumption and delay overhead of data transfer being much higher than the computation overhead, causing the "memory wall" bottleneck. Emerging in-memory computing chips are considered to be an effective technical route to break through the "memory wall" bottleneck and accelerate the computation of artificial intelligence models.

[0003] However, the current in-memory computing hardware acceleration technology still faces three challenges.

[0004] First, the write bandwidth and computation throughput of the current in-memory computing hardware acceleration chip do not match, and the weight write update affects the computation efficiency, which are in conflict. In the actual hardware design and software running process, due to physical factors such as lithography limit and economic factors such as production cost, the total hardware resources that can be integrated on the chip are always limited. Therefore, the current memory-compute integration technology cannot completely deploy many large neural network models on a single chip. This means that in actual operation, the in-memory computing array can only store part of the weights of the neural network, and needs to dynamically write and update the weight data, as shown in Figure 1

[0005] The traditional in-memory computing architecture does not support read-write and computation parallelism, so the computation must be paused when updating the memory array data. This design increases the time and energy overhead, and reduces the overall efficiency of the in-memory computing accelerator. To solve this problem, pipeline technology and data prefetching technology can be introduced at the accelerator system level to reduce the delay caused by data transfer. However, when the data transfer time is much longer than the computation time, these technologies cannot effectively hide the data transfer delay, and the performance bottleneck still exists.

[0006] ​Existing solutions mainly focus on analog domain compute-in-memory technologies based on current domain, voltage domain, charge domain, and time domain. These solutions have advantages in terms of computing energy efficiency and computing density. However, the analog domain computing precision is limited by device fluctuations, circuit noise, and other factors, and the system stability risk is large, which is difficult to land. On the other hand, taking the SRAM-based compute-in-memory technology as an example, this kind of design usually couples the bit line of SRAM with the computing unit, resulting in that the compute-in-memory array can only perform computation or read-write operation at the same time. Unlike the computing function that can be implemented in parallel in two dimensions, the weight update in the memory array is still written in a one-dimensional row-by-row manner, resulting in a significant mismatch between data write bandwidth and computing throughput. Therefore, when facing large neural network models, the actual computing efficiency of traditional analog domain compute-in-memory technology is greatly reduced.

[0007] Secondly, the traditional memory layout design is different from the CMOS logic layout design. This mismatch brings additional lateral space requirements between the memory cell area and the logic area, as well as different cell heights, resulting in area waste, as shown in Figure 2 In the traditional compute-separate architecture, the design of memory cells and CMOS logic cells follows different rules and optimization goals. The design of memory cells focuses on high density and repairability to meet the needs of large-scale data storage. Taking SRAM as an example, these cells usually adopt compact design rules (Push Rule) to achieve high storage density, while allowing a certain degree of manufacturing defects, as SRAM design includes an easy-to-implement cell repair mechanism. This design usually generates SRAM arrays within a certain range by a dedicated compiler according to the needs of system architects. In contrast, the design of CMOS logic cells focuses more on reliability and integration. Since the topology of logic cells is complex and diverse, including various logic gates and flip-flops, their design must take into account a wide range of application scenarios and high uncertainty. Therefore, CMOS logic cells usually adopt more conservative design rules to ensure the universality and reliability of the design. This design rule is called Logic Rule, which allows logic cells to follow the same digital circuit design flow in different digital chip designs, i.e. plug and play.

[0008] However, the mismatch between these two design rules makes it difficult to achieve optimal power consumption, performance, and area in compute-in-memory architecture. To solve this problem, the present application proposes a collaborative optimization design method, which aims to study the design rules of memory cells and CMOS logic cells and proposes a new design method to customize the layout design so that these two cells can coexist and work collaboratively in the same architecture.

[0009] Third, in the design of the integrated digital domain memory-computing array, due to the close coupling of the digital computing logic unit and the memory involved in analog signal processing, the signal and power integrity are negatively affected, and the working speed of the two is limited, which directly affects the performance, stability and reliability of the entire system.

[0010] On the one hand, the memory processing analog signals requires to ensure the accuracy of the signals while the bit line can only be slowly charged and discharged. However, the digital computing logic unit closely coupled with the memory can generate high-frequency digital signals, which can be coupled to the effective computing performance of the memory through various parasitic effects, and even cause computing errors. Utility model content

[0011] In view of the above problems, the utility model provides a memory computing array, comprising: a memory cell group capable of storing data for computing; a computing unit for performing a computing operation; a latch capable of storing data read from the memory cell group; and a global bit line switch connected between a global bit line and the memory cell group, wherein the global bit line can realize data interaction between the memory computing array and the outside, and the global bit line switch is configured to: disconnect in response to a computing operation instruction, read data from the memory cell group to the latch for performing a computing operation, and close after the latch completes data latching, so that the memory cell group reads / writes data through the global bit line, so that the computing operation and the read / write operation are parallel.

[0012] The memory computing array provided by the application realizes the parallel of the storage mode and the computing mode through the isolation of the global bit line and the local bit line by the global bit line switch, and the latching of the data used for participating in the computation by the latch. Specifically, the local bit line is responsible for connecting a smaller range of memory cells, for example, the memory cells of a memory computing array, and the global bit line is responsible for collecting the signals of multiple local bit lines and performing global transmission. When entering the computing mode / in response to the computing operation instruction, the global bit line switch is disconnected, at this time, the global bit line is isolated from the memory cell group and the local bit line, and the data and weights required for performing the computing operation are read from the memory cell group to the latch. After the data is completed latching, the global bit line switch is closed. If read / write operation is required, since the data / weights required for performing the computing operation have been latched to the latch, the data read / write to the memory cell group in the storage mode (also called read / write mode) does not affect the execution of the computing task, thereby providing a storage and computing module that are separated from each other but closely adjacent, without causing additional delay overhead of data transfer, while realizing the high-speed parallel of read / write and computing of the memory-computing integrated architecture.

[0013] To achieve the above-mentioned utility model purposes, the embodiment provides a compute-in-memory macro circuit, which comprises: a compute-in-memory array group, which is internally integrated with a plurality of compute-in-memory arrays and an adder tree connected with a computing unit of each compute-in-memory array; a decoding and driving module, which is used for decoding input address information and generating corresponding driving signals to select a specific compute-in-memory array group to perform a local readout operation and control the computation of the compute-in-memory array group; a read-write driving circuit, which is used for controlling the data writing / reading of a memory unit group in the compute-in-memory array group; and a control signal generating module, which is connected with the decoding and driving module and the read-write driving circuit and is used for generating control signals to control the decoding and driving module and the read-write driving circuit.

[0014] Optionally, the compute-in-memory array group is configured to have 32*64 sub-arrays, each of which comprises 16*4 memory units, and each 16 memory units cooperate with a latch to form a compute-in-memory array.

[0015] Optionally, in the column direction, 32 sub-arrays and 1 adder tree form a DCIM block, and 64 DCIM blocks are used to perform a multiply-accumulate operation of 1bit input and 4bit weight of 32 input channels, and the 64 DCIM blocks constitute a DCIM array, supporting INT4 / 8 / 16 data format configuration.

[0016] Optionally, the compute-in-memory macro circuit is configured with a 4-bit-wide 64-bit mask, each bit of which controls whether the DCIM block in the corresponding column direction is enabled, and if the weight of the DCIM block does not need to be updated, the mask cancels the write enable of the corresponding DCIM block, thereby avoiding re-writing operation.

[0017] Optionally, each bit of the mask corresponds to a DCIM block, if the mask bit is 1, the corresponding DCIM block is enabled to enter the writing operation; if the mask bit is 0, the corresponding DCIM block is not enabled and skips the writing operation.

[0018] Optionally, further comprising an in-situ decoupling circuit, comprising: a differential amplifier SA, a first capacitor CP1 and a second capacitor CP2, a non-inverting input of the differential amplifier SA is configured to be connected to a positive signal bit line BLP, an inverting input of the differential amplifier SA is configured to be connected to a negative signal bit line BLN, a memory cell power domain VDDM is designed to be disposed between the positive signal bit line and the negative signal bit line, a computing unit power domain VDDLO is symmetrically disposed on both sides of the memory cell power domain VDDM, and the first capacitor CP1 and the second capacitor CP2 are respectively connected between the computing unit power domain VDDLO and the positive signal bit line BLP and the negative signal bit line BLN disposed on both sides of the memory cell power domain VDDM.

[0019] Optionally, the layout of the memory cell and the computing unit is configured to be highly matched.

[0020] Optionally, the full adders of the adder tree are staggered between the subarrays of the DCIM block.

[0021] In order to achieve the above-mentioned purposes, the present application provides an in-memory computing device configured with the in-memory computing array or the in-memory computing macro circuit described above.

[0022] In summary, the in-memory computing array and the in-memory computing macro circuit provided by the present application eliminate the data transfer delay from the memory cell to the computing unit, realize simultaneous data reading and writing and computing, avoid reducing the computing throughput due to waiting for weight update. In addition, due to the optimization of the layout design, the memory cell and the computing unit can be closely coupled in a smaller chip space, eliminating the space redundancy caused by the mismatch of the layout rules, improving the storage density and the computing power density, and significantly improving the chip performance. The present embodiment further provides an in-situ decoupling circuit, which reduces the crosstalk between analog and digital signals, suppresses power noise, avoids wiring congestion, optimizes signal and power integrity, improves the robustness of the in-memory computing array under various working conditions, and ensures stable operation of the system. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 is the architecture schematic diagram of the in-memory computing array in the prior art.

[0024] Figure 2 is the layout structure schematic diagram of the memory cell and the computing unit of the in-memory computing array in the prior art.

[0025] Figure 3 is the structure schematic diagram of the in-memory computing macro circuit and the in-memory computing array provided by the embodiment of the present application.

[0026] Figure 4is a run-time sequence diagram of the in-memory computing array provided in the embodiment of the utility model.

[0027] Figure 5 is a layout structure diagram of the memory unit and the computing unit in the in-memory computing array provided in the embodiment of the utility model.

[0028] Figure 6 is a layout structure diagram of the memory unit and the computing unit in the in-memory computing array provided in the embodiment of the utility model.

[0029] Figure 7 is a structure diagram of the in-situ decoupling circuit provided in the embodiment of the utility model. Specific implementation

[0030] The technical scheme in the embodiment of the utility model will be clearly and completely described below in combination with the drawings in the embodiment of the utility model, obviously, the described embodiment is only a part of the embodiment of the utility model, not all the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by the person skilled in the art without creative labor are within the protection scope of the utility model.

[0031] As Figure 3 shown, the embodiment provides an in-memory computing array 100, comprising: a memory unit group 110 capable of storing data for computing; a computing unit 120 for performing a computing operation inside the in-memory computing array; a latch 130 capable of storing data read from the memory unit group 110; and a global bit line switch GBLSW connected between a global bit line GBL (including a positive signal bit line GBLP and a negative signal bit line GBLN) and the memory unit group 110, wherein the global bit line GBL can realize data interaction between the in-memory computing array 100 and the outside, and the global bit line switch GBLSW is configured to: in response to a computing operation instruction, disconnect, read data from the memory unit group 110 to the latch 130 for performing the computing operation, and close after the latch 130 completes data latching, so that the memory unit group 110 reads / writes data through the global bit line GBL, so that the computing operation and the read / write operation can be parallel.

[0032] The in-memory computing array provided by the embodiment realizes parallelism of storage mode and computing mode through isolation of the global bit line and the local bit line LBL (including the positive signal bit line LBLP and the negative signal bit line LBLN) by the global bit line switch GBLSW and latching of data used for computing by the latch 130. Specifically, the local bit line LBL is responsible for connecting a small range of memory cells, for example, the memory cells of one in-memory computing array 100, while the global bit line is responsible for collecting signals of multiple local bit lines LBL and performing global transmission. When entering the computing mode / executing the computing operation instruction, the global bit line switch GBLSW is opened, at this time, the global bit line GBL is isolated from the memory cell group 110 and the local bit line, the data and weights required for the computing operation are read out from the memory cell group 110 to the latch 130, and in response to completion of data latching of the latch 130, the global bit line switch GBLSW is closed, at this time, if read and write operations are required, since the data / weights required for the computing operation have been latched to the latch 130, data read / write to the memory cell group 110 in the storage mode (also referred to as the read-write mode) does not affect the execution of the computing task, thereby providing an in-memory computing architecture in which the storage and computing modules are separated but closely adjacent, without additional delay of data transfer, and high-speed parallelism of read-write and computing is realized.

[0033] The operation timing of the in-memory computing array 100 provided by the embodiment will be described below. Figure 4

[0034] When the in-memory computing array 100 enters the computing mode, the global bit line switch GBLSW is opened, since the memory cell group 110 and the global bit line GBL are isolated, the memory cell group 110 stops / read-write operation, and the latch 130 reads out data required for the computing operation from the memory cell group 110 locally; in response to completion of local data reading, the global bit line switch GBLSW is closed, at this time, the computing unit 120 can execute the computing task and send the computing result to the adder tree for accumulation, and since the global bit line switch GBLSW is closed, the isolation of the global bit line GBL and the memory cell group 110 is released, so that the data reading / writing operation in the storage mode can be performed in parallel while the computing unit 120 executes the computing operation.

[0035] Continuing to refer to Figure 3 The in-memory computing macro circuit 200 provided by the embodiment includes: an in-memory computing array group 210, which internally integrates a plurality of in-memory computing arrays 100, and an adder tree 211 connected to the computing unit 120 of each in-memory computing array;

[0036] ​The decoding and driving module 220 is configured to decode the input address information and generate corresponding driving signals to select a specific in-memory computing array group 210 or in-memory computing array 100 to perform a local read operation and control the calculation of the in-memory computing array group 210.

[0037] The read-write driving circuit 230 is configured to control the data write / read of the memory cell group 110 in the in-memory computing array group 210; and

[0038] The control signal generation module 240 is connected to the decoding and driving module 220 and the read-write driving circuit 230, and is configured to generate control signals to control the decoding and driving module 220 and the read-write driving circuit 230.

[0039] Specifically, the in-memory computing array group 210 can be configured to have 32*64 sub-arrays, each of which includes 16*4 memory cells, and each 16 memory cells cooperate with a latch to form an in-memory computing array 100. The 4 in-memory computing arrays 100 in each sub-array collectively store the 4-bit weights of 16 matrices, which can be used to perform a multiplication operation of 1-bit input and 4-bit weight. In the column direction, 32 sub-arrays and 1 adder tree (AT) form a DCIM block, and there are a total of 64 DCIM blocks, which are used to perform a multiply-accumulate (MAC) operation of 32 input channels, 1-bit input and 4-bit weight. The 64 DCIM blocks constitute a DCIM array, which supports INT4 / 8 / 16 data format configuration. In this way, the architecture can flexibly process weights and input data of different bit widths to adapt to different precision requirements. In addition, the 64 DCIM blocks constitute a DCIM array, which significantly improves the parallel processing capability of in-memory computing and is suitable for efficient inference in neural networks.

[0040] Optionally, in the present embodiment, the read-write driving circuit 230 is configured with a 4-bit wide 64-bit mask, each bit of which controls whether the corresponding DCIM block in the column direction is enabled. When the weights of some DCIM blocks do not need to be updated, the mask cancels the write enable of these DCIM blocks, thereby avoiding re-writing operations.

[0041] Specifically, a 64-bit mask is mapped to 64 DCIM blocks in the column direction, and each bit in the mask corresponds to a DCIM block: if the mask bit is 1, the DCIM block is enabled for writing operation; if the mask bit is 0, the DCIM block is not enabled and the writing operation is skipped.

[0042] This way allows flexible selection of which DCIM blocks participate in writing in the column direction, thereby realizing flexible configuration of data writing positions.

[0043] The technical effects of the mask setting include:

[0044] Energy saving: significantly reduces unnecessary write operations, reducing overall energy consumption.

[0045] Performance improvement: avoids unnecessary writes, reduces operation time, and improves write efficiency.

[0046] Flexibility: supports selective updating of weights in different columns, facilitating adaptation to dynamically changing workloads.

[0047] In summary, the application of the in-memory computing array 100 provided by the embodiment provides an in-memory computing macro circuit 200, which, through the hierarchical design idea of DCIM blocks, subarrays, and adder trees, realizes efficient parallel computation in storage mode and computing mode, and realizes efficient operation of matrix multiplication and accumulation.

[0048] In addition, due to its support for INT4 / 8 / 16 data format configuration, flexible data format support can adjust the precision of weights and input data according to application requirements.

[0049] Finally, the write operation is optimized through the mask function: through flexible 64-bit masks, unnecessary write operations are avoided, power consumption is reduced, and performance is improved.

[0050] This design is suitable for efficient computing fields, especially in in-memory computing applications in neural network inference and training, and has significant technical advantages.

[0051] To solve the problem of mismatch between the layout of the memory unit and the computing unit in the prior art, as shown in Figure 5 The layout of the memory unit and the computing unit is set to be highly matched, so that the memory unit and the computing unit are closely adjacent, and the layout area is compressed.

[0052] Further, in the embodiment, as shown in Figure 6 Taking the SRAM-based in-memory computing technology as an example, the height of the SRAM is increased to match the computing unit LLNC, and the size of the n-type well region and the p-type substrate region is adjusted accordingly. Such design not only guarantees yield and performance, but also provides more space for the design and wiring of the computing unit and the power / ground grid in the adder tree, which is conducive to the performance optimization of the DCIM macro unit. The full adder (FA) in the adder tree (AT) is staggered between the subarrays of the DCIM block, and the well size and cell height matched with the storage unit, improving the area utilization and realizing higher integration and reliability in smaller chip space.

[0053] Optionally, in order to avoid the crosstalk of the analog signals on the signal lines such as the digital signals and the global bit line GBL of the adder tree 211 in the in-memory computing macro circuit 200 provided in this embodiment, this embodiment provides an in-situ decoupling wiring strategy. On the one hand, the digital signal lines and the analog signal lines are arranged in different metal layers to reduce their mutual interference. On the other hand, as shown in Figure 7 Figure 7 The left side shows that in the prior art, the memory cell power domain VDDM (also referred to as the memory cell power domain) is susceptible to the crosstalk noise caused by the high-frequency digital signals of the computing cell power domain VDDLO due to its sensitivity, and is prone to signal errors due to coupling noise interference. The right side shows that this embodiment provides an in-situ decoupling circuit including a differential amplifier SA, a first capacitor CP1 and a second capacitor CP2. The non-inverting input terminal of the differential amplifier SA is configured to be connected to the positive signal bit line BLP, and the inverting input terminal of the differential amplifier SA is configured to be connected to the negative signal bit line BLN. The memory cell power domain VDDM is designed to be arranged between the positive signal bit line and the negative signal bit line. The computing cell power domain is symmetrically arranged on both sides of the memory cell power domain VDDM. The first capacitor CP1 and the second capacitor CP2 are respectively connected between the computing cell power domain VDDM arranged on both sides of the memory cell power domain VDDM and the positive signal bit line BLP and the negative signal bit line BLN. In this way, the coupling noise between the analog signal lines and the digital signal lines can be eliminated by the decoupling capacitors without adding additional components through the differential structure wiring.

[0054] In summary, the in-memory computing array 100 and the in-memory computing macro circuit 200 provided in this embodiment eliminate the data transfer delay from the memory cell to the computing cell, enable simultaneous data reading and writing and computing, and avoid reducing the computing throughput due to waiting for weight update. In addition, the layout design is optimized, so that the memory cell and the computing cell can be closely coupled in a smaller chip space, eliminating the space redundancy caused by the mismatch of layout rules, improving the storage density and computing power density, and significantly improving the chip performance. This embodiment also reduces the crosstalk influence between analog and digital signals by providing an in-situ decoupling circuit, suppresses the power noise, avoids the wiring congestion problem, optimizes the signal and power integrity, improves the robustness of the memory-computing array under various working conditions, and ensures the stable operation of the system.

[0055] ​The technical scheme of the utility model has been described in connection with the drawings. However, it is easy for those skilled in the art to understand that the protection scope of the utility model is obviously not limited to the above-mentioned specific embodiments. Those skilled in the art can make equivalent changes or replacements to the related technical features without deviating from the principles of the utility model, and the technical schemes after the changes or replacements will all fall within the protection scope of the utility model.

Claims

1. An in-memory computing array, comprising: The application comprises: a memory cell group capable of storing data for calculation; a calculation unit for performing calculation operation; a latch capable of storing data read from the memory cell group; and a global bit line switch connected between a global bit line and the memory cell group, wherein the global bit line enables the in-memory computing array to interact with external data, and the global bit line switch is configured to: be opened in response to a calculation operation instruction to read data from the memory cell group to the latch for performing calculation operation, and closed after the latch completes data latching to enable the memory cell group to read / write data through the global bit line, so that calculation operation and read / write operation can be performed in parallel.

2. An in-memory computing macro circuitry applying the in-memory computing array of claim 1, wherein, The application comprises: an in-memory computing array group internally integrated with a plurality of in-memory computing arrays and a adder tree connected to the calculation unit of each in-memory computing array; a decoding and driving module for decoding input address information and generating corresponding driving signals to select a specific in-memory computing array group for local read operation and control the calculation of the in-memory computing array group; a read / write driving circuit for controlling data write / read of the memory cell group in the in-memory computing array group; and a control signal generation module connected to the decoding and driving module and the read / write driving circuit for generating control signals to control the decoding and driving module and the read / write driving circuit.

3. The in-memory computing macro circuit of claim 2, wherein, The in-memory computing array group is configured to have 32*64 sub-arrays, each including 16*4 memory cells, and each 16 memory cells cooperate with a latch to form an in-memory computing array.

4. The in-memory computing macro circuit of claim 3, wherein, In the column direction, 32 sub-arrays and 1 adder tree form a DCIM block, and 64 DCIM blocks are used to perform multiplication and accumulation operation of 1 bit input and 4 bit weight of 32 input channels, and 64 DCIM blocks constitute a DCIM array, supporting INT4 / 8 / 16 data format configuration.

5. The in-memory computing macro circuit of claim 4, wherein, The read / write driving circuit is configured with a 4-bit wide 64-bit mask, each bit of which controls whether the corresponding DCIM block in the column direction is enabled, and if the weight of the DCIM block does not need to be updated, the mask will cancel the write enable of the corresponding DCIM block, thereby avoiding re-writing operation.

6. The in-memory computing macro circuit of claim 5, wherein, Each bit of the mask corresponds to a DCIM block, if the mask bit is 1, the corresponding DCIM block is enabled to enter the write operation; if the mask bit is 0, the corresponding DCIM block is not enabled and skips the write operation.

7. The in-memory computing macro circuit of any one of claims 2-6, wherein, Also included is an in-situ decoupling circuit comprising: a differential amplifier SA, a first capacitor CP1 and a second capacitor CP2, a non-inverting input of the differential amplifier SA is configured to be connected to a positive signal bit line BLP, an inverting input of the differential amplifier SA is configured to be connected to a negative signal bit line BLN, a memory cell power domain VDDM is designed to be disposed between the positive signal bit line and the negative signal bit line, a computing cell power domain VDDLO is symmetrically disposed on both sides of the memory cell power domain VDDM, the first capacitor CP1 and the second capacitor CP2 are respectively connected between the computing cell power domain VDDLO disposed on both sides of the memory cell power domain VDDM and the positive signal bit line BLP and the negative signal bit line BLN.

8. The in-memory computing macro circuit of any one of claims 4-6, wherein, The layout of the memory cell and the computing cell is configured to be highly matched.

9. The in-memory computing macro circuit of claim 8, wherein, Full adders of the adder tree are interleaved between subarrays of the DCIM block.

10. An in-memory computing device, comprising: configured with the in-memory computing array of claim 1 or the in-memory computing macro circuit of any one of claims 2-9.

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