LDO (Low Dropout Regulator) circuit with current limiting function and chip
By introducing a limiting circuit and a power resistor into an NMOS LDO, the problem of chip damage caused by excessive output current is solved, achieving fast current limiting, simplifying the circuit structure, reducing costs, and improving system reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-25
- Publication Date
- 2026-04-14
AI Technical Summary
Existing NMOS LDOs have shortcomings in current limiting, which can cause excessive output current under overload or short circuit conditions, easily damaging internal components. Furthermore, current current limiting circuits are complex, costly, and consume a lot of power.
A limiting circuit using NMOS series circuitry combined with an external power resistor limits the current by clamping the gate-source voltage of the regulating transistor, simplifying the external circuit structure.
It can quickly limit current when the output is overloaded or short-circuited to avoid chip damage, reduce power consumption and cost, improve system reliability, and take into account small size packaging.
Smart Images
Figure CN224122935U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of power management technology, specifically, but not limited to, an LDO circuit and chip with current limiting function. Background Technology
[0002] Low dropout regulators (LDOs) are widely used in various electronic devices due to their advantages such as low cost, low power consumption, low noise, and simple peripheral circuitry. Among them, LDOs using NMOS transistors as the regulating transistor (NMOS-type LDOs) have become an important choice for high-current applications due to their low on-resistance and good transient response characteristics.
[0003] However, existing NMOS LDOs still have significant shortcomings in current limiting functionality. Currently available NMOS LDOs mainly suffer from the following problems: First, they lack integrated current limiting functionality, leading to excessive output current under overload or short-circuit conditions, which can easily damage internal components and affect system reliability; second, although they possess current limiting functionality, their implementation circuitry is relatively complex. Such solutions require additional modules such as current monitors, current mirror circuits, reference voltage sources, and voltage comparators. Figure 1 As shown, the existing solution requires reducing the detected current by a certain ratio through a current mirror, then converting it into a voltage signal through a resistor, and comparing it with a reference voltage to achieve the current limiting function. This process involves multiple circuit modules, which are redundant and consume a lot of power, increasing the chip area and manufacturing cost.
[0004] In view of this, a new structure is needed to solve at least some of the above problems. Utility Model Content
[0005] In response to at least one or more problems in the background art, this utility model proposes an LDO circuit and chip with current limiting function. The LDO circuit can quickly limit the current when the output is overloaded or short-circuited, so as to avoid chip damage, while reducing the external circuit, reducing the overall cost, and improving the system reliability.
[0006] According to one aspect of the present invention, an LDO circuit with current limiting function includes:
[0007] An amplification module has a first input terminal connected to a reference voltage signal and a second input terminal connected to a feedback voltage signal, used to generate an amplified signal based on the reference voltage signal and the feedback voltage signal;
[0008] The regulating tube has its first end coupled to the output terminal of the amplification module, and its second end serving as the output terminal of the LDO circuit.
[0009] A limiting module, with its first end coupled to the first end of the regulating tube and its second end coupled to the second end of the regulating tube, is used to clamp the voltage between the first and second ends of the regulating tube.
[0010] Optionally, the LDO circuit includes a voltage divider network, with a first terminal connected to a power supply voltage signal and a second terminal coupled to the third terminal of the regulating transistor, for reducing the voltage at the third terminal of the regulating transistor.
[0011] Optionally, the voltage divider network includes:
[0012] The power resistor has its first end connected to the power supply voltage signal and its second end coupled to the third end of the regulating tube.
[0013] Optionally, the LDO circuit includes:
[0014] The feedback module has its input terminal coupled to the second terminal of the regulating tube and its output terminal coupled to the second input terminal of the amplification module, and is used to acquire and output the feedback voltage signal.
[0015] Optionally, the feedback module includes:
[0016] The voltage divider circuit has its first end coupled to the second end of the regulating tube, and the second end is grounded.
[0017] The filter circuit has its first end coupled to the second end of the regulating transistor, and its second end coupled to the voltage divider output terminal of the voltage divider circuit and the second input terminal of the amplification module, for outputting a stable feedback voltage signal.
[0018] Optionally, the adjusting tube includes:
[0019] The NMOS transistor has its gate coupled to the output terminal of the amplification module, its source serving as the output terminal of the LDO circuit, and its drain connected to the power supply voltage.
[0020] The limiting module includes:
[0021] The first NMOS transistor has its gate and drain connected and coupled to the first end of the regulating transistor;
[0022] The second NMOS transistor has its gate and drain connected and coupled to the source of the first NMOS transistor, and its source is coupled to the second end of the regulating transistor.
[0023] Optionally, the threshold voltages of the first NMOS transistor, the second NMOS transistor, and the regulating transistor are the same.
[0024] According to another aspect of this utility model, an LDO circuit with current limiting function includes:
[0025] The NMOS regulator has its gate coupled to the operational amplifier circuit, its source as the output terminal of the LDO circuit, and its drain coupled to the power resistor.
[0026] An operational amplifier circuit has a first input terminal connected to a reference voltage signal, a second input terminal connected to a feedback voltage signal, and an output terminal coupled to the gate of an NMOS regulating transistor, used to generate an amplified signal based on the reference voltage signal and the feedback voltage signal;
[0027] A power resistor, the first end of which is connected to the power supply voltage signal, and the second end of which is coupled to the drain of the NMOS regulating transistor;
[0028] The feedback circuit has its input terminal coupled to the source of the NMOS regulating transistor and its output terminal coupled to the second input terminal of the operational amplifier circuit, and is used to generate the feedback voltage signal based on the output voltage of the LDO circuit.
[0029] A limiting circuit, the first end of which is coupled to the gate of the NMOS regulating transistor, and the second end of which is coupled to the source of the NMOS regulating transistor, is used to clamp the gate-source voltage of the NMOS regulating transistor.
[0030] Optionally, the limiting circuit includes:
[0031] The first NMOS transistor has its gate and drain connected and coupled to the gate of the NMOS regulating transistor;
[0032] The second NMOS transistor has its gate and drain connected and coupled to the source of the first NMOS transistor, and its source is coupled to the source of the NMOS regulating transistor.
[0033] Optionally, the threshold voltages of the first NMOS transistor, the second NMOS transistor, and the NMOS regulating transistor are the same.
[0034] According to another aspect of the present invention, a chip is provided, wherein the chip integrates any of the above-mentioned LDO circuits with current limiting function.
[0035] The LDO circuit and chip with current limiting function of this invention can quickly limit the current when the output is overloaded or short-circuited by setting an NMOS series limiting circuit and combining it with an external power resistor, so as to avoid chip damage, reduce external circuits, reduce overall cost, and improve system reliability. Attached Figure Description
[0036] The accompanying drawings are provided to further illustrate the present invention and, together with the description, serve to explain the embodiments of the present invention, but do not constitute a limitation thereof. In the drawings:
[0037] Figure 1 A schematic diagram of the structure of an NMOS type LDO circuit in the prior art is shown.
[0038] Figure 2 The block diagram of the LDO circuit with current limiting function of this invention is shown.
[0039] Figure 3 A schematic diagram of the LDO circuit with current limiting function of this invention is shown. Detailed Implementation
[0040] To further understand this utility model, preferred embodiments of this utility model are described below in conjunction with examples. However, it should be understood that these descriptions are only for further illustrating the features and advantages of this utility model, and not for limiting the scope of the claims of this utility model.
[0041] The description in this section pertains to only a few typical embodiments, and this utility model is not limited to the scope of the embodiments described. Combinations of different embodiments, substitution of some technical features in different embodiments, and substitution of the same or similar prior art with some technical features in the embodiments are also within the scope of the description and protection of this utility model.
[0042] The terms "coupled" or "connected" in this specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as a connection through an electrically conductive medium like a conductor, which may contain parasitic inductance or capacitance. It can also be a connection through intermediate circuits or components described in the embodiments of this specification. Indirect connections may also include connections through other active or passive devices that achieve the same or similar function, such as connections through switches, signal amplification circuits, follower circuits, or other circuits or components. "Multiple" or "more" indicates two or more.
[0043] According to one aspect of this utility model, an LDO circuit with current limiting function, such as... Figure 2 As shown, it includes an amplification module 1, an adjustment tube 2, and a limiting module 3, wherein:
[0044] The first input terminal of the amplification module 1 is connected to the reference voltage signal Vref, and the second input terminal is connected to the feedback voltage signal Vfb, which is used to generate an amplified signal based on the reference voltage signal Vref and the feedback voltage signal Vfb.
[0045] The first end of the regulating tube 2 is coupled to the output end of the amplification module 1, and the second end serves as the output end of the LDO circuit.
[0046] The first end of the limiting module 3 is coupled to the first end of the regulating tube 2, and the second end is coupled to the second end of the regulating tube 2, for clamping the voltage between the first end and the second end of the regulating tube 2.
[0047] In one specific embodiment, the adjustment transistor 2 includes an NMOS transistor Q1, such as... Figure 3 As shown, the gate of NMOS transistor Q1 is coupled to the output terminal of the amplification module 1, the source of NMOS transistor Q1 serves as the output terminal of the LDO circuit, and the drain of NMOS transistor Q1 is connected to the power supply voltage VCC. Alternatively, the regulating transistor 2 can also be an NPN transistor.
[0048] In another specific embodiment, the limiting module 3 includes a first NMOS transistor M1 and a second NMOS transistor M2, such as... Figure 3 As shown, the gate and drain of the first NMOS transistor M1 are connected and coupled to the first terminal of the adjustment transistor 2; the gate and drain of the second NMOS transistor M2 are connected and coupled to the source of the first NMOS transistor M1, and the source of the second NMOS transistor M2 is coupled to the second terminal of the adjustment transistor 2. The adjustment transistor 2 includes an NMOS transistor Q1, the gate of which is coupled to the output terminal of the amplification module 1, the source of which serves as the output terminal of the LDO circuit, and the drain of which is connected to the power supply voltage VCC. The threshold voltage of the NMOS adjustment transistor Q1 is the same as the threshold voltages of the first NMOS transistor M1 and the second NMOS transistor M2.
[0049] Specifically, the first NMOS transistor M1 and the second NMOS transistor M2 limit the maximum current of the LDO by clamping the gate-source voltage of the NMOS transistor Q1. Since the saturation current of the MOS transistor is proportional to the square of the difference between its gate-source voltage and its threshold voltage, the above structure can effectively control the current flowing through the NMOS transistor Q1, thereby significantly reducing the power consumption and heat generation of the chip.
[0050] In one embodiment, the LDO circuit further includes a voltage divider network 4, such as... Figure 2 As shown, specifically:
[0051] The first terminal of the voltage divider network 4 is connected to the power supply voltage signal Vcc, and the second terminal is coupled to the third terminal of the regulating transistor 2 to reduce the voltage at the third terminal of the regulating transistor 2. In a specific embodiment, the regulating transistor 2 includes an NMOS transistor Q1, the gate of which is coupled to the output terminal of the amplification module 1, the source of which serves as the output terminal of the LDO circuit, and the drain of which is the second terminal of the voltage divider network 4.
[0052] In another specific embodiment, the voltage divider network 4 includes a power resistor R0, such as Figure 3As shown, the regulating transistor 2 includes an NMOS transistor Q1. The first terminal of the power resistor R0 is connected to the power supply voltage signal Vcc, and the second terminal of the power resistor R0 is coupled to the drain of the NMOS transistor Q1. Specifically, the power resistor R0 bears part of the voltage drop and power consumption of the LDO circuit, reducing the power consumption burden of the regulating transistor 2. This further reduces the heat generation of the chip, balancing small chip size packaging and high reliability.
[0053] In another embodiment, the LDO circuit further includes a feedback module 5, such as Figure 2 As shown, specifically:
[0054] The input terminal of the feedback module 5 is coupled to the second terminal of the adjustment tube 2, and the output terminal is coupled to the second input terminal of the amplification module 1, for acquiring and outputting the feedback voltage signal Vfb.
[0055] In one specific implementation, the feedback module 5 includes a voltage divider circuit and a filter circuit, wherein:
[0056] The first terminal of the voltage divider circuit is coupled to the second terminal of the regulating transistor 2, and the second terminal is grounded. Specifically, the voltage divider circuit includes a first resistor R1 and a second resistor R2 connected in series, as shown below. Figure 3 As shown, the other end of the first resistor R1 is coupled to the second end of the regulating tube 2, and the other end of the second resistor R2 is grounded.
[0057] The first terminal of the filter circuit is coupled to the second terminal of the regulating transistor 2, and the second terminal is coupled to the voltage divider output terminal of the voltage divider circuit and the second input terminal of the amplification module 1, for outputting a stable feedback voltage signal Vfb. Specifically, the filter circuit includes a first capacitor C1, such as... Figure 3 As shown, one end of the first capacitor C1 is coupled to the second end of the regulating tube 2, and the other end of the first capacitor C1 is coupled to the connection point of the first resistor R1 and the second resistor R2.
[0058] According to another aspect of this utility model, an LDO circuit with current limiting function, such as... Figure 3 As shown, it includes an NMOS regulator Q1, an operational amplifier circuit, a power resistor R0, a feedback circuit, and a limiting circuit, wherein:
[0059] The gate of the NMOS transistor Q1 is coupled to the operational amplifier circuit, the source of the NMOS transistor Q1 serves as the output terminal of the LDO circuit, and the drain of the NMOS transistor Q1 is coupled to the power resistor R0.
[0060] The operational amplifier circuit has a reference voltage signal Vref connected to its first input terminal, a feedback voltage signal Vfb connected to its second input terminal, and its output terminal coupled to the gate of an NMOS regulating transistor Q1. It is used to generate an amplified signal based on the reference voltage signal Vref and the feedback voltage signal Vfb.
[0061] The first end of the power resistor R0 is connected to the power supply voltage signal VCC, and the second end of the power resistor R0 is coupled to the drain of the NMOS regulating transistor Q1.
[0062] The input terminal of the feedback circuit is coupled to the source of the NMOS regulating transistor Q1, and the output terminal of the feedback circuit is coupled to the second input terminal of the operational amplifier circuit, which is used to generate the feedback voltage signal Vfb based on the output voltage of the LDO circuit.
[0063] The first terminal of the limiting circuit is coupled to the gate of the NMOS regulating transistor Q1, and the second terminal of the limiting circuit is coupled to the source of the NMOS regulating transistor Q1, for clamping the gate-source voltage of the NMOS regulating transistor Q1.
[0064] In one specific implementation, the limiting circuit includes a first NMOS transistor M1 and a second NMOS transistor M2, such as... Figure 3 As shown, specifically:
[0065] The gate and drain of the first NMOS transistor M1 are connected and coupled to the gate of the NMOS regulating transistor Q1;
[0066] The gate and drain of the second NMOS transistor M2 are connected and coupled to the source of the first NMOS transistor M1. The source of the second NMOS transistor M2 is coupled to the source of the NMOS regulating transistor Q1.
[0067] Preferably, the first NMOS transistor M1, the second NMOS transistor M2, and the NMOS regulating transistor Q1 are of the same type, and the threshold voltages of the first NMOS transistor M1, the second NMOS transistor M2, and the NMOS regulating transistor Q1 are the same.
[0068] According to another aspect of the present invention, a chip is provided, the chip integrating an LDO circuit with current limiting function as described above.
[0069] The LDO circuit and chip with current limiting function of this invention can quickly limit the current when the output is overloaded or short-circuited by setting an NMOS series limiting circuit and combining it with an external power resistor, thereby reducing the power consumption of the chip itself, avoiding chip damage, reducing external circuits, lowering the overall cost, improving system reliability, and taking into account small size packaging.
[0070] Those skilled in the art should know that the logic controls such as "high level" and "low level", "set" and "reset", "AND gate" and "OR gate", "non-inverting input" and "inverting input" in the logic control involved in the specification or drawings can be interchanged or changed, and the same function or purpose as the above embodiment can be achieved by adjusting the subsequent logic control.
[0071] The description and application of this utility model herein are illustrative and not intended to limit the scope of the utility model to the above embodiments. The effects or advantages described in the specification may not be apparent in actual experimental examples due to uncertainties in specific conditions or parameters or other factors, and such descriptions are not intended to limit the scope of the utility model. Variations and modifications to the embodiments disclosed herein are possible, and various substitutions and equivalent components of the embodiments are well known to those skilled in the art. It should be clear to those skilled in the art that this utility model can be implemented in other forms, structures, arrangements, proportions, and with other components, materials, and parts without departing from the spirit or essential characteristics of the utility model. Other variations and modifications can be made to the embodiments disclosed herein without departing from the scope and spirit of the utility model.
Claims
1. An LDO circuit with current limiting function, characterized in that, include: An amplification module has a first input terminal connected to a reference voltage signal and a second input terminal connected to a feedback voltage signal, used to generate an amplified signal based on the reference voltage signal and the feedback voltage signal; The regulating tube has its first end coupled to the output terminal of the amplification module, and its second end serving as the output terminal of the LDO circuit. A limiting module, with its first end coupled to the first end of the regulating tube and its second end coupled to the second end of the regulating tube, is used to clamp the voltage between the first and second ends of the regulating tube.
2. The LDO circuit with current limiting function according to claim 1, characterized in that, include: A voltage divider network has a first end connected to a power supply voltage signal and a second end coupled to the third end of the regulating transistor, used to reduce the voltage at the third end of the regulating transistor.
3. The LDO circuit with current limiting function according to claim 2, characterized in that, The voltage divider network includes: The power resistor has its first end connected to the power supply voltage signal and its second end coupled to the third end of the regulating tube.
4. The LDO circuit with current limiting function according to claim 1, characterized in that, include: The feedback module has its input terminal coupled to the second terminal of the regulating tube and its output terminal coupled to the second input terminal of the amplification module, and is used to acquire and output the feedback voltage signal.
5. The LDO circuit with current limiting function according to claim 4, characterized in that, The feedback module includes: The voltage divider circuit has its first end coupled to the second end of the regulating tube, and the second end is grounded. The filter circuit has its first end coupled to the second end of the regulating transistor, and its second end coupled to the voltage divider output terminal of the voltage divider circuit and the second input terminal of the amplification module, for outputting a stable feedback voltage signal.
6. The LDO circuit with current limiting function according to claim 1, characterized in that, The adjusting tube includes: The NMOS transistor has its gate coupled to the output terminal of the amplification module, its source serving as the output terminal of the LDO circuit, and its drain connected to the power supply voltage.
7. The LDO circuit with current limiting function according to claim 1, characterized in that, The limiting module includes: The first NMOS transistor has its gate and drain connected and coupled to the first end of the regulating transistor; The second NMOS transistor has its gate and drain connected and coupled to the source of the first NMOS transistor, and its source is coupled to the second end of the regulating transistor.
8. The LDO circuit with current limiting function according to claim 7, characterized in that, The threshold voltages of the first NMOS transistor, the second NMOS transistor, and the regulating transistor are the same.
9. An LDO circuit with current limiting function, characterized in that, include: The NMOS regulator has its gate coupled to the operational amplifier circuit, its source as the output terminal of the LDO circuit, and its drain coupled to the power resistor. An operational amplifier circuit has a first input terminal connected to a reference voltage signal, a second input terminal connected to a feedback voltage signal, and an output terminal coupled to the gate of an NMOS regulating transistor, used to generate an amplified signal based on the reference voltage signal and the feedback voltage signal; A power resistor, the first end of which is connected to the power supply voltage signal, and the second end of which is coupled to the drain of the NMOS regulating transistor; The feedback circuit has its input terminal coupled to the source of the NMOS regulating transistor and its output terminal coupled to the second input terminal of the operational amplifier circuit, and is used to generate the feedback voltage signal based on the output voltage of the LDO circuit. A limiting circuit, the first end of which is coupled to the gate of the NMOS regulating transistor, and the second end of which is coupled to the source of the NMOS regulating transistor, is used to clamp the gate-source voltage of the NMOS regulating transistor.
10. The LDO circuit with current limiting function according to claim 9, characterized in that, The limiting circuit includes: The first NMOS transistor has its gate and drain connected and coupled to the gate of the NMOS regulating transistor; The second NMOS transistor has its gate and drain connected and coupled to the source of the first NMOS transistor, and its source is coupled to the source of the NMOS regulating transistor.
11. The LDO circuit with current limiting function according to claim 10, characterized in that, The threshold voltages of the first NMOS transistor, the second NMOS transistor, and the NMOS regulating transistor are the same.
12. A chip, characterized in that, The chip integrates an LDO circuit with current limiting function as described in any one of claims 1-11.