Communication analog-digital hybrid bridge

Abstract

The utility model relates to a communication analog-to-digital hybrid bridge, which comprises a radio frequency front end, an ADC / DAC conversion module, a DSP module and a protocol conversion module, the protocol conversion module is provided with a multi-protocol interface, and the multi-protocol interface is connected with the ADC / DAC conversion module through a dual-channel JESD204B interface; and the protocol conversion module is connected with the DSP module through a SerDes deserializer. According to the utility model, the bandwidth and delay bottleneck of the traditional discrete chipset is broken through, the five-mode signal synchronous processing is supported, the end-to-end delay is less than or equal to 8 microseconds, and the five-mode signal synchronous processing circuit is suitable for a high-density radio frequency front end and an industrial real-time control system.

Description

A communication analog-to-digital hybrid bridge Technical Field

[0001] This utility model relates to the field of communications, and in particular to a communication analog-to-digital hybrid bridge. Background Technology

[0002] Communication standards typically include five types: PDT, DMR, PDR, public network, and analog signals. However, walkie-talkies often do not communicate with public networks or analog signals. That is, walkie-talkies supporting PDT, DMR, and PDR communication often lack the ability to transmit or receive public network or analog signals, thus limiting their functionality. Current methods integrate communication chips for all five standards into the walkie-talkie, allowing it to transmit and receive the five communication signals. However, this approach results in problems such as large chip cluster size, limited bandwidth, interference between digital and analog signals, noise, high call latency, and low efficiency of multi-chip collaboration. Summary of the Invention

[0003] The purpose of this application is to provide a communication analog-to-digital hybrid bridge, which aims to solve the problems existing in the prior art.

[0004] This application provides a communication analog-to-digital hybrid bridge, including an RF front-end, an ADC / DAC conversion module, and a DSP module. It also includes a protocol conversion module with multiple protocol interfaces, including a PDT protocol interface, a DMR protocol interface, a PDR protocol interface, a public network signal protocol interface, and an analog signal protocol interface. These multiple protocol interfaces are connected to the ADC / DAC conversion module via a dual-channel JESD204B interface. The protocol conversion module and the DSP module are connected via a SerDes deserializer. The DSP module is configured in RapidIO mode to receive signals sent by the protocol conversion module.

[0005] The protocol conversion module uses an FPGA chip and integrates 8 GTH transceivers.

[0006] The radio frequency front end uses SDR in the range of 0.1-6GHz.

[0007] The bridge also includes a power supply system, which includes an independent LDO power supply for the ADC / DAC conversion module, using a 1.0V core voltage, 1.8V I / O, and ripple <5mV; a multi-phase Buck-Boost power supply for the protocol conversion module, with a voltage of 0.85V-1.2V; and a digitally adjustable PMU power management unit for the DSP module, which receives load status commands from the protocol conversion module via the EMIF bus.

[0008] The bridge also includes a noise reduction system, which includes an ADC / DAC conversion module and a protocol conversion module connected via an SPI bus. The ADC / DAC conversion module is equipped with a filter, and its filter coefficient is adjusted by the noise power spectral density calculated by the protocol conversion module.

[0009] The beneficial effects of this invention are as follows: By employing a dual-channel JESD204B interface connection, this invention achieves ultra-high-speed transmission of 12.5Gbps×2, effectively increasing bandwidth utilization to 98%. Based on the SerDes protocol, the adaptive link supports microsecond-level dynamic switching between RapidIO and 10G Ethernet protocols. Combined with a priority preemption scheduling algorithm, it enables hierarchical transmission of control commands and data payloads. The multi-level hybrid power supply network (LDO+Buck-Boost+PMU) adjusts power supply parameters in real time according to the DSP module load status monitored by the FPGA, achieving 40% energy efficiency optimization under ultra-low ripple of 5mV. Based on a gradient descent weighted filtering algorithm, the internal filtering coefficients of the ADC module are dynamically configured via the SPI bus, achieving a noise suppression response period ≤10μs. This invention breaks through the bandwidth and latency bottlenecks of traditional discrete chipsets, supports five-mode signal synchronous processing, and has an end-to-end latency ≤8μs, making it suitable for high-density RF front-ends and industrial real-time control systems. Attached Figure Description

[0010] Figure 1 is a schematic diagram of the electrical connection principle of this utility model. Detailed Implementation

[0011] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0012] Figure 1 shows a communication analog-to-digital hybrid bridge, comprising an RF front-end, an ADC / DAC conversion module, a protocol conversion module, and a DSP module. The protocol conversion module has multiple protocol interfaces, including a PDT protocol interface, a DMR protocol interface, a PDR protocol interface, a public network signal protocol interface, and an analog signal protocol interface. These multiple protocol interfaces are connected to the ADC / DAC conversion module via dual-channel JESD204B interfaces. Subframe interleaving technology eliminates synchronization header redundancy, and the ADC / DAC conversion module sends LVDS low-voltage differential signals to the protocol conversion module. The protocol conversion module and the DSP module are connected via a SerDes deserializer. The DSP module is configured in RapidIO mode to receive signals sent by the protocol conversion module.

[0013] The ADC / DAC conversion module uses the ADRV9009 chip, the protocol conversion module uses the FPGA chip (Zynq UltraScale+), and the DSP module uses the TI C6678 chip.

[0014] The protocol conversion module uses an FPGA chip and integrates 8 GTH transceivers (16.3Gbps / channel), supporting adaptive SRIO, PCIe, and Ethernet protocols. It automatically selects the transmission protocol based on the data stream type: 1. Control commands: low-latency mode (RapidIO short packets, CRC16 checksum); 2. Data payload: high-throughput mode (10G Ethernet jumbo frames, LDPC error correction).

[0015] While completing physical layer frame parsing, the protocol conversion module pushes channel state information (CQI) to the DSP module via RapidIO, enabling the DSP module to calculate the spectrum allocation matrix in advance (predicting time slot occupancy > 90%). JESD204B interface data is directly written to the protocol conversion module's Block RAM (BRAM), bypassing the DDR controller via the AXI-Stream protocol, reducing latency to 2μs (traditional solutions ≥ 10μs).

[0016] The radio frequency front end uses SDR in the range of 0.1-6GHz.

[0017] The bridge also includes a power supply system, comprising an independent LDO power supply for the ADC / DAC conversion module, using a 1.0V core voltage, 1.8V I / O, and ripple <5mV. It also includes a multi-phase Buck-Boost power supply for the protocol conversion module, with a voltage range of 0.85V-1.2V, supporting DVFS dynamic voltage-frequency scaling. Furthermore, it includes a digitally adjustable PMU power management unit for the DSP module, receiving load status commands from the protocol conversion module via the EMIF bus. When the protocol conversion module detects that the DSP module load is >80%, it automatically increases the DSP module voltage (1.0V → 1.1V) and locks the clock frequency.

[0018] The bridge also includes a noise reduction system, comprising an ADC / DAC conversion module and a protocol conversion module connected via an SPI bus. The ADC / DAC conversion module is equipped with a filter, and its filter coefficients are adjusted based on the noise power spectral density calculated by the protocol conversion module. The noise power spectral density is calculated based on the sampling data from the ADC / DAC conversion module, and a signal is sent via the SPI bus to the ADC / DAC conversion module to adjust the filter coefficients of its internal filter. The filter coefficient algorithm is shown in the following formula:

[0019]

[0020] Where W(f) is the frequency response (weighting coefficient) of the filter at frequency f, and its value ranges from [0,1]. S(f) is the power spectral density of the desired signal at frequency f. N(f) is the power spectral density of the noise at frequency f.

[0021] The filter adaptively adjusts the gain of each frequency component by calculating the ratio of signal power to total power (signal + noise). At frequencies where the signal is stronger than the noise (S(f) ≫ N(f), W(f) approaches 1, preserving most of the signal; at frequencies where noise is dominant (N(f) ≫ S(f), W(f) approaches 0, suppressing noise. This gradient descent weighted filtering achieves a convergence speed three times faster than the traditional LMS algorithm.

[0022] The protocol conversion module integrates decoding logic for five protocol standards, as shown in Table 1. It is used to decode PDT, DMR, PDR, public network (4G / 5G), and analog signals (FM / AM) received by the multi-protocol interface to generate analog signal output.

[0023] Table 1. Decoding Logic and Objectives of the Five-Mode Protocol

[0024] The above embodiments are not intended to limit the present invention. Unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection through an intermediate medium; or a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances. The present invention is not limited to the examples above. Changes, modifications, additions, or substitutions made by those skilled in the art within the scope of the technical solution of the present invention are also within the protection scope of the present invention. Furthermore, the technical features involved in the different embodiments of the present application described above can be combined with each other as long as they do not conflict with each other.

[0025] It will be apparent to those skilled in the art that this invention is not limited to the details of the exemplary embodiments described above, and that it can be implemented in other specific forms without departing from the spirit or essential characteristics of this invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects.

Claims

1. A communication analog-to-digital hybrid bridge, comprising a radio frequency front-end, an ADC / DAC conversion module, and a DSP module, characterized in that, It also includes a protocol conversion module with multiple protocol interfaces, including PDT protocol interface, DMR protocol interface, PDR protocol interface, public network signal protocol interface, and analog signal protocol interface. The multiple protocol interfaces are connected to the ADC / DAC conversion module through a dual-channel JESD204B interface. The protocol conversion module and the DSP module are connected through a SerDes deserializer. The DSP module is configured in RapidIO mode to receive signals sent by the protocol conversion module.

2. The communication analog-to-digital hybrid bridge according to claim 1, characterized in that, The protocol conversion module uses an FPGA chip and integrates 8 GTH transceivers.

3. The communication analog-to-digital hybrid bridge according to claim 1, characterized in that, The radio frequency front end uses an SDR of 0.1-6 GHz.

4. The communication analog-to-digital hybrid bridge according to claim 1, characterized in that, The bridge also includes a power supply system, which includes an independent LDO power supply for the ADC / DAC conversion module, using a 1.0V core voltage, 1.8V I / O, and ripple <5mV; a multi-phase Buck-Boost power supply for the protocol conversion module, with a voltage of 0.85V-1.2V; and a digitally adjustable PMU power management unit for the DSP module, which receives load status commands from the protocol conversion module via the EMIF bus.

5. The communication analog-to-digital hybrid bridge according to claim 1, characterized in that, The bridge also includes a noise reduction system, which includes an ADC / DAC conversion module and a protocol conversion module connected via an SPI bus. The ADC / DAC conversion module is equipped with a filter, and its filter coefficient is adjusted by the noise power spectral density calculated by the protocol conversion module.

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