Server mainboard and computer equipment

Abstract

The embodiment of the utility model provides a server mainboard and computer equipment, and the server mainboard comprises a plurality of processors, each processor comprises a plurality of interconnection interfaces supporting a memory interconnection interface bus and is used for interconnection among the plurality of processors; the mainboard wire comprises a plurality of connecting channels, and each connecting channel is connected with one interconnection port of the corresponding processor; the plurality of connection channels comprise forbidden connection channels forbidden based on BIOS configuration and activated connection channels not forbidden; the plurality of processors communicate with each other through the activation connection channel. According to the embodiment of the invention, multiple connection modes are provided to realize interconnection among the servers, and the interconnection requirements among multiple processors are met.

Description

Technical Field

[0001] This application relates to the field of processor technology, specifically to a server motherboard and computer equipment. Background Technology

[0002] The server motherboard is the core hardware platform of a computer system, primarily used to connect the computer system's computing units, processors, and other IP (Intellectual Property) components. In addition, the server motherboard also connects the computer system's memory, storage bus, various controllers, and expansion cards.

[0003] With the development of integrated circuit design technology, the number of IP components on server motherboards is increasing, and the corresponding number of interfaces is also growing. For example, a server motherboard can house multiple processors, which need to process large amounts of data and perform high-speed data exchange through interconnect interfaces. Therefore, achieving efficient interconnection between processors is particularly important. Against this backdrop, meeting the interconnection requirements between multiple processors in server motherboard design has become a crucial technical problem that needs to be solved by those skilled in the art. Utility Model Content

[0004] In view of this, embodiments of this application provide a server motherboard and computer device that support flexible configuration of interconnection methods between processors to meet the interconnection needs between multiple processors.

[0005] To achieve the above objectives, the embodiments of this application provide the following technical solutions.

[0006] In a first aspect, embodiments of this application provide a server motherboard, including:

[0007] Multiple processors, the processors including multiple interconnect interfaces supporting a memory interconnect interface bus for interconnecting the multiple processors;

[0008] The motherboard traces include multiple connection channels, each connection channel connecting to an interconnect interface of each of the multiple processors.

[0009] The plurality of connection channels include disabled connection channels that are disabled based on BIOS configuration, and active connection channels that are not disabled; the plurality of processors communicate with each other through the active connection channels.

[0010] Optionally, the plurality of interconnect interfaces include: a plurality of first interconnect interfaces and a plurality of second interconnect interfaces, wherein the plurality of first interconnect interfaces are arranged in a first position of the processor, and the plurality of second interconnect interfaces are arranged in a second position of the processor, with the first position and the second position opposite to each other;

[0011] The connection channel is divided into a first connection channel and a second connection channel. The first connection channel is a connection channel between the first interconnect interfaces of different processors, and the second connection channel is a connection channel between the second interconnect interfaces of different processors.

[0012] Optionally, the disabled connection channels include: all second connection channels.

[0013] Optionally, the disabled connection channel further includes:

[0014] A portion of the first connection channels, wherein the number of active connection channels in the first connection channels is greater than or equal to the number of disabled connection channels.

[0015] Optionally, the disabled connection channels include: all first connection channels.

[0016] Optionally, the disabled connection channel includes: a portion of the first connection channel; wherein the number of active connection channels in the first connection channel is less than or equal to the number of disabled connection channels.

[0017] Optionally, the disabled connection channel further includes:

[0018] A second connection channel, wherein the number of active connection channels in the first connection channel is equal to the number of disabled connection channels, and the number of active connection channels in the second connection channel is equal to the number of disabled connection channels.

[0019] Optionally, the plurality of interconnecting interfaces include: a zeroth sequence interface, a first sequence interface, a second sequence interface, a third sequence interface, a fourth sequence interface, and a fifth sequence interface;

[0020] Among them, the zeroth sequence interface, the first sequence interface, the second sequence interface, and the third sequence interface are the first interconnection interfaces located in the first position; the fourth sequence interface and the fifth sequence interface are the second interconnection interfaces located in the second position.

[0021] The first interconnecting interfaces in the first position are connected with an interval of one position between them according to their interface numbers; the second interconnecting interfaces in the second position are connected with adjacent interfaces according to their interface numbers.

[0022] Optionally, the processor further includes: a plurality of PCIe interfaces; the PCIe interfaces are connected to PCIe slots on the server motherboard;

[0023] The server motherboard also includes:

[0024] At least one memory module connected to each processor.

[0025] Secondly, embodiments of this application provide a computer device, including a server motherboard as described in any of the preceding claims.

[0026] The server motherboard provided in this application embodiment includes: multiple processors, each processor including multiple interconnect interfaces supporting a memory interconnect bus for interconnection between the multiple processors; motherboard traces including multiple connection channels, each connection channel connecting to one interconnect interface of each of the multiple processors; the multiple connection channels including disabled connection channels disabled based on BIOS (Basic Input / Output System) configuration, and active connection channels not disabled; the multiple processors communicate with each other through the active connection channels. It can be seen that when processors are interconnected through interconnect interfaces supporting a memory interconnect bus, this application embodiment uses the motherboard traces connecting the interconnect interfaces between processors as the connection channels between processors. Furthermore, the connection channels on the motherboard traces can be flexibly configured in the BIOS, thereby configuring disabled connection channels and active connection channels, enabling processors to communicate through the active connection channels. In other words, this application embodiment can flexibly configure the active and disabled connection channels between processors through the BIOS, thereby supporting flexible configuration of the interconnection methods between processors, realizing the diversification of connection methods between multiple processors, and meeting the diverse interconnection needs between multiple processors. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0028] Figure 1 A schematic diagram of an optional structure of a dual-socket server motherboard provided in an embodiment of this application;

[0029] Figure 2 A schematic diagram of the motherboard layout for a dual-socket server motherboard provided in an embodiment of this application;

[0030] Figures 3-11 This is a schematic diagram of the interconnection mode of a dual-socket server provided in an embodiment of this application. Detailed Implementation

[0031] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0032] A server motherboard is a computer motherboard specifically designed for servers. It is a core component of data centers and enterprise-level servers, integrating various key components to support high-reliability and high-performance computing requirements. A server motherboard may include multiple CPU (Central Processing Unit) sockets to support multi-processor configurations, numerous memory slots to expand memory capacity, multiple PCIe expansion slots (Peripheral Component Interconnect Express) to connect high-performance network cards, storage devices, and other I / O (Input / Output) interface cards, and integrated or remote management modules for remote monitoring and maintenance. Furthermore, a server motherboard may also include hot-swappable hard drive interfaces, redundant power supply modules, and various sensors and control chips for system monitoring and diagnostics. These components work together to ensure that the server can efficiently and stably handle large amounts of data and requests, meeting the stringent requirements of enterprise applications for computing power, data storage, network communication, and system management.

[0033] To meet the interconnection requirements of multiple processors on a server motherboard, cable connections (also known as cable links) can be used to connect the processors. However, high-speed signal quality via cable connections is unstable and cannot support various interconnection modes between processors. Therefore, this application improves the interconnection method for multiple processors by flexibly configuring the connection channels between processors through the BIOS to support various interconnection requirements and avoids cable connections. Furthermore, by avoiding cable connections to the motherboard, electromagnetic interference (EMI) and radio frequency interference (RFI) can be reduced, which helps improve the stability of high-speed signal quality.

[0034] The server motherboard in this application may specifically include: multiple processors, wherein each processor includes multiple interconnect interfaces supporting a memory interconnect interface bus for interconnection between the multiple processors;

[0035] The processor is the core component of the server motherboard, responsible for executing program instructions and processing data. Multiple processors can exist, including at least two processors, and can support interconnection between any two or more processors. Specifically, each processor has multiple interconnect interfaces, and one interconnect interface of a processor can connect to the interconnect interfaces of other processors, enabling interconnection between multiple processors.

[0036] The motherboard traces include multiple connection channels, each connection channel connecting to an interconnect interface of each of the multiple processors; the multiple connection channels include disabled connection channels that are disabled based on BIOS configuration, and active connection channels that are not disabled; the multiple processors communicate with each other through the active connection channels.

[0037] One interconnect interface of the processor is connected to a corresponding interconnect interface of other processors to form a connection channel in the motherboard wiring, and then the connection channel is used to realize the connection between processors.

[0038] In one embodiment, a disabled connection channel indicates that the connection channel is in a disabled state, that is, the connection channel does not work and cannot transmit data; while an active connection channel indicates that the connection channel is in an active state, that is, the connection channel can transmit data, thereby enabling communication between processors through the active connection channel.

[0039] As can be seen, when processors are interconnected via interconnect interfaces that support memory interconnect bus, this embodiment uses the motherboard traces connecting the interconnect interfaces between processors as the connection channels between processors. Furthermore, the connection channels on the motherboard traces can be flexibly configured in the BIOS, allowing for the configuration of disabled connection channels and active connection channels, enabling processors to communicate through active connection channels. In other words, this embodiment allows for the flexible configuration of active and disabled connection channels between processors via the BIOS, thereby supporting flexible configuration of interconnection methods between processors, diversifying the connection methods between multiple processors, and meeting the diverse interconnection needs between multiple processors.

[0040] Furthermore, since the connection channels between processors are implemented through motherboard traces, the use of cable connections is avoided. As a result, motherboard trace connections can reduce electromagnetic interference and radio frequency interference, which helps to ensure the stability of high-speed signal quality transmission between multiple processors.

[0041] In optional implementations, embodiments of this application support interconnection between dual processors (i.e., interconnection between two processors), or interconnection between more than two processors, thereby forming a dual-processor or multi-processor server motherboard. For ease of explanation, the following description uses two processors as an example to illustrate the connection method between the two processors.

[0042] refer to Figure 1 The schematic diagram of an optional structure of a dual-processor server motherboard provided in this application embodiment shows that there are two processors, namely a first processor CPU0 and a second processor CPU1. CPU0 and CPU1 are connected by multiple connection channels. One connection channel connects an interconnect interface of the first processor CPU0 and an interconnect interface of the second processor CPU1.

[0043] Each CPU also has at least one corresponding memory module, which can be DDR5 (Double Data Rate 5) memory. The DDR5 memory modules are distributed on both sides of the CPU. For example, combined with... Figure 1 As shown, DDR5 memory can be in the form of DIMM (Dual In-line Memory Module). A DIMM is a standard memory module consisting of multiple memory chips, installed in the memory slots of the motherboard. A single CPU can have 6 DIMMs on one side and 12 DIMMs on both sides. The 12 DIMMs are numbered from A to L. Correspondingly, the memory channels of each DIMM are identified as CH, and the memory channels of the 12 DIMMs are numbered from A to L. The numbering order can be set according to actual needs and is not limited here.

[0044] It should be noted that the memory channel is designed to support the operating speed and performance standard of DDR5 memory. The types of DDR5 memory modules can be divided into RDIMM (Registered DIMM), LRDIMM (Load-Reduced DIMM), NVDIMM (Non-Volatile Dual In-line Memory Module), and 3DSDIMM (3Dimensional Stacking DIMM), etc.

[0045] Multiple connection channels are channels between CPU0 and CPU1, which may include: disabled connection channels that are disabled based on BIOS configuration, and active connection channels that are not disabled; the multiple processors communicate with each other through the active connection channels.

[0046] In an optional embodiment, the BIOS can also be referred to as BIOS software. The BIOS software can record disabled connection channel information (e.g., identifiers of disabled connection channels) and activated connection channel information (e.g., identifiers of activated connection channels) among the aforementioned multiple connection channels. Therefore, in this embodiment, by running the BIOS software, the connection channels can be configured based on the disabled and activated connection channel information recorded by the BIOS software, thereby disabling the connection channels corresponding to the disabled connection channel information and activating the connection channels corresponding to the activated connection channel information. It should be noted that the BIOS software can be implemented through software compilation and is burned into the motherboard's Flash chip.

[0047] Specifically, CPU0 may include several interfaces, through which CPU0 achieves physical or electrical connections with external devices. These interfaces may include multiple interconnect interfaces, multiple communication interfaces, multiple board-side USB interfaces, multiple on-board USB Type-A connectors, a UART port (Universal Asynchronous Receiver / Transmitter port), and an SPI interface, etc.

[0048] The multiple interconnect interfaces include: interface number zero G0, interface number one G1, interface number two G2, interface number three G3, interface number four G4, and interface number five G5.

[0049] Multiple communication interfaces include: interface number 6 P6, interface number 7 P7, and interface number 8 P8;

[0050] In an optional embodiment, the sixth serial number interface P6 has a total of 16 bits, which is connected to the PCIe x16 SLOT (PCI Express x16 slot) through the 5th generation of the PCI Express (PCIe) interface standard, where x16 indicates that the slot has 16 data channels.

[0051] In an optional embodiment, the seventh serial number interface P7 has a total of 16 bits. The seventh serial number interface P7 can be connected to a SATA connector and a PCIe x16 SLOT. The SATA connector needs to occupy 4 bits of the seventh serial number interface P7, and the PCIe x16 SLOT needs to occupy the remaining 12 bits of the seventh serial number interface P7.

[0052] In an optional embodiment, the eighth serial number interface P8 has two bits. One bit can be connected to the computer's internal expansion card interface specification M.2PCIe through the fourth generation of the PCI Express (PCIe) interface standard, and the other bit can be connected to the SATA connector through a single SATA interface, or connected to the BMC through the second generation of the PCI Express (PCIe) interface standard.

[0053] The first processor CPU0's board-side USB interfaces can specifically include: a USB 3.2 interface and a USB 2.0 interface; among which, the USB 3.2 interface is a high-speed USB interface, providing faster data transfer speeds. The USB 3.2 interface is backward compatible with USB 3.1 interfaces (also known as USB 3.1 Gen 2), USB 3.0 interfaces (also known as USB 3.2 Gen 1), and USB 2.0 interfaces. Furthermore, the first processor CPU0 can have two sets of USB 3.2 interfaces and USB 2.0 interfaces on the front and two sets of USB 3.2 interfaces and USB 2.0 interfaces on the rear, and also has the following built-in USB interfaces: two sets of USB 3.2 interfaces (backward compatible with USB 2.0 interfaces), two sets of USB 2.0 Type A interfaces, and one set of USB 2.0 interfaces, with the one set of USB 2.0 interfaces used for connecting to the BMC chip.

[0054] Furthermore, the first processor CPU0 is also equipped with a UART port, which can use references or instances of three UART (Universal Asynchronous Receiver / Transmitter) interfaces.

[0055] The above describes the interface settings for the first processor, CPU0. The interface settings for the second processor, CPU1, are the same as described above and will not be repeated here.

[0056] In an optional embodiment, both the first processor CPU0 and the second processor CPU1 include an SPI interface (Serial Peripheral Interface). The SPI interface in CPU0 or CPU1 can obtain the BIOS, thereby configuring disabled connection channels and active connection channels based on the received BIOS.

[0057] In an optional embodiment, the board-side USB interface of the second processor CPU1 may specifically include a USB 3.2 interface and a USB 2.0 interface. In this embodiment, the USB 3.2 interface is backward compatible with the USB 2.0 interface.

[0058] Furthermore, the dual-socket server motherboard in this embodiment also includes a BMC (Baseboard Management Controller), which is a hardware manager integrated on the server motherboard. It is responsible for monitoring and managing the server's hardware status, performing remote management operations, and providing monitoring and control functions for the devices. The BMC communicates with other components in the system through different interfaces. For example, MAC3 (Media Access Control 3) in the BMC is used as a network interface, and communication and control with the processor are achieved through the NCSI (Network Controller Sideband Interface) interface.

[0059] Furthermore, the server motherboard also includes a CPLD (Complex Programmable Logic Device), a programmable device in digital circuitry. The CPLD's logic circuitry is controlled through the configuration of its internal programmable interconnect network, thereby implementing different digital circuit functions. By applying CPLD logic circuitry, hardware development costs can be significantly reduced.

[0060] To more clearly illustrate the structure of the dual-socket server motherboard in the embodiments of this application, the embodiments of this application also provide, as follows: Figure 2 The diagram shown is a schematic of the motherboard layout for a dual-socket server motherboard. Specifically, the dual-socket server motherboard may include: multiple processors 201, DDR5 memory 202, an 8-pin power connector 203, an M.2 connector 204, a CRPS power connector 205, an onboard USB Type-A connector 206, a BMC chip 207, a PCIe x16 physical slot 208, a SATA connector 209, a network chip 210, a VGA interface 211, an RJ45 network connector 212, and an onboard USB interface 213.

[0061] Specifically:

[0062] The 8PIN (8-pin) power connector 203 is used to provide additional power to the motherboard or specific components (such as the CPU) to ensure sufficient power supply, especially under high power demand conditions; where 8PIN means that the power connector contains 8 pins for transmitting power and signals, of course, the 8PIN form of the power connector is just an example.

[0063] The M.2 connector 204 is used to connect high-speed storage devices, such as solid-state drives (SSDs), providing fast data transfer speeds and a compact design.

[0064] The CRPS (Common Redundant Power Supply) power connector 205 is used to connect redundant power modules, providing high reliability and continuous power supply, and is commonly found in high-availability servers.

[0065] The onboard USB Type-A connector 206 is used to connect and power USB devices and can be used for debugging, external device connection, or other system integration.

[0066] The BMC chip 207 is used for remote management and monitoring of servers, enabling hardware management independent of the operating system, including power-on, power-off, and status monitoring.

[0067] PCIe X16 physical slot 208 is used to insert expansion cards, such as graphics cards and network interface cards, to provide high-speed data transmission capabilities.

[0068] The SATA (Serial Advanced Technology Attachment) connector 209 is used to connect storage devices such as HDDs (Hard Disk Drives) and SSDs, supporting data and power transfer.

[0069] The network chip 210 is used to handle the transmission and reception of network data and protocol control, and provides network connectivity for the server.

[0070] The VGA (Video Graphics Array) interface 211 is used to output video signals and connect to a monitor or other video devices.

[0071] The RJ45 (Registered Jack 45) network connector 212 is used to connect Ethernet cables to enable wired network communication.

[0072] The 213 edge-mounted USB port is a USB port installed on the edge of the motherboard, facilitating the connection of external devices such as USB flash drives, keyboards, and mice. This edge-mounted USB port supports dual network ports; it also supports internal expansion interface devices for small computers and other low-speed interface circuits, thus facilitating connection to external devices.

[0073] In this embodiment, a dual-socket server motherboard can be formed through the above layout design. The interconnection relationship among the multiple processors 201 in the structure of the dual-socket server motherboard can be further referred to... Figures 3-11 As shown.

[0074] Figures 3-11 This is a schematic diagram of the interconnection mode of a dual-socket server provided in an embodiment of this application.

[0075] Combination Figure 3 As shown, any processor's multiple interconnect interfaces include: multiple first interconnect interfaces and multiple second interconnect interfaces. The multiple first interconnect interfaces are arranged at a first position AA of the processor, and the multiple second interconnect interfaces are arranged at a second position BB of the processor. The first position AA and the second position BB are opposite to each other, and both the first position AA and the second position BB extend along the direction of the processor.

[0076] In this embodiment, the interconnect interface is a processor interface that supports a memory interconnect interface bus, allowing processors to connect via the interconnect interface and communicate with each other to access each other's memory resources; combined with Figure 3 As shown, the multiple interconnect interfaces in a single CPU include: interface number zero G0, interface number one G1, interface number two G2, interface number three G3, interface number four G4, and interface number five G5.

[0077] Among them, the zeroth sequence interface G0, the first sequence interface G1, the second sequence interface G2, and the third sequence interface G3 are the first interconnection interfaces located in the first position AA; the fourth sequence interface G4 and the fifth sequence interface G5 are the second interconnection interfaces located in the second position BB.

[0078] In an optional embodiment, the first interconnect interfaces in the first position are connected with an interval of one position between the interface numbers. The connection relationship is as follows: the zero-number interface G0 of the first processor CPU0 is connected to the second-number interface G2 of the second processor CPU1; the first-number interface G1 of the first processor is connected to the third-number interface G3 of the second processor; the second-number interface G2 of the first processor is connected to the zero-number interface G0 of the second processor; and the third-number interface G3 of the first processor is connected to the first-number interface G1 of the second processor.

[0079] Furthermore, the second interconnect interfaces in the second position are connected adjacently according to their interface numbers. The connection relationship is as follows: the fourth sequence interface G4 of the first processor is connected to the fifth sequence interface G5 of the second processor, and the fifth sequence interface G5 of the first processor is connected to the fourth sequence interface G4 of the second processor.

[0080] In the optional implementation, the zeroth sequence interface G0, the first sequence interface G1, the second sequence interface G2, the third sequence interface G3, the fourth sequence interface G4, and the fifth sequence interface G5 are all high-speed SerDes IO interfaces, which can support multiple protocols such as PCIe, CXL (Compute Express Link, high-speed interconnect technology), SATA (Serial Advanced Technology Attachment), and XGBE (eXtreme Gigabit Ethernet, high-speed network technology), or custom interconnect protocols (such as enterprise-customized interconnect protocols between processors, including but not limited to arbitrary interconnect communication protocols between CPUs and deep computing units).

[0081] Specifically: Interface G0 (number 0) supports PCIe and custom interconnect protocols; Interface G1 (number 1) supports PCIe, custom interconnect protocols, and CXL 2.0; Interface G2 (number 2) supports PCIe and custom interconnect protocols; Interface G3 (number 3) supports PCIe, custom interconnect protocols, and CXL 2.0; Interface G4 (number 4) supports PCIe, SATA, and custom interconnect protocols; and Interface G5 (number 5) supports PCIe, SATA, and custom interconnect protocols.

[0082] The connection channels formed by interconnecting interfaces in different orientations are divided into a first connection channel 100 and a second connection channel 200. The first connection channel is a connection channel between the first interconnecting interfaces of different processors, which can be considered as the interconnecting channel between the first interconnecting interface of the first processor CPU0 and the first interconnecting interface of the second processor CPU1, and communication is achieved through an active connection channel that is not disabled. The second connection channel is a connection channel between the second interconnecting interfaces of different processors, which can be considered as the interconnecting channel between the second interconnecting interface of the first processor CPU0 and the second interconnecting interface of the second processor CPU1, and communication is achieved through an active connection channel that is not disabled.

[0083] By configuring the connection status of multiple connection channels through BIOS software, various interconnection modes between processors on the server motherboard can be formed through reasonable combinations of disabled and active connection channels to meet diverse interconnection needs between processors.

[0084] In an optional implementation, a first interconnection mode may be included among multiple interconnection modes. In the first interconnection mode, disabling connection channels includes: all second connection channels. (Combined) Figure 3As shown, the first connection channel 100 formed by connecting the first interconnect interface of the first processor CPU0 and the first interconnect interface of the second processor CPU1 is an active connection channel. For ease of illustration, the active connection channel is represented by a solid line in the figure. The second connection channel 200 formed by connecting the second interconnect interface of the first processor CPU0 and the second interconnect interface of the second processor CPU1 is in a disabled state and is a disabled connection channel. For ease of illustration, the disabled connection channel is represented by a dashed line in the figure.

[0085] For example, taking the first interconnection interface as such as the zeroth serial number interface G0, the first serial number interface G1, the second serial number interface G2, and the third serial number interface G3, and the second interconnection interface as such as the fourth serial number interface G4 and the fifth serial number interface G5, the first connection channel is: the connection channel between the zeroth serial number interface G0 of the first processor and the second serial number interface G2 of the second processor, the connection channel between the first serial number interface G1 of the first processor and the third serial number interface G3 of the second processor, the connection channel between the second serial number interface G2 of the first processor and the zeroth serial number interface G0 of the second processor, and the connection channel between the third serial number interface G3 of the first processor and the first serial number interface G1 of the second processor.

[0086] The second connection channel is: the connection channel between the fourth serial number interface G4 of the first processor and the fifth serial number interface G5 of the second processor, and the connection channel between the fifth serial number interface G5 of the first processor and the fourth serial number interface G4 of the second processor.

[0087] In the first interconnection mode, the first connection channel is configured to be activated, and the second connection channel is configured to be disabled. The first processor CPU0 and the second processor CPU1 communicate through the first connection channel.

[0088] In optional implementations, a second interconnection mode can be included among multiple interconnection modes, combined with... Figure 4 As shown, in the second interconnection mode, in addition to all the second connection channels, the disabled connection channels also include some of the first connection channels, and the number of active connection channels in the first connection channels is greater than the number of disabled connection channels. Figure 4 As shown, the activated connection channel (shown by the solid line) is:

[0089] A first connection channel is formed by connecting the zeroth serial number interface G0 of the first processor and the second serial number interface G2 of the second processor; a first connection channel is formed by connecting the second serial number interface G2 of the first processor and the zeroth serial number interface G0 of the second processor; and a first connection channel is formed by connecting the third serial number interface G3 of the first processor and the first serial number interface G1 of the second processor.

[0090] The connection channel is disabled (shown by the dashed line) as follows:

[0091] A first connection channel is formed by connecting the first serial number interface G1 of the first processor and the third serial number interface G3 of the second processor; a second connection channel is formed by connecting the fourth serial number interface G4 of the first processor and the fifth serial number interface G5 of the second processor; and a second connection channel is formed by connecting the fifth serial number interface G5 of the first processor and the fourth serial number interface G4 of the second processor.

[0092] In the second interconnection mode, the first processor CPU0 and the second processor CPU1 communicate through a portion of the first connection channel.

[0093] Combination Figure 5 As shown, the third interconnect mode requires two sets of interconnect signals. These interconnect signals can be understood as signals transmitted in the active connection channels formed between the first and second processors. One active connection channel can transmit one set of interconnect signals. That is, in the third interconnect mode, two active connection channels are needed to transmit the two sets of interconnect signals. The remaining connection channels are disabled connection channels, which cannot be used to transmit interconnect signals. Specifically, in the third interconnect mode, the disabled connection channels include all the second connection channels and a portion of the first connection channels, where the number of active connection channels in the first connection channels equals the number of disabled connection channels. The third interconnect mode of the server motherboard combines... Figure 5 As shown, the first connection channel formed by connecting the zeroth serial number interface G0 of the first processor and the second serial number interface G2 of the second processor is configured as an active connection channel. The first connection channel formed by connecting the second serial number interface G2 of the first processor and the zeroth serial number interface G0 of the second processor is configured as an active connection channel. The second connection channel formed by connecting the first serial number interface G1 of the first processor and the third serial number interface G3 of the second processor, the first connection channel formed by connecting the third serial number interface G3 of the first processor and the first serial number interface G1 of the second processor, the second connection channel formed by connecting the fourth serial number interface G4 of the first processor and the fifth serial number interface G5 of the second processor, and the second connection channel formed by connecting the fifth serial number interface G5 of the first processor and the fourth serial number interface G4 of the second processor are all disabled connection channels. In the current mode, communication between the first processor CPU0 and the second processor CPU1 is realized through two sets of active connection channels.

[0094] In other optional implementations of the embodiments of this application, disabling connection channels through BIOS software configuration includes: all first connection channels.

[0095] Combination Figure 6 As shown, the fourth interconnect mode requires two sets of interconnect signals. In the fourth interconnect mode, the connection channel is disabled for all first connection channels. The server motherboard's fourth interconnect mode combines... Figure 6As shown, the first connection channel is formed by connecting the zeroth serial number interface G0 of the first processor and the second serial number interface G2 of the second processor; the first connection channel is formed by connecting the first serial number interface G1 of the first processor and the third serial number interface G3 of the second processor; the first connection channel is formed by connecting the second serial number interface G2 of the first processor and the zeroth serial number interface G0 of the second processor; the first connection channel formed by connecting the third serial number interface G3 of the first processor and the first serial number interface G1 of the second processor is configured as a disabled connection channel; the second connection channel is formed by connecting the fourth serial number interface G4 of the first processor and the fifth serial number interface G5 of the second processor, and the second connection channel formed by connecting the fifth serial number interface G5 of the first processor and the fourth serial number interface G4 of the second processor is an active connection channel. In the current mode, communication between the first processor CPU0 and the second processor CPU1 is realized through two sets of active connection channels.

[0096] In a further optional implementation of the embodiments of this application, disabling a connection channel by configuring BIOS software includes: a portion of the first connection channels; wherein the number of active connection channels in the first connection channels is less than or equal to the number of disabled connection channels.

[0097] Combination Figure 7 As shown, the fifth interconnect mode requires three sets of interconnect signals. In the fifth interconnect mode, the disabled connection channels are part of the first connection channels; wherein, the number of active connection channels in the first connection channels is less than the number of disabled connection channels. The fifth interconnect mode of the server motherboard combines... Figure 7 As shown, the configuration includes a first connection channel formed by connecting the second serial number interface G2 of the first processor and the zero serial number interface G0 of the second processor, and a second connection channel formed by connecting the fourth serial number interface G4 of the first processor and the fifth serial number interface G5 of the second processor. Both the fifth serial number interface G5 of the first processor and the fourth serial number interface G4 of the second processor are active connection channels. The configuration also includes a first connection channel formed by connecting the zero serial number interface G0 of the first processor and the second serial number interface G2 of the second processor, a first connection channel formed by connecting the first serial number interface G1 of the first processor and the third serial number interface G3 of the second processor, and a first connection channel formed by connecting the third serial number interface G3 of the first processor and the first serial number interface G1 of the second processor. All of these are disabled connection channels. In this case, the number of active connection channels in the first connection channel is less than the number of disabled connection channels. In the current mode, communication between the first processor CPU0 and the second processor CPU1 is achieved through three sets of active connection channels.

[0098] Combination Figure 8As shown, the sixth interconnect mode requires three sets of interconnect signals. In the sixth interconnect mode, the disabled connection channels are part of the first connection channels; wherein, the number of active connection channels in the first connection channels is less than the number of disabled connection channels. The sixth interconnect mode of the server motherboard combines... Figure 8 As shown, the first connection channel formed by connecting the third serial number interface G3 of the first processor and the first serial number interface G1 of the second processor, and the second connection channel formed by connecting the fourth serial number interface G4 of the first processor and the fifth serial number interface G5 of the second processor, are all active connection channels. The first connection channels formed by connecting the zero serial number interface G0 of the first processor and the second serial number interface G2 of the second processor, the first connection channels formed by connecting the first serial number interface G1 of the first processor and the third serial number interface G3 of the second processor, and the first connection channels formed by connecting the second serial number interface G2 of the first processor and the zero serial number interface G0 of the second processor are all disabled connection channels. At this time, the number of active connection channels in the first connection channel is less than the number of disabled connection channels. In the current mode, communication between the first processor CPU0 and the second processor CPU1 is realized through 3 sets of active connection channels.

[0099] Combination Figure 9 As shown, the seventh interconnect mode requires four sets of interconnect signals. In the seventh interconnect mode, the disabled connection channels are part of the first connection channels; wherein, the number of active connection channels in the first connection channels is equal to the number of disabled connection channels. The seventh interconnect mode of the server motherboard combines... Figure 9 As shown, the configuration includes a first connection channel formed by connecting the zeroth serial number interface G0 of the first processor and the second serial number interface G2 of the second processor; a second connection channel formed by connecting the second serial number interface G2 of the first processor and the zeroth serial number interface G0 of the second processor; and a second connection channel formed by connecting the fourth serial number interface G4 of the first processor and the fifth serial number interface G5 of the second processor. The second connection channel formed by connecting the fifth serial number interface G5 of the first processor and the fourth serial number interface G4 of the second processor are both active connection channels. The configuration also includes a first connection channel formed by connecting the first serial number interface G1 of the first processor and the third serial number interface G3 of the second processor; and a first connection channel formed by connecting the third serial number interface G3 of the first processor and the first serial number interface G1 of the second processor. These are both disabled connection channels. In this configuration, the number of active connection channels equals the number of disabled connection channels. In the current mode, communication between the first processor CPU0 and the second processor CPU1 is achieved through four sets of active connection channels.

[0100] Combination Figure 10As shown, the eighth interconnect mode requires four sets of interconnect signals. In the eighth interconnect mode, the disabled connection channels are part of the first connection channels; wherein, the number of activated connection channels in the first connection channels is equal to the number of disabled connection channels. The eighth interconnect mode of the server motherboard combines... Figure 10 As shown, the configuration includes a first connection channel formed by connecting the first serial number interface G1 of the first processor and the third serial number interface G3 of the second processor; a second connection channel formed by connecting the third serial number interface G3 of the first processor and the first serial number interface G1 of the second processor; and a second connection channel formed by connecting the fourth serial number interface G4 of the first processor and the fifth serial number interface G5 of the second processor. The second connection channel formed by connecting the fifth serial number interface G5 of the first processor and the fourth serial number interface G4 of the second processor are both active connection channels. The configuration also includes a first connection channel formed by connecting the zero serial number interface G0 of the first processor and the second serial number interface G2 of the second processor; and a first connection channel formed by connecting the second serial number interface G2 of the first processor and the zero serial number interface G0 of the second processor are both disabled connection channels. In this configuration, the number of active connection channels equals the number of disabled connection channels. In the current mode, communication between the first processor CPU0 and the second processor CPU1 is achieved through four sets of active connection channels.

[0101] In a further optional embodiment, the disabled connection channel includes, in addition to a portion of the first connection channel, a portion of the second connection channel, wherein the number of active connection channels in the first connection channel is equal to the number of disabled connection channels, and the number of active connection channels in the second connection channel is equal to the number of disabled connection channels.

[0102] Combination Figure 11 As shown, the ninth interconnect mode requires three sets of interconnect signals. In the ninth interconnect mode, disabling connection channels includes not only a portion of the first connection channels but also a portion of the second connection channels. Specifically, the number of active connection channels in the first connection channels equals the number of disabled connection channels, and the number of active connection channels in the second connection channels equals the number of disabled connection channels. The ninth interconnect mode of the server motherboard combines... Figure 11As shown, the first connection channel formed by connecting the zeroth serial number interface G0 of the first processor and the second serial number interface G2 of the second processor, the first connection channel formed by connecting the second serial number interface G2 of the first processor and the zeroth serial number interface G0 of the second processor, and the second connection channel formed by connecting the fourth serial number interface G4 of the first processor and the fifth serial number interface G5 of the second processor are active connection channels. The first connection channel formed by connecting the first serial number interface G1 of the first processor and the third serial number interface G3 of the second processor, the first connection channel formed by connecting the third serial number interface G3 of the first processor and the first serial number interface G1 of the second processor, and the second connection channel formed by connecting the fifth serial number interface G5 of the first processor and the fourth serial number interface G4 of the second processor are all disabled connection channels. In the current mode, communication between the first processor CPU0 and the second processor CPU1 is achieved through these three active connection channels.

[0103] Based on the various interconnection modes described above, as an optional implementation, embodiments of this application can set BIOS software corresponding to various interconnection modes. One type of BIOS software for each interconnection mode is used to record disabled connection channel information (e.g., identifiers of disabled connection channels) and activated connection channel information (e.g., identifiers of activated connection channels) for that interconnection mode. Thus, by using BIOS software corresponding to different interconnection modes, the configuration of the connection channels for the aforementioned different interconnection modes can be achieved. For example, embodiments of this application can use different versions of BIOS software burned into the motherboard's Flash chip. Each version of BIOS software corresponds to BIOS configuration information for one interconnection mode. Therefore, by running different versions of BIOS software, different interconnection modes for the connection channels can be configured according to the records of each version of BIOS software.

[0104] Furthermore, the processor also includes multiple PCIe interfaces, which are connected to the PCIe slots of the server motherboard. Regardless of the mode, the sixth interface P6 and the seventh interface P7 of the first processor CPU0 can be flexibly configured with different differential bus interface devices through the PCIe interfaces. The types of differential bus interface devices can be XGBE, SATA, PCIe, etc. The sixth interface P6 and the seventh interface P7 of the second processor CPU1 are set in a similar way to those of the first processor CPU0, and will not be described in detail here.

[0105] Specifically, the sixth interface P6 supports three protocols: PCIe, SATA, and CXL 2.0; the seventh interface P7 supports four protocols: PCIe, SATA, XGBE, and CXL 2.0.

[0106] Furthermore, the processor also includes an eighth serial interface P8, which supports both PCIe and SATA protocols. The eighth serial interface P8 can be interconnected with the MCIO 4I interface through the memory interconnect interface bus to combine multiple physical channels into a high-speed data stream, thereby improving the efficiency and real-time performance of data transmission.

[0107] In one alternative embodiment, the PCIe interface may specifically be a PCIe x16 SLOT, meaning that the PCIe interface slot has 16 lanes, supporting multi-channel bandwidth.

[0108] This application also provides a computer device, which includes a processor motherboard as described above.

[0109] The foregoing describes multiple embodiment schemes provided by the embodiments of this application. The optional methods described in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending to a variety of possible embodiment schemes. These can all be considered as the embodiment schemes disclosed and published by the embodiments of this application.

[0110] While the embodiments disclosed above are described in this application, this application is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A server motherboard, characterized in that, include: Multiple processors, the processors including multiple interconnect interfaces supporting a memory interconnect interface bus for interconnecting the multiple processors; The motherboard traces include multiple connection channels, each connection channel connecting to an interconnect interface of each of the multiple processors. The plurality of connection channels include disabled connection channels that are disabled based on BIOS configuration, and active connection channels that are not disabled; The multiple processors communicate with each other through the activated connection channel.

2. The server motherboard according to claim 1, characterized in that, The plurality of interconnect interfaces include: a plurality of first interconnect interfaces and a plurality of second interconnect interfaces, wherein the plurality of first interconnect interfaces are arranged at a first position of the processor and the plurality of second interconnect interfaces are arranged at a second position of the processor, with the first position and the second position opposite to each other; The connection channel is divided into a first connection channel and a second connection channel. The first connection channel is a connection channel between the first interconnect interfaces of different processors, and the second connection channel is a connection channel between the second interconnect interfaces of different processors.

3. The server motherboard according to claim 2, characterized in that, The disabled connection channels include: all second connection channels.

4. The server motherboard according to claim 3, characterized in that, The disabled connection channel also includes: A portion of the first connection channels, wherein the number of active connection channels in the first connection channels is greater than or equal to the number of disabled connection channels.

5. The server motherboard according to claim 2, characterized in that, The disabled connection channels include: all first connection channels.

6. The server motherboard according to claim 2, characterized in that, The disabled connection channel includes: a portion of the first connection channel; wherein the number of active connection channels in the first connection channel is less than or equal to the number of disabled connection channels.

7. The server motherboard according to claim 6, characterized in that, The disabled connection channel also includes: A second connection channel, wherein the number of active connection channels in the first connection channel is equal to the number of disabled connection channels, and the number of active connection channels in the second connection channel is equal to the number of disabled connection channels.

8. The server motherboard according to any one of claims 2-7, characterized in that, The plurality of interconnecting interfaces include: the zeroth serial number interface, the first serial number interface, the second serial number interface, the third serial number interface, the fourth serial number interface, and the fifth serial number interface; Among them, the zeroth sequence interface, the first sequence interface, the second sequence interface, and the third sequence interface are the first interconnection interfaces located in the first position; the fourth sequence interface and the fifth sequence interface are the second interconnection interfaces located in the second position. The first interconnecting interfaces in the first position are connected with an interval of one position between them according to their interface numbers; the second interconnecting interfaces in the second position are connected with adjacent interfaces according to their interface numbers.

9. The server motherboard according to claim 1, characterized in that, The processor also includes: multiple PCIe interfaces; the PCIe interfaces are connected to PCIe slots on the server motherboard; The server motherboard also includes: At least one memory module connected to each processor.

10. A computer device, characterized in that, Including the server motherboard as described in any one of claims 1-9.

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