Display device

Abstract

A display device comprises a display panel, a first test module and a second test module. The display panel comprises a plurality of pixels, a first substrate and a second substrate. The first substrate is provided with a plurality of first electrodes divided into first odd-numbered electrodes and first even-numbered electrodes. The second substrate is provided with a plurality of second electrodes which are divided into second odd-numbered electrodes and second even-numbered electrodes. The first test module is coupled to the first odd electrodes and the first even electrodes. The second test module is coupled to the second odd electrodes and the second even electrodes. One of the first test module and the second test module provides a first time sequence signal, and the other provides a second time sequence signal and a third time sequence signal, so that the pixels display a plurality of lines. When two adjacent lines present a gray scale line, the two first electrodes or the two second electrodes corresponding to the gray scale line have a short circuit defect. Therefore, the defect detection rate is improved.

Description

Technical Field

[0001] This disclosure relates to a display device, and more particularly to a cholesterol liquid crystal display device. Background Technology

[0002] Cholesteric liquid crystal displays (ChLCDs) are compatible with existing LCD manufacturing methods and, due to their multi-color capabilities, high reflectivity, energy efficiency, and eye-friendly features, have become the mainstream reflective display technology in recent years. If defective products (such as short circuits between adjacent pixels, short circuits or broken wires between adjacent electrodes) are not intercepted in the front-end processes of the display, the yield of subsequent processes will be affected, leading to waste or rework of driver chips or chip-on-film (COF) packages, resulting in increased production costs.

[0003] However, in existing inspection methods, all electrodes on the upper and lower substrates of the display panel are short-circuited together, making it impossible to effectively detect short-circuit defects in adjacent electrodes. Furthermore, existing inspection methods do not provide specific guidelines for the inspection architecture of display panels. Therefore, it is clear that there is currently a lack of an effective inspection architecture for detecting defects in the front-end processes, and relevant industry players are actively seeking solutions. Utility Model Content

[0004] Therefore, the purpose of this disclosure is to provide a display device that can be applied to the detection architecture of four-sided steps and two-sided steps, and uses a detection method of paired odd and even electrodes to detect the display panel, thereby effectively detecting defective products in the front-end process and avoiding defective products from being missed to the back-end process, which would increase production costs.

[0005] An embodiment of the structural implementation of this disclosure provides a display device comprising a display panel, a first test module, and a second test module. The display panel includes a plurality of pixels, a first substrate, and a second substrate. The first substrate has a plurality of first electrodes connected to the plurality of pixels, wherein the plurality of first electrodes are divided into a plurality of first odd-numbered electrodes and a plurality of first even-numbered electrodes. The second substrate is disposed opposite to the first substrate and has a plurality of second electrodes connected to the plurality of pixels, wherein the plurality of second electrodes are divided into a plurality of second odd-numbered electrodes and a plurality of second even-numbered electrodes. The first test module is coupled to the plurality of first odd-numbered electrodes and the plurality of first even-numbered electrodes. The second test module is coupled to the plurality of second odd-numbered electrodes and the plurality of second even-numbered electrodes. One of the first test module and the second test module provides a first timing signal, and the other of the first test module and the second test module provides a second timing signal and a third timing signal with opposite phases. The plurality of pixels display a plurality of lines based on a first timing signal, a second timing signal, and a third timing signal received from the plurality of first odd-numbered electrodes, the plurality of first even-numbered electrodes, the plurality of second odd-numbered electrodes, and the plurality of second even-numbered electrodes, wherein the first timing signal, the second timing signal, and the third timing signal are all pulse width modulation signals. When two adjacent lines of the plurality of lines form a grayscale line, two of the plurality of first electrodes or two of the plurality of second electrodes at the corresponding grayscale line position are detected as a short-circuit defect.

[0006] Other embodiments of the aforementioned implementation are as follows: When the first test module provides a first timing signal to the plurality of first electrodes, and the second test module provides a second timing signal to the plurality of second odd-numbered electrodes and a third timing signal to the plurality of second even-numbered electrodes, a pinch voltage is formed between the plurality of first electrodes and the plurality of second odd-numbered electrodes, and a zero voltage is formed between the plurality of first electrodes and the plurality of second even-numbered electrodes. The plurality of pixels display a plurality of black lines and a plurality of white lines of the plurality of lines according to the pinch voltage and the zero voltage, and the plurality of black lines and the plurality of white lines are arranged alternately. When a grayscale voltage between the pinch voltage and the zero voltage is formed between one of the plurality of first electrodes and the plurality of second odd-numbered electrodes, and a grayscale voltage is formed between one of the plurality of first electrodes and the plurality of second even-numbered electrodes, the plurality of pixels display grayscale lines according to the grayscale voltage.

[0007] Other embodiments of the aforementioned implementation are as follows: When the aforementioned first test module provides a second timing signal to the plurality of first odd-numbered electrodes and a third timing signal to the plurality of first even-numbered electrodes, and the second test module provides a first timing signal to the plurality of second electrodes, a pinch voltage is formed between the plurality of second electrodes and the plurality of first odd-numbered electrodes, and a zero voltage is formed between the plurality of second electrodes and the plurality of first even-numbered electrodes. The plurality of pixels display a plurality of black lines and a plurality of white lines of the plurality of lines according to the pinch voltage and the zero voltage, and the plurality of black lines and the plurality of white lines are arranged alternately. When a grayscale voltage between the pinch voltage and the zero voltage is formed between one of the plurality of second electrodes and the plurality of first odd-numbered electrodes, and a grayscale voltage is formed between one of the plurality of second electrodes and the plurality of first even-numbered electrodes, the plurality of pixels display grayscale lines according to the grayscale voltage.

[0008] Other embodiments of the aforementioned implementation are as follows: The aforementioned first test module is disposed on the second substrate and includes a first odd-numbered test circuit and a first even-numbered test circuit. The first odd-numbered test circuit is coupled to the plurality of first odd-numbered electrodes and is used to electrically connect the plurality of first odd-numbered electrodes to each other. The first even-numbered test circuit is coupled to the plurality of first even-numbered electrodes and is used to electrically connect the plurality of first even-numbered electrodes to each other. The second test module is disposed on the second substrate and includes a second odd-numbered test circuit and a second even-numbered test circuit. The second odd-numbered test circuit is coupled to the plurality of second odd-numbered electrodes and is used to electrically connect the plurality of second odd-numbered electrodes to each other. The second even-numbered test circuit is coupled to the plurality of second even-numbered electrodes and is used to electrically connect the plurality of second even-numbered electrodes to each other.

[0009] Other embodiments of the aforementioned implementation are as follows: The aforementioned display device further includes two first chip package structures and two second chip package structures. The two first chip package structures are disposed on a second substrate, each of the two first chip package structures including a plurality of first pins. A portion of the plurality of first pins of one of the two first chip package structures is electrically connected to a first odd-numbered test circuit, and a portion of the plurality of first pins of the other two first chip package structures is electrically connected to a first even-numbered test circuit. The two second chip package structures are disposed on the second substrate, each of the two second chip package structures including a plurality of second pins. A portion of the plurality of second pins of one of the two second chip package structures is electrically connected to a second odd-numbered test circuit, and a portion of the plurality of second pins of the other two second chip package structures is electrically connected to a second even-numbered test circuit.

[0010] Other embodiments of the aforementioned implementation are as follows: The aforementioned display device further includes two first fan-out structures and two second fan-out structures. The two first fan-out structures are disposed on a second substrate, wherein each of the two first fan-out structures includes a plurality of first fan-out wires. The plurality of first fan-out wires of one of the two first fan-out structures are electrically connected to the plurality of first pins and the plurality of first odd-numbered electrodes of that of the two first chip package structures. The plurality of first fan-out wires of the other of the two first fan-out structures are electrically connected to the plurality of first pins and the plurality of first even-numbered electrodes of the other of the two first chip package structures. The two second fan-out structures are disposed on a second substrate, wherein each of the two second fan-out structures includes a plurality of second fan-out wires. The plurality of second fan-out wires of one of the two second fan-out structures are electrically connected to the plurality of second pins and the plurality of second odd-numbered electrodes of that of the two second chip package structures. The plurality of second fan-out wires of the other of the two second fan-out structures are electrically connected to the plurality of second pins and the plurality of second even-numbered electrodes of the other of the two second chip package structures.

[0011] Other embodiments of the aforementioned implementation are as follows: The aforementioned display panel further includes two conductive adhesive structures and a frame adhesive structure. The two conductive adhesive structures are disposed between the first substrate and the second substrate, wherein one of the two conductive adhesive structures is electrically connected to one end of the plurality of first electrodes and the plurality of first fan-out wires of the two first fan-out structures, and the other of the two conductive adhesive structures is electrically connected to the other end of the plurality of first electrodes and the plurality of first fan-out wires of the other of the two first fan-out structures. The frame adhesive structure is disposed between the first substrate and the second substrate, forming a closed space with the first substrate and the second substrate, wherein the two conductive adhesive structures are located within the closed space.

[0012] Other embodiments of the aforementioned implementation are as follows: The material of the aforementioned two conductive adhesive structures is an anisotropic conductive film (ACF).

[0013] Other embodiments of the aforementioned implementation are as follows: The aforementioned display panel is a liquid crystal display panel, each of the two conductive adhesive structures includes a plurality of conductive units, and the density of the plurality of conductive units is determined by a color of the liquid crystal display panel.

[0014] Other embodiments of the aforementioned implementation are as follows: the width of each of the aforementioned two conductive adhesive structures is determined by the density of the plurality of conductive units.

[0015] Other embodiments of the aforementioned implementation are as follows: The aforementioned display panel further includes a two-conductive adhesive structure and a two-frame adhesive structure. The two-conductive adhesive structure is disposed between the first substrate and the second substrate, wherein one of the two-conductive adhesive structures is electrically connected to one end of the plurality of first electrodes and the plurality of first fan-out wires of the two first fan-out structures, and the other of the two-conductive adhesive structure is electrically connected to the other end of the plurality of first electrodes and the plurality of first fan-out wires of the other of the two first fan-out structures. The two-frame adhesive structure is disposed between the first substrate and the second substrate, and is interactively connected with the two-conductive adhesive structure to form a ring-shaped frame adhesive.

[0016] Another embodiment of the structural implementation of this disclosure provides a display device, comprising a display panel, a first test module, and a second test module. The display panel includes a plurality of pixels, a first substrate, and a second substrate. The first substrate has a plurality of first electrodes connecting the plurality of pixels, wherein the plurality of first electrodes are divided into a plurality of first odd-numbered electrodes and a plurality of first even-numbered electrodes. The second substrate is disposed opposite to the first substrate and has a plurality of second electrodes connecting the plurality of pixels, wherein the plurality of second electrodes are grouped into a first electrode group and a second electrode group, the first electrode group including a plurality of second odd-numbered electrodes and a plurality of second even-numbered electrodes, and the second electrode group including a plurality of third odd-numbered electrodes and a plurality of third even-numbered electrodes. The first test module is coupled to the plurality of first odd-numbered electrodes and the first electrode group, and provides a first timing signal to the plurality of first odd-numbered electrodes. The second test module is coupled to the plurality of first even-numbered electrodes and the second electrode group, and provides a first timing signal to the plurality of first even-numbered electrodes. The first test module provides a second timing signal and a third timing signal of opposite phase to the plurality of second odd-numbered electrodes and the plurality of second even-numbered electrodes, respectively. The second test module provides a second timing signal and a third timing signal to the plurality of third odd-numbered electrodes and the plurality of third even-numbered electrodes, respectively. The plurality of pixels display multiple lines based on the first, second, and third timing signals received from the plurality of first odd-numbered electrodes, the plurality of first even-numbered electrodes, the plurality of second odd-numbered electrodes, the plurality of second even-numbered electrodes, the plurality of third odd-numbered electrodes, and the plurality of third even-numbered electrodes, where the first, second, and third timing signals are all pulse width modulation signals. When two adjacent lines form a grayscale line, the two first electrodes or the two second electrodes at the corresponding grayscale line position are detected as a short-circuit defect.

[0017] Other embodiments of the aforementioned implementation are as follows: A pinch voltage is formed between the plurality of first electrodes, the plurality of second odd-numbered electrodes, and the plurality of third odd-numbered electrodes; a zero voltage is formed between the plurality of first electrodes, the plurality of second even-numbered electrodes, and the plurality of third even-numbered electrodes; the plurality of pixels display a plurality of black lines and a plurality of white lines of the plurality of lines respectively according to the pinch voltage and the zero voltage, and the plurality of black lines and the plurality of white lines are arranged alternately. When a grayscale voltage between the pinch voltage and the zero voltage is formed between one of the plurality of first electrodes, the plurality of second odd-numbered electrodes, and the plurality of third odd-numbered electrodes, and a grayscale voltage is formed between one of the plurality of first electrodes, the plurality of second even-numbered electrodes, and the plurality of third even-numbered electrodes, the plurality of pixels display grayscale lines according to the grayscale voltage.

[0018] Other embodiments of the aforementioned implementation are as follows: The aforementioned first test module is disposed on the second substrate and includes a first odd-numbered test circuit, a second odd-numbered test circuit, and a first even-numbered test circuit. The first odd-numbered test circuit is coupled to the plurality of first odd-numbered electrodes and is used to electrically connect the plurality of first odd-numbered electrodes to each other. The second odd-numbered test circuit is coupled to the plurality of second odd-numbered electrodes and is used to electrically connect the plurality of second odd-numbered electrodes to each other. The first even-numbered test circuit is coupled to the plurality of second even-numbered electrodes and is used to electrically connect the plurality of second even-numbered electrodes to each other. The second test module is disposed on the second substrate and includes a second even-numbered test circuit, a third even-numbered test circuit, and a third odd-numbered test circuit. The second even-numbered test circuit is coupled to the plurality of first even-numbered electrodes and is used to electrically connect the plurality of first even-numbered electrodes to each other. The third even-numbered test circuit is coupled to the plurality of third even-numbered electrodes and is used to electrically connect the plurality of third even-numbered electrodes to each other. The third odd-numbered test circuit is coupled to the plurality of third odd-numbered electrodes and is used to electrically connect the plurality of third odd-numbered electrodes to each other.

[0019] Other embodiments of the aforementioned implementation are as follows: The aforementioned display device further includes a first chip package structure, a second chip package structure, a third chip package structure, a fourth chip package structure, a fifth chip package structure, and a sixth chip package structure. The first chip package structure is disposed on a second substrate and includes a plurality of first pins, wherein a portion of the plurality of first pins is electrically connected to a first odd-numbered test circuit. The second chip package structure is disposed on the second substrate and includes a plurality of second pins, wherein a portion of the plurality of second pins is electrically connected to a second odd-numbered test circuit. The third chip package structure is disposed on the second substrate and includes a plurality of third pins, wherein a portion of the plurality of third pins is electrically connected to a first even-numbered test circuit. The fourth chip package structure is disposed on the second substrate and includes a plurality of fourth pins, wherein a portion of the plurality of fourth pins is electrically connected to a second even-numbered test circuit. The fifth chip package structure is disposed on the second substrate and includes a plurality of fifth pins, wherein a portion of the plurality of fifth pins is electrically connected to a third odd-numbered test circuit. The sixth chip package structure is disposed on the second substrate and includes a plurality of sixth pins, wherein a portion of the plurality of sixth pins is electrically connected to a third even-numbered test circuit.

[0020] Other embodiments of the aforementioned implementation are as follows: The aforementioned display device further includes a first fan-out structure and a second fan-out structure. The first fan-out structure is disposed on a second substrate and includes a plurality of first fan-out wires, wherein one end of the plurality of first fan-out wires is electrically connected to the plurality of first pins, the plurality of second pins, and the plurality of third pins, and the other end of the plurality of first fan-out wires is electrically connected to the plurality of first electrodes and the first electrode group, respectively. The second fan-out structure is disposed on a second substrate and includes a plurality of second fan-out wires, wherein one end of the plurality of second fan-out wires is electrically connected to the plurality of fourth pins, the plurality of fifth pins, and the plurality of sixth pins, respectively, and the other end of the plurality of second fan-out wires is electrically connected to the plurality of first electrodes and the second electrode group, respectively.

[0021] Other embodiments of the aforementioned implementation are as follows: The aforementioned display panel further includes a two conductive adhesive structure and a frame adhesive structure. The two conductive adhesive structures are disposed between the first substrate and the second substrate, wherein one of the two conductive adhesive structures is electrically connected to one end of the plurality of first electrodes and the plurality of first fan-out wires of the first fan-out structure, and the other of the two conductive adhesive structures is electrically connected to the other end of the plurality of first electrodes and the plurality of second fan-out wires. The frame adhesive structure is disposed between the first substrate and the second substrate, and forms a closed space with the first substrate and the second substrate, wherein the two conductive adhesive structures are located in the closed space. Attached Figure Description

[0022] Figure 1 This is a schematic diagram illustrating a display device in a first embodiment of a first embodiment according to the present disclosure;

[0023] Figure 2 It is a timing diagram illustrating the first timing signal, the second timing signal, and the third timing signal of the present disclosure;

[0024] Figure 3A It is a drawing Figure 1 A schematic diagram showing that the first substrate of the display device has no short circuit between adjacent electrodes during the detection process;

[0025] Figure 3B It is a drawing Figure 1 A schematic diagram showing that a short circuit between adjacent electrodes was detected in the first substrate of the display device during the testing process;

[0026] Figure 3C It is a drawing Figure 1 A schematic diagram showing that the second substrate of the display device has no short circuit between adjacent electrodes during the detection process;

[0027] Figure 3D It is a drawing Figure 1 A schematic diagram showing that a short circuit between adjacent electrodes was detected on the second substrate of the display device during the testing process;

[0028] Figure 4 It is a drawing Figure 1 A schematic diagram of the wiring connections for the display device;

[0029] Figure 5 It is a drawing Figure 1 Detailed structural diagrams of the first odd-numbered test circuit, the first chip package structure, and the first fan-out circuit structure;

[0030] Figure 6 It is a drawing Figure 1 Detailed structural diagrams of the first even-numbered test circuit, another first chip package structure, and another first fan-out circuit structure;

[0031] Figure 7 It is a drawing Figure 1 A cross-sectional view of the selected area in the image;

[0032] Figure 8 It is a drawing Figure 1 A cross-sectional view of another selected area in the image;

[0033] Figure 9 This is a schematic diagram illustrating a display device in a second embodiment according to a first embodiment of the present disclosure;

[0034] Figure 10 This is a schematic diagram illustrating a display device in a third embodiment of a first embodiment according to the present disclosure;

[0035] Figure 11 This is a schematic flowchart illustrating a display device testing method according to the second embodiment of this disclosure;

[0036] Figure 12 This is a schematic diagram illustrating a display device according to a third embodiment of the present disclosure; and

[0037] Figure 13 It is a drawing Figure 12 A schematic diagram of the wiring connections for the display device.

[0038] The reference numerals in the attached figures are explained as follows:

[0039] 100, 100a, 100b, 300: Display devices

[0040] 110, 110a, 110b, 310: Display panel

[0041] 111, 111a, 111b, 311: First substrate

[0042] 112, 112a, 112b, 312: Second substrate

[0043] 113: First conductive layer

[0044] 114: Conductive adhesive layer

[0045] 115: Second conductive layer

[0046] 116: Insulation layer

[0047] 117: Metal layer

[0048] 118: Liquid Crystal Layer

[0049] 120, 120b, 320: First Test Module

[0050] 121,121b,C O1 First odd-number test circuit

[0051] 1211, 1221, 1311, 1321: Laser fine-tuning blocks

[0052] 1212, 1312: Odd-line allocation blocks

[0053] 122,122b,C E1 First even-numbered test circuit

[0054] 1222, 1322: Even-line allocation blocks

[0055] 130, 130b, 330: Second Test Module

[0056] 131,131b,C O2 Second odd-number test circuit

[0057] 132,132b,C E2 Second even-number test circuit

[0058] 141,142,S P1 First chip packaging structure

[0059] 1411, 1421: First pin

[0060] 151,152,S P2 Second chip packaging structure

[0061] 161, 162: First fan-out structure

[0062] 1611, 1621, 3611: First sector outgoing wire

[0063] 1711, 1721, 3711: Second sector outgoing wires

[0064] 200: Display Device Testing Method

[0065] 340: Stepped-up packaging structure

[0066] 350: Stepped-down package structure

[0067] C E3 Third even-number test circuit

[0068] C O3 Third odd number test circuit

[0069] CP1, CP2, CP3, CP4, CP5, CP6: Conductive adhesive structure

[0070] D1, D2, D3: Direction

[0071] F, F1, F2: Frame adhesive structure

[0072] GL1, GL2: Grayscale lines

[0073] GY1: First Electrode Group

[0074] GY2: Second electrode group

[0075] IP: Intermittent Phase

[0076] L1, L3: Black lines

[0077] L2, L4: White lines

[0078] P: pixel

[0079] R1, R2: Selected area

[0080] RP: Reset Phase

[0081] SP: Selection Phase

[0082] S P3 Third chip packaging structure

[0083] S P4 Fourth chip packaging structure

[0084] S P5 Fifth chip packaging structure

[0085] S P6 Sixth chip packaging structure

[0086] S01, S02, S03, S04: Steps

[0087] S1: First timing signal

[0088] S2: Second timing signal

[0089] S3: Third timing signal

[0090] U: Conductive unit

[0091] Xc, Xr: First electrode

[0092] X1,X3,X M-1 First odd-numbered electrode

[0093] X2,X4,X M First even-numbered electrode

[0094] Yc, Yr: Second electrode

[0095] Y1,Y3,Y N-1 ,Y 11 ,Y 1K-1 Second odd-numbered electrode

[0096] Y2,Y4,Y N ,Y 12 ,Y 1K Second even-numbered electrode

[0097] Y 21 ,Y 2N-1 Third odd-numbered electrode

[0098] Y 22 ,Y 2N Third even-numbered electrode Detailed Implementation

[0099] Several embodiments of this disclosure will be described below with reference to the accompanying drawings. For clarity, many practical details will be set forth in the following description. However, it should be understood that these practical details should not be used to limit the scope of this disclosure. That is, in some embodiments of this disclosure, these practical details are not essential. Furthermore, for the sake of simplicity, some conventional structures and elements will be illustrated in the drawings in a simple schematic manner; and repeated elements may be denoted by the same reference numerals.

[0100] Furthermore, in this document, when a component (or unit or module, etc.) is "connected / linked" to another component, it can mean that the component is directly connected / linked to the other component, or it can mean that the component is indirectly connected / linked to the other component, that is, there is another component between the component and the other component. Only when it is explicitly stated that a component is "directly connected / linked" to another component does it indicate that there is no other component between the component and the other component. The terms "first," "second," and "third" are only used to describe different components and do not limit the components themselves; therefore, "first component" can also be referred to as "second component." Moreover, the combinations of components / units / circuits in this document are not combinations generally known, conventional, or existing in this art. Whether the component / unit / circuit itself is existing cannot be used to determine whether its combination relationship is easily completed by a person skilled in the art.

[0101] Please see Figure 1 This is a schematic diagram illustrating a display device in a first embodiment according to the first embodiment of the present disclosure. Figure 1 As shown, the display device 100 includes a display panel 110, a first test module 120, and a second test module 130. The display panel 110 includes a plurality of pixels P, a first substrate 111, and a second substrate 112. The first substrate 111 is provided with a plurality of first electrodes Xr connecting the plurality of pixels P, and the plurality of first electrodes Xr are divided into a plurality of first odd-numbered electrodes X1, X3, ..., X... M-1 and multiple first even-numbered electrodes X2, X4, ..., X M Where M is an even number. The second substrate 112 is disposed opposite to the first substrate 111 and is provided with a plurality of second electrodes Yc connecting the plurality of pixels P, and the plurality of second electrodes Yc are divided into a plurality of second odd-numbered electrodes Y1, Y3, ..., Y1. N-1 and multiple second even-numbered electrodes Y2, Y4, ..., Y N Where N is an even number. The first test module 120 is coupled to the plurality of first electrodes Xr (i.e., the first odd-numbered electrodes X1, X3, ..., Xr). M-1 and the first even-numbered electrodes X2, X4, ..., X M The second test module 130 is coupled to the plurality of second electrodes Yc (i.e., the second odd-numbered electrodes Y1, Y3, ..., Yc).N-1 and the second even-numbered electrodes Y2, Y4, ..., Y N ).

[0102] One of the first test module 120 and the second test module 130 provides a first timing signal. The other of the first test module 120 and the second test module 130 provides a second timing signal and a third timing signal with opposite phases. The plurality of pixels P are determined according to the first odd-numbered electrodes X1, X3, ..., X M-1 The first even-numbered electrodes X2, X4, ..., X M The second odd-numbered electrodes Y1, Y3, ..., Y N-1 and the second even-numbered electrodes Y2, Y4, ..., Y N The received first, second, and third timing signals display multiple lines. When two adjacent lines form a grayscale line, two of the multiple first electrodes Xr or two of the multiple second electrodes Yc at the corresponding grayscale line position can be detected as a short-circuit defect. Therefore, the display device 100 of this disclosure uses a detection method of paired odd and even electrodes to detect all first electrodes Xr and second electrodes Yc, thereby conveniently and quickly identifying the position of the grayscale line and finding the defective electrode. This not only provides visual clarity but also avoids the waste or rework of driver chips or chip-on-film (COF) packages caused by defective products from the front-end process being passed to the back-end process, thus reducing production costs.

[0103] In detail, Figure 1 A partial transparent top view of the display device 100 is shown, and this partial transparent top view refers to the view from the opposite direction of a direction D1. Figure 1 The diagram further illustrates a direction D2 and a direction D3, where direction D2 is, for example, the horizontal direction of the display device 100, and direction D3 is, for example, the vertical direction of the display device 100. Directions D1, D2, and D3 are perpendicular to each other. The display panel 110 may be a liquid crystal display panel, such as a cholesteric liquid crystal display panel. The first substrate 111 may be the upper substrate of the cholesteric liquid crystal display panel, and the second substrate 112 may be the lower substrate of the cholesteric liquid crystal display panel. The plurality of first electrodes Xr extend in direction D2 and are spaced apart from each other along direction D3 on the first substrate 111, wherein the first electrodes Xr may be scan lines. The plurality of second electrodes Yc extend in direction D3 and are spaced apart from each other along direction D2 on the second substrate 112, wherein the second electrodes Yc may be data lines. The plurality of intersection areas of the plurality of first electrodes Xr and the plurality of second electrodes Yc form the plurality of pixels P, and the plurality of pixels P are arranged in an array.

[0104] For ease of explanation, only the first odd-numbered electrodes X1 and X3 will be listed below to represent all first odd-numbered electrodes X1, X3, ..., Xr. M-1 And only the first even-numbered electrodes X2 and X4 are listed to represent all first even-numbered electrodes X2, X4, ..., X M Similarly, for the second electrode Yc, only the second odd-numbered electrodes Y1 and Y3 are listed below to represent all second odd-numbered electrodes Y1, Y3, ..., Yc. N-1 And only the second even-numbered electrodes Y2 and Y4 are listed to represent all second even-numbered electrodes Y2, Y4, ..., Y N .

[0105] In some embodiments, the second substrate 112 expands outward from the positions of the plurality of pixels P to form a four-sided step, such as an upper step, a lower step, a left step, and a right step. A first test module 120 is disposed on the second substrate 112 and may include a first odd-numbered test circuit 121 and a first even-numbered test circuit 122. The first odd-numbered test circuit 121 and the first even-numbered test circuit 122 are located on the left and right steps of the second substrate 112, respectively. The first odd-numbered test circuit 121 is coupled to first odd-numbered electrodes X1 and X3 and is used to electrically connect the first odd-numbered electrodes X1 and X3 to each other. The first even-numbered test circuit 122 is coupled to first even-numbered electrodes X2 and X4 and is used to electrically connect the first even-numbered electrodes X2 and X4 to each other. A second test module 130 is disposed on the second substrate 112 and may include a second odd-numbered test circuit 131 and a second even-numbered test circuit 132. The second odd-numbered test circuit 131 and the second even-numbered test circuit 132 are located on the upper and lower steps of the second substrate 112, respectively. The second odd-numbered test circuit 131 is coupled to the second odd-numbered electrodes Y1 and Y3, and is used to electrically connect the second odd-numbered electrodes Y1 and Y3 to each other. The second even-numbered test circuit 132 is coupled to the second even-numbered electrodes Y2 and Y4, and is used to electrically connect the second even-numbered electrodes Y2 and Y4 to each other.

[0106] Please continue reading. Figure 2 , Figure 3A , Figure 3B , Figure 3C and Figure 3D ,in Figure 2 It is a timing diagram illustrating the first timing signal, the second timing signal, and the third timing signal of the present disclosure; Figure 3A It is a drawing Figure 1 A schematic diagram showing that the first substrate of the display device has no short circuit between adjacent electrodes during the detection process; Figure 3B It is a drawing Figure 1 A schematic diagram showing that a short circuit between adjacent electrodes was detected in the first substrate of the display device during the testing process; Figure 3C It is a drawing Figure 1A schematic diagram showing that the second substrate of the display device has no short circuit between adjacent electrodes during the testing process; and Figure 3D It is a drawing Figure 1 A schematic diagram showing that a short circuit between adjacent electrodes was detected on the second substrate of the display device during the testing process.

[0107] like Figure 2 As shown, the first timing signal S1, the second timing signal S2, and the third timing signal S3 are all pulse-width modulation (PWM) signals with the same duty cycle and pulse amplitude. The first timing signal S1 and the third timing signal S3 can be signals with the same phase, and the first timing signal S1 and the second timing signal S2 can be signals with opposite phases, i.e., the second timing signal S2 and the third timing signal S3 are inverses of each other. When the first test module 120 provides the first timing signal S1 to the plurality of first electrodes Xr, and the second test module 130 provides the second timing signal S2 to the second odd-numbered electrodes Y1 and Y3 and provides the third timing signal S3 to the second even-numbered electrodes Y2 and Y4, a pinch voltage is formed between the plurality of first electrodes Xr and the second odd-numbered electrodes Y1 and Y3, and a zero voltage is formed between the plurality of first electrodes Xr and the second even-numbered electrodes Y2 and Y4.

[0108] Furthermore, to detect whether there is a short-circuit defect in the electrodes of the upper substrate (i.e., the first electrode Xr disposed on the first substrate 111), a first timing signal S1 can be provided to the first odd-numbered electrodes X1, X3 and the first even-numbered electrodes X2, X4 through the first odd-numbered test circuit 121 and the first even-numbered test circuit 122, respectively. Then, a second timing signal S2 can be provided to the second odd-numbered electrodes Y1, Y3 through the second odd-numbered test circuit 131, and a third timing signal S3 can be provided to the second even-numbered electrodes Y2, Y4 through the second even-numbered test circuit 132. Therefore, the aforementioned pinch voltage is the voltage difference between the first timing signal S1 and the second timing signal S2, and it can be, for example, ±20V. The aforementioned zero voltage is the voltage difference between the first timing signal S1 and the third timing signal S3, and it can be, for example, 0V.

[0109] In some embodiments, such as Figure 3A As shown, when there is no short circuit between adjacent electrodes on the first substrate 111, the plurality of pixels P respectively display a plurality of lines based on the pinch voltage and zero voltage. The plurality of lines extend in direction D2 and may include a plurality of black lines L1 and a plurality of white lines L2, and the black lines L1 and white lines L2 are arranged alternately along direction D3. In some embodiments, such as Figure 3BAs shown, when a grayscale voltage between the pinch voltage and zero voltage is formed between the plurality of first electrodes Xr and one of the second odd-numbered electrodes Y1, Y3, and a grayscale voltage is formed between the plurality of first electrodes Xr and one of the second even-numbered electrodes Y2, Y4, the plurality of pixels P display a grayscale line GL1 based on the grayscale voltage. For example, in the case of a short circuit between adjacent electrodes on the first substrate 111, two of the plurality of first electrodes Xr (i.e., a certain first odd-numbered electrode and an adjacent first even-numbered electrode) are short-circuited to each other. These two first electrodes Xr respectively form a grayscale voltage with a voltage range between 0 and 20V or -20 and 0V between the second odd-numbered electrodes Y1, Y3 and the second even-numbered electrodes Y2, Y4, causing the pixel P connected to these two first electrodes Xr to display a grayscale line GL1 based on the grayscale voltage. In this way, the two first electrodes Xr corresponding to the position of the grayscale line GL1 can be detected as short-circuit defects. The principle of the detection method of paired odd and even electrodes of this disclosure will be explained in detail below.

[0110] The display panel 110 can utilize PWM mode as the driving method for the display screen. Figure 2 In the PWM mode, a single pixel period may include a reset phase RP, an intermittent phase IP, and a selection phase SP. After passing through the reset phase RP, intermittent phase IP, and selection phase SP, the display panel 110 can determine whether the stable state of the cholesteric liquid crystal in pixel P is a focal conic state or a planar state. Assuming that all first electrodes Xr on the first substrate 111 are subject to a first timing signal S1, and the second odd-numbered electrodes Y1, Y3, and second even-numbered electrodes Y2, Y4 on the second substrate 112 are subject to a second timing signal S2 and a third timing signal S3, respectively. After passing through the reset phase RP and intermittent phase IP, the cholesteric liquid crystal in pixel P transitions to a homeotropic state. Then, after passing through the selection phase SP, the cholesteric liquid crystal in pixel P determines its current state based on a voltage difference (ΔV) between the electrodes of the upper and lower substrates. When the voltage difference is high (ΔV = V...), the cholesteric liquid crystal... H When the voltage difference is 0 (ΔV = 0), the cholesteric liquid crystal is in a focal conic state, and pixel P displays a black image; when the voltage difference is 0 (ΔV = 0), the cholesteric liquid crystal is in a planar state, and pixel P displays a white image. If a high voltage (ΔV = V) is applied between the upper and lower substrates... H When one electrode of a pixel P and its adjacent electrode with a voltage of 0 (ΔV = 0) are short-circuited, the pixel P connecting these two electrodes is based on a voltage range of 0 to V. H The voltage difference between them is displayed as a gray line (grayscale line GL1). By following this weak line (ΔV≠0), the location of the short circuit can be found, thus achieving the purpose of detecting defects.

[0111] On the other hand, when the first test module 120 provides a second timing signal S2 to the first odd-numbered electrodes X1 and X3 and provides a third timing signal S3 to the first even-numbered electrodes X2 and X4, and the second test module 130 provides a first timing signal S1 to the plurality of second electrodes Yc, a pinch voltage is formed between the plurality of second electrodes Yc and the first odd-numbered electrodes X1 and X3, and a zero voltage is formed between the plurality of second electrodes Yc and the first even-numbered electrodes X2 and X4.

[0112] Furthermore, if it is desired to detect whether there is a short circuit defect in the electrodes of the lower substrate (i.e., the second electrode Yc disposed on the second substrate 112), the first odd-number test circuit 121 can provide a second timing signal S2 to the first odd-number electrodes X1 and X3, the first even-number test circuit 122 can provide a third timing signal S3 to the first even-number electrodes X2 and X4, and the second odd-number test circuit 131 and the second even-number test circuit 132 can respectively provide a first timing signal S1 to the second odd-number electrodes Y1 and Y3 and the second even-number electrodes Y2 and Y4.

[0113] In some embodiments, such as Figure 3C As shown, when there is no short circuit between adjacent electrodes on the second substrate 112, the plurality of pixels P display a plurality of lines based on the difference voltage and zero voltage, respectively. These plurality of lines extend in direction D3 and may include a plurality of black lines L3 and a plurality of white lines L4, with the black lines L3 and white lines L4 arranged alternately along direction D2. In some embodiments, such as... Figure 3D As shown, when a grayscale voltage between the pinch voltage and zero voltage is formed between the plurality of second electrodes Yc and one of the first odd-numbered electrodes X1 and X3, and a grayscale voltage is formed between the plurality of second electrodes Yc and one of the first even-numbered electrodes X2 and X4, the plurality of pixels P display a grayscale line GL2 based on the grayscale voltage. For example, in the case of a short circuit between adjacent electrodes on the second substrate 112, two of the plurality of second electrodes Yc (i.e., a certain second odd-numbered electrode and an adjacent second even-numbered electrode) are short-circuited to each other. These two second electrodes Yc form grayscale voltages with a voltage range between 0 and 20V or -20 and 0V between the first odd-numbered electrodes X1 and X3 and the first even-numbered electrodes X2 and X4, respectively, causing the pixel P connected to these two second electrodes Yc to display a grayscale line GL2 based on the grayscale voltage. In this way, the two second electrodes Yc at the position corresponding to the grayscale line GL2 can be detected as short-circuit defects.

[0114] Please refer to the following: Figure 1 , Figure 4 , Figure 5 and Figure 6 ,in Figure 4 It is a drawing Figure 1 A schematic diagram of the wiring connections for the display device; Figure 5 It is a drawing Figure 1Detailed structural diagrams of the first odd-numbered test circuit, the first chip package structure, and the first fan-out circuit structure; and Figure 6 It is a drawing Figure 1 Detailed structural diagrams of the first even-numbered test circuit, another first chip package structure, and another first fan-out circuit structure.

[0115] In some embodiments, the display device 100 may further include two first chip package structures 141 and 142, and the two first chip package structures 141 and 142 are respectively disposed on the left step and right step of the second substrate 112, and respectively connected to the first odd-numbered test circuit 121 and the first even-numbered test circuit 122. Figure 1 , Figure 4 , Figure 5 and Figure 6 As shown, the first odd-number test circuit 121 may include a laser trimming block 1211 and an odd-line distribution block 1212. The first even-number test circuit 122 may include a laser trimming block 1221 and an even-line distribution block 1222. The first chip package structure 141 includes a plurality of first pins 1411, and a portion of the plurality of first pins 1411 is electrically connected to the odd-line distribution block 1212 via the laser trimming block 1211. The first chip package structure 142 may include a plurality of first pins 1421, and a portion of the plurality of first pins 1421 is electrically connected to the even-line distribution block 1222 via the laser trimming block 1221.

[0116] In some embodiments, the display device 100 may further include two second chip package structures 151 and 152, and the two second chip package structures 151 and 152 are respectively disposed on the upper step and lower step of the second substrate 112, and respectively connected to the second odd-numbered test circuit 131 and the second even-numbered test circuit 132. Figure 4 As shown, the second odd-number test circuit 131 may include a laser trimming block 1311 and an odd-line allocation block 1312. The second even-number test circuit 132 may include a laser trimming block 1321 and an even-line allocation block 1322. The second chip package structure 151 includes a plurality of second pins (not shown separately), and a portion of the plurality of second pins is electrically connected to the odd-line allocation block 1312 via the laser trimming block 1311 of the second odd-number test circuit 131. The second chip package structure 152 may include a plurality of second pins (not shown separately), and a portion of the plurality of second pins is electrically connected to the even-line allocation block 1322 via the laser trimming block 1321 of the second even-number test circuit 132. In other embodiments, the first and second chip package structures may also be bonding regions in a thin-film flip-chip packaging process.

[0117] In some embodiments, the display device 100 may further include two first fan-out structures 161, 162 (illustrated in...). Figure 5 and Figure 6 The first fan-out structure 161 includes a plurality of first fan-out wires 1611, which are electrically connected to the first pins 1411 and the first odd-numbered electrodes X1 and X3 of the first chip package structure 141, respectively. The first fan-out structure 162 includes a plurality of first fan-out wires 1621, which are electrically connected to the first pins 1421 and the first even-numbered electrodes X2 and X4 of the first chip package structure 142, respectively. In some embodiments, the display device 100 may further include two second fan-out structures (not otherwise labeled), which are respectively disposed on the upper and lower steps of the second substrate 112. One of the two second fan-out structures includes a plurality of second fan-out wires 1711, which are electrically connected to the second pins and the second odd-numbered electrodes Y1 and Y3 of the second chip package structure 151, respectively. The other of the two second fan-out structures includes a plurality of second fan-out wires 1721, which are electrically connected to the second pins and the second even-numbered electrodes Y2 and Y4 of the second chip package structure 152, respectively. Therefore, the first electrode Xr can be electrically connected to the left and right sets of first odd-numbered test circuits 121 and first even-numbered test circuits 122 via two first fan-out structures 161, 162 and two first chip package structures 141, 142 for testing. Similarly, the second electrode Yc can be electrically connected to the upper and lower sets of second odd-numbered test circuits 131 and second even-numbered test circuits 132 via two second fan-out structures and two second chip package structures 151, 152 for testing. After testing is completed, laser melting of all laser fine-tuning blocks 1211, 1221, 1311, 1321 restores the first electrode Xr and the second electrode Yc to independent wires.

[0118] The first electrode Xr of the first substrate 111 can be controlled by two first chip package structures 141 and 142 on the left and right steps. For example, the first odd-numbered electrode X1 can be jointly controlled by the first chip disposed on the first chip package structure 141 and the first chip disposed on the first chip package structure 142, forming a left-right dual-sided drive to reduce the resistance-capacitance delay time (RC delay time), and the remaining first electrodes Xr follow the same order. The second electrode Yc of the second substrate 112 can be controlled by two second chip package structures 151 and 152 on the upper and lower steps. For example, the second odd-numbered electrode Y1 can be jointly controlled by the first chip disposed on the second chip package structure 151 and the first chip disposed on the second chip package structure 152, forming an upper-lower dual-sided drive to reduce the resistance-capacitance delay time, and the remaining second electrodes Yc follow the same order. Therefore, this upper-lower and left-right dual-sided drive architecture can not only improve the charging rate of pixel P, but also display black and white lines in the active area by using the detection method of paired odd and even electrodes. If adjacent lines are short-circuited, grayscale lines GL1 or GL2 will be formed, and short-circuit defects can be detected from this.

[0119] In some embodiments, the display panel 110 may further include two conductive adhesive structures CP1 and CP2 and a frame adhesive structure F (illustrated in...). Figure 1 The two conductive adhesive structures CP1 and CP2, and the frame adhesive structure F, can all serve as frame adhesives for sealing the liquid crystal cell and are disposed between the first substrate 111 and the second substrate 112. Conductive adhesive structure CP1 is applied to the left side inside the display panel 110, i.e., the side near the signal output of the first odd-numbered test circuit 121. Conductive adhesive structure CP2 is applied to the right side inside the display panel 110, i.e., the side near the signal output of the first even-numbered test circuit 122. Specifically, the two conductive adhesive structures CP1 and CP2 can complete the function of conducting the first electrode Xr through the cell assembly process, while the frame adhesive structure F is mainly used to seal the liquid crystal cell and the two conductive adhesive structures CP1 and CP2 located on the left and right sides to prevent liquid crystal leakage.

[0120] Conductive adhesive structure CP1 is electrically connected to one end of the plurality of first electrodes Xr and the plurality of first fan-out wires 1611 of the first fan-out structure 161. Conductive adhesive structure CP2 is electrically connected to the other end of the plurality of first electrodes Xr and the plurality of first fan-out wires 1621 of the first fan-out structure 162. The frame adhesive structure F forms a closed space with the first substrate 111 and the second substrate 112, and the two conductive adhesive structures CP1 and CP2 are located within this closed space. Furthermore, a closed region (not otherwise specified) may exist between the two conductive adhesive structures CP1 and CP2 and the frame adhesive structure F. When the two conductive adhesive structures CP1 and CP2 and the frame adhesive structure F do not overlap, the closed region may be a vacuum region or filled with cholesteric liquid crystal. In other embodiments, the edges of the two conductive adhesive structures may also be flush with the edges of the frame adhesive structure, or partially overlap with the frame adhesive structure.

[0121] The materials of the two conductive adhesive structures CP1 and CP2 can be, but are not limited to, anisotropic conductive film (ACF). Each of the two conductive adhesive structures CP1 and CP2 includes a resin matrix and multiple conductive units U (illustrated in...). Figure 7 The conductive units U can be, but are not limited to, anisotropic conductive gold balls. The density of the plurality of conductive units U is determined by the color of the cholesteric liquid crystal display panel, and the width of each of the two conductive adhesive structures CP1 and CP2 is determined by the density of the plurality of conductive units U. Furthermore, the widths of the two conductive adhesive structures CP1 and CP2 and the frame adhesive structure F can be equal or unequal depending on the cell gap of different colors. For example, the two conductive adhesive structures CP1 and CP2 can use different anisotropic conductive gold ball sizes in different colors (red, green, and blue) of liquid crystal cells, with the particle size order being red > green > blue; in other words, the density order is blue > green > red. The width of each conductive adhesive structure CP1 and CP2 can be greater than or equal to 700 μm, but this width cannot be too wide (or the density of the conductive gold balls cannot be too high) to avoid excessive impedance at the conduction point, which could lead to insufficient charging due to RC delay during signal transmission. In other embodiments, the conductive adhesive structure can use the same density of anisotropic conductive gold balls in liquid crystal cells of different colors.

[0122] Please refer to the following: Figure 1 , Figure 7 and Figure 8 ,in Figure 7 It is a drawing Figure 1 A cross-sectional view of the selected area in the image; and Figure 8 It is a drawing Figure 1 A cross-sectional view of another selected area within the image. Specifically, Figure 7 A cross-sectional view of the liquid crystal cell located in the selected area R1 of the display panel 110 is shown. Figure 8A cross-sectional view of the liquid crystal cell located in the selected area R2 of the display panel 110 is shown.

[0123] like Figure 1 and Figure 7 As shown, a metal layer 117, an insulating layer 116, a second conductive layer 115, a conductive adhesive layer 114, and a first conductive layer 113 may be sequentially stacked along direction D1 between the first substrate 111 and the second substrate 112 in the liquid crystal cell located in the selected area R1. The processes for the aforementioned layer structures can be coating processes, deposition processes, patterning processes, or other suitable processes. Deposition processes may include, for example, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or other suitable deposition processes. Patterning processes may include, for example, photolithography, etching, other suitable processes, or combinations thereof. In detail, a metal layer 117 (e.g., a molybdenum-aluminum alloy or a copper alloy) is disposed on the second substrate 112, and an insulating layer 116 (e.g., silicon nitride (SiNx), with a thickness ≥ 350 nm) is stacked upward along direction D1. The metal layer 117 is formed after a patterning process. Figure 1 The first fan-out conductor 1621 is formed. The insulating layer 116 is perforated by photolithography and etching to form a via, electrically connecting the metal layer 117 to the second conductive layer 115. A conductive adhesive layer 114 is disposed between the first conductive layer 113 and the second conductive layer 115, and is formed by a patterning process. Figure 1 The conductive adhesive structure CP2 is used in the first conductive layer 113 and the second conductive layer 115. The materials for the first conductive layer 113 and the second conductive layer 115 can be, but are not limited to, transparent conductive materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), other suitable transparent conductive materials, or combinations thereof. The first conductive layer 113 is formed after a patterning process. Figure 1 The first odd-numbered electrode X in M-1 .

[0124] When the first substrate 111 and the second substrate 112 are bonded together and pressed, the first conductive layer 113 (i.e., the first odd-numbered electrode X) M-1The conductive units U in the conductive adhesive layer 114 (i.e., conductive adhesive structure CP2) can be electrically connected to the second conductive layer 115. The second conductive layer 115 can be electrically connected to the metal layer 117 (i.e., the first fan-out conductor 1621) through vias, and then concentrated to the first chip package structure 142. Finally, it is electrically connected to the first even-numbered test circuit 122 via the first pin 1421 of the first chip package structure 142. In this way, the test signal (e.g., the first timing signal S1) generated from the first even-numbered test circuit 122 can be transmitted to the first odd-numbered electrode X via the aforementioned electrical connection lines. M-1 The same applies to the other first electrodes Xr.

[0125] like Figure 1 and Figure 8 As shown, in the liquid crystal cell located in the selected area R2, a metal layer 117, an insulating layer 116, a second conductive layer 115, and a liquid crystal layer 118 can be sequentially stacked between the first substrate 111 and the second substrate 112 along direction D1. The process for each of the aforementioned layers, in addition to coating, deposition, and patterning processes, may also include using liquid crystal dispensing, liquid crystal injection, or other suitable processes to place the liquid crystal layer 118 between the first substrate 111 and the second substrate 112. Specifically, the metal layer 117 is disposed on the second substrate 112, and the insulating layer 116 is stacked upwards along direction D1. The metal layer 117 is formed after a patterning process. Figure 1 The second fan-out conductor 1711 is formed. The insulating layer 116 is drilled through by photolithography and etching processes to form a via, allowing the metal layer 117 to be electrically connected to the second conductive layer 115. The second conductive layer 115 is formed by a patterning process. Figure 1 The second odd-numbered electrode Y1 in the middle.

[0126] The second conductive layer 115 (i.e., the second odd-numbered electrode Y1) can be electrically connected to the metal layer 117 (i.e., the second fan-out conductor 1711) through vias, and is concentrated in the second chip package structure 151. Finally, it is electrically connected to the second odd-numbered test circuit 131 through the second pin of the second chip package structure 151. In this way, the test signal (e.g., the second timing signal S2) generated from the second odd-numbered test circuit 131 can be transmitted to the second odd-numbered electrode Y1 through the aforementioned electrical connection lines, and so on for the other second electrodes Yc.

[0127] Please see Figure 9 This is a schematic diagram illustrating a display device in a second embodiment according to the first embodiment of the present disclosure. Figure 9 As shown, the display panel 110a of the display device 100a may include two conductive adhesive structures CP3 and CP4 and two frame adhesive structures F1 and F2. The connection relationships between the conductive adhesive structures CP3 and CP4, the frame adhesive structures F1 and F2, and other components in the display device 100a are all related to... Figure 1The corresponding component connections of the display panel 110 are the same. Furthermore, the materials and functions of the conductive adhesive structures CP3 and CP4, and the frame adhesive structures F1 and F2 are also the same. Figure 1 The corresponding components of the display panel 110 are the same. The difference between the two lies in the frame adhesive configuration structure.

[0128] Specifically, conductive adhesive structures CP3 and CP4 and two-frame adhesive structures F1 and F2 are all disposed between the first substrate 111a and the second substrate 112a, and are interconnected to form a ring-shaped frame adhesive. Therefore, compared to Figure 1 Display panel 110, Figure 9 The 110a display panel features a narrow bezel and a high screen ratio thanks to its dual-side drive architecture on the top, bottom, left, and right sides.

[0129] Please refer to the following: Figure 2 and Figure 10 ,in Figure 10 This is a schematic diagram illustrating a display device according to a third embodiment of the first embodiment of the present disclosure. As shown in Figures 2 and 10, the display device 100b includes a display panel 110b, a first test module 120b, and a second test module 130b, wherein the configuration relationship between the display panel 110b, the first test module 120b, and the second test module 130b is as follows: Figure 1 The configuration relationship between the corresponding components of the display panel 110 is similar. The difference between the two is that after the panel is rotated (for example, rotated 90 degrees clockwise), its connection configuration with the test modules on each step is different, but the detection method of pairing odd and even electrodes is still the same.

[0130] Specifically, the plurality of first electrodes Xc on the first substrate 111b are arranged extending in the direction D3 and connected to the plurality of pixels P, and the plurality of first electrodes Xc are divided into a plurality of first odd-numbered electrodes X1, X3, ..., X M-1 and multiple first even-numbered electrodes X2, X4, ..., X M The plurality of second electrodes Yr on the second substrate 112b are arranged extending in direction D2 and connected to the plurality of pixels P, and the plurality of second electrodes Yr are divided into a plurality of second odd-numbered electrodes Y1, Y3, ..., Y N-1 and multiple second even-numbered electrodes Y2, Y4, ..., Y N .

[0131] Furthermore, the display panel 110b may also include two conductive adhesive structures CP5 and CP6 and a frame adhesive structure F. The configuration, materials, and functions of the two conductive adhesive structures CP5 and CP6 and the frame adhesive structure F are related to... Figure 1The conductive adhesive structures CP1 and CP2 are similar to the frame adhesive structure F, so details will not be elaborated further. For ease of explanation, only the first odd-numbered electrodes X1 and X3 are listed below to represent all first odd-numbered electrodes X1, X3, ..., Xc. M-1 And only the first even-numbered electrodes X2 and X4 are listed to represent all first even-numbered electrodes X2, X4, ..., X M Similarly, for the second electrode Yr, only the second odd-numbered electrodes Y1 and Y3 are listed below to represent all second odd-numbered electrodes Y1, Y3, ..., Yr. N-1 And only the second even-numbered electrodes Y2 and Y4 are listed to represent all second even-numbered electrodes Y2, Y4, ..., Y N .

[0132] The first odd-numbered test circuit 121b and the first even-numbered test circuit 122b of the first test module 120b are located on the left and right steps of the second substrate 112b, respectively. The first odd-numbered test circuit 121b is coupled to the second odd-numbered electrodes Y1 and Y3, and is used to electrically connect the second odd-numbered electrodes Y1 and Y3 to each other. The first even-numbered test circuit 122b is coupled to the second even-numbered electrodes Y2 and Y4, and is used to electrically connect the second even-numbered electrodes Y2 and Y4 to each other. The second odd-numbered test circuit 131b and the second even-numbered test circuit 132b of the second test module 130b are located on the upper and lower steps of the second substrate 112b, respectively. The second odd-numbered test circuit 131b is coupled to the first odd-numbered electrodes X1 and X3, and is used to electrically connect the first odd-numbered electrodes X1 and X3 to each other. The second even-numbered test circuit 132b is coupled to the first even-numbered electrodes X2 and X4, and is used to electrically connect the first even-numbered electrodes X2 and X4 to each other.

[0133] To detect whether there is a short-circuit defect in the electrodes of the upper substrate (i.e., the first electrodes Xc disposed on the first substrate 111b), a first timing signal S1 can be provided to the first odd electrodes X1, X3 and the first even electrodes X2, X4 through the second odd test circuit 131b and the second even test circuit 132b, respectively. Then, a second timing signal S2 can be provided to the second odd electrodes Y1, Y3 through the first odd test circuit 121b, and a third timing signal S3 can be provided to the second even electrodes Y2, Y4 through the first even test circuit 122b. In the case of a short circuit between adjacent electrodes in the first substrate 111b, two of the multiple first electrodes Xc (i.e., a certain first odd electrode and an adjacent first even electrode) are short-circuited to each other. These two first electrodes Xc form a grayscale voltage with a voltage range between 0 and 20V or -20 and 0V between the second odd electrodes Y1, Y3 and the second even electrodes Y2, Y4, respectively, causing the pixel P connected to these two first electrodes Xc to display a grayscale line based on the grayscale voltage. In this way, the two first electrodes Xc at the corresponding grayscale line positions can be detected as short-circuit defects.

[0134] Please refer to the following: Figure 1 , Figure 2 and Figure 11 ,in Figure 11 This is a schematic flowchart illustrating a display device testing method according to a second embodiment of this disclosure. Figure 1 , Figure 2 and Figure 11 As shown, the display device detection method 200 can be used to detect whether there is a short circuit defect in the electrodes of the upper and lower substrates of the display device 100, and includes the following steps S01, S02, S03 and S04.

[0135] Step S01 involves providing a first timing signal S1 to one of the plurality of first electrodes Xr and the plurality of second electrodes Yc via either the first test module 120 or the second test module 130 (i.e., simultaneously providing the first timing signal S1 to either the plurality of first electrodes Xr or the plurality of second electrodes Yc).

[0136] Step S02 provides a second timing signal S2 and a third timing signal S3 with opposite phases to the other of the plurality of first electrodes Xr and the plurality of second electrodes Yc via the other of the first test module 120 and the second test module 130.

[0137] Step S03 uses multiple pixels P in the display device 100 to transmit signals from multiple first odd-numbered electrodes X1, X3, ..., Xr among the multiple first electrodes Xr. M-1 Multiple first even-numbered electrodes X2, X4, ..., X M and the plurality of second odd-numbered electrodes Y1, Y3, ..., Yc in the plurality of second electrodes Yc N-1 and multiple second even-numbered electrodes Y2, Y4, ..., Y N Receive the first timing signal S1, the second timing signal S2 and the third timing signal S3, thereby displaying multiple lines.

[0138] Step S04 determines whether a grayscale line appears among the plurality of lines to generate a detection result. In step S04, when the detection result is "yes" (i.e., two adjacent lines among the plurality of lines appear as grayscale lines), it can be detected that two of the plurality of first electrodes Xr or two of the plurality of second electrodes Yc at the position corresponding to the grayscale line are short-circuit defects. When the detection result is "no" (i.e., no grayscale line appears among the plurality of lines), the display device 100 is determined to be a good product. Therefore, the display device detection method 200 of this disclosure can provide a detection method for odd and even electrode pairs for display devices 100 with four-sided steps, thereby effectively detecting whether the first electrode Xr or the second electrode Yc of the display panel 110 has defects, preventing defective products from being missed in subsequent processes, thereby reducing product manufacturing costs.

[0139] Please refer to the following: Figure 2 , Figure 12 and Figure 13 ,in Figure 12 This is a schematic diagram illustrating a display device according to a third embodiment of the present disclosure; and Figure 13 It is a drawing Figure 12 A schematic diagram of the wiring connections for the display device. (See diagram below.) Figure 2 and Figure 12 As shown, the display device 300 includes a display panel 310, a first test module 320, and a second test module 330.

[0140] The display panel 310 includes a plurality of pixels P, a first substrate 311, and a second substrate 312. The first substrate 311 is provided with a plurality of first electrodes Xc connecting the plurality of pixels P. The plurality of first electrodes Xc extend in direction D3 and are divided into a plurality of first odd-numbered electrodes X1, ..., X2. M-1 and multiple first even-numbered electrodes X2, ..., X M Where M is an even number. The second substrate 312 is disposed opposite to the first substrate 311 and is provided with a plurality of second electrodes Yr connecting the plurality of pixels P. The plurality of second electrodes Yr extend in direction D2 and are grouped into a first electrode group GY1 and a second electrode group GY2. The first electrode group GY1 includes a plurality of second odd-numbered electrodes Y. 11 ..., Y 1K-1 and multiple second even-numbered electrodes Y 12 ..., Y 1K Where K is an even number. The second electrode group GY2 contains multiple third odd-numbered electrodes Y. 21 ..., Y 2N-1 and multiple third even-numbered electrodes Y 22 ..., Y 2N , where N is an even number.

[0141] The first test module 320 is coupled to the first odd-numbered electrodes X1, ..., X2. M-1 and the first electrode group GY1, and provides a first timing signal S1 to the first odd-numbered electrodes X1, ..., X M-1 The second test module 330 is coupled to the first even-numbered electrodes X2, ..., X... M and the second electrode group GY2, and provides a first timing signal S1 to the first even-numbered electrodes X2, ..., X M Furthermore, the first test module 320 provides a second timing signal S2 and a third timing signal S3 with opposite phases to the second odd-numbered electrode Y of the first electrode group GY1. 11 ..., Y 1K-1 and the second even-numbered electrode Y 12 ..., Y 1KSimultaneously, the second test module 330 also provides a second timing signal S2 and a third timing signal S3 to the third odd-numbered electrode Y of the second electrode group GY2. 21 ..., Y 2N-1 and the third even-numbered electrode Y 22 ..., Y 2N The plurality of pixels P are determined according to the first odd-numbered electrodes X1, ..., X... M-1 First even-numbered electrode X2, ..., X M Second odd-numbered electrode Y 11 ..., Y 1K-1 Second even-numbered electrode Y 12 ..., Y 1K The third odd-numbered electrode Y 21 ..., Y 2N-1 and the third even-numbered electrode Y 22 ..., Y 2N The received first timing signal S1, second timing signal S2, and third timing signal S3 display multiple lines. When two adjacent lines among the multiple lines form a grayscale line, two of the multiple first electrodes Xc or two of the multiple second electrodes Yr at the corresponding grayscale line positions can be detected as a short-circuit defect.

[0142] Specifically, the plurality of first electrodes Xc and the second odd-numbered electrodes Y 11 ..., Y 1K-1 and the third odd-numbered electrode Y 21 ..., Y 2N-1 A pinch voltage can be formed between the plurality of first electrodes Xc and the second even-numbered electrodes Y. 12 ..., Y 1K and the third even-numbered electrode Y 22 ..., Y 2N A zero voltage can be formed between them. The plurality of pixels P display alternating black and white lines based on the difference voltage and the zero voltage, respectively. When the plurality of first electrodes Xc and the second odd-numbered electrodes Y 11 ..., Y 1K-1 and the third odd-numbered electrode Y 21 ..., Y 2N-1 A grayscale voltage between the first electrode Xc and the second even-numbered electrode Y is formed between the first electrode Xc and the second even-numbered electrode Yc. 12 ..., Y 1K and the third even-numbered electrode Y 22 ..., Y 2N When a grayscale voltage is formed between the two, the plurality of pixels P display the aforementioned grayscale line according to the grayscale voltage.

[0143] like Figure 12 and Figure 13As shown, the first test module 320 is disposed on the upper step of the second substrate 312, and may include a first odd-numbered test circuit C. O1 1. Second odd number test circuit C O2 and a first even-numbered test circuit C E1 The first odd-numbered test circuit C O1 Coupled to the first odd-numbered electrodes X1, ..., X M-1 And used to connect the first odd-numbered electrodes X1, ..., X M-1 They are electrically connected to each other. The second odd-numbered test circuit C O2 Coupled to the second odd-numbered electrode Y 11 ..., Y 1K-1 And used to connect the second odd-numbered electrode Y 11 ..., Y 1K-1 They are electrically connected to each other. First even-numbered test circuit C E1 Coupled to the second even-numbered electrode Y 12 ..., Y 1K And used to connect the second even-numbered electrode Y 12 ..., Y 1K They are electrically connected to each other.

[0144] The second test module 330 is disposed on the lower step of the second substrate 312 and includes a second even-numbered test circuit C. E2 A third even-number test circuit C E3 and a third odd-numbered test circuit C O3 The second even-numbered test circuit C E2 Coupled to the first even-numbered electrodes X2, ..., X M And used to connect the first even-numbered electrodes X2, ..., X M They are electrically connected to each other. Third even-numbered test circuit C E3 Coupled to the third even-numbered electrode Y 22 ..., Y 2N And used to connect the third even-numbered electrode Y 22 ..., Y 2N They are electrically connected to each other. Third odd-numbered test circuit C O3 Coupled to the third odd-numbered electrode Y 21 ..., Y 2N-1 And used to connect the third odd-numbered electrode Y 21 ..., Y 2N-1 They are electrically connected to each other.

[0145] In some embodiments, the display device 300 may further include an upper-stepped package structure 340 and a lower-stepped package structure 350. The upper-stepped package structure 340 includes a first chip package structure S. P1 A second chip packaging structure S P2 and a third chip packaging structure S P3The stepped-down package structure 350 includes a fourth chip package structure S. P4 The fifth chip packaging structure S P5 and a sixth chip packaging structure S P6 .

[0146] First chip packaging structure S P1 The second substrate 312 is disposed thereon and includes a plurality of first pins, wherein a portion of the plurality of first pins is connected to a first odd-numbered test circuit C. O1 A laser trimming block is electrically connected to the first odd-numbered test circuit C. O1 The first odd-line allocation block. Second chip packaging structure S P2 The second substrate 312 is disposed thereon and includes a plurality of second pins, wherein a portion of the plurality of second pins is connected to a second odd-numbered test circuit C. O2 A laser trimming block is electrically connected to the second odd-numbered test circuit C. O2 The odd-numbered line allocation block. Third chip packaging structure S P3 The second substrate 312 is disposed thereon and includes a plurality of third pins, wherein a portion of the plurality of third pins is connected to a first even-numbered test circuit C. E1 A laser trimming block is electrically connected to the first even-numbered test circuit C. E1 A single-line allocation block. Fourth chip package structure S P4 The second substrate 312 is disposed thereon and includes a plurality of fourth pins, wherein a portion of the plurality of fourth pins is connected to a second even-numbered test circuit C. E2 A laser trimming block is electrically connected to the second even-numbered test circuit C. E2 A single-line allocation block. Fifth chip package structure S P5 The second substrate 312 is disposed thereon and includes a plurality of fifth pins, wherein a portion of the plurality of fifth pins is connected to a third odd-numbered test circuit C. O3 A laser trimming block is electrically connected to the third odd-numbered test circuit C. O3 The odd-numbered line is allocated to the block. The sixth chip packaging structure S P6 The second substrate 312 is disposed thereon and includes a plurality of sixth pins, wherein a portion of the plurality of sixth pins is connected to a third even-numbered test circuit C. E3 A laser trimming block is electrically connected to the third even-numbered test circuit C. E3 A single-line allocation block.

[0147] In some embodiments, the display device 300 may further include a first fan-out structure (not otherwise labeled) and a second fan-out structure (not otherwise labeled). The first fan-out structure is disposed on the second substrate 312 and includes a plurality of first fan-out wires 3611. One end of the plurality of first fan-out wires 3611 is electrically connected to the plurality of first pins, the plurality of second pins, and the plurality of third pins, respectively, and the other end of the plurality of first fan-out wires 3611 is electrically connected to the plurality of first electrodes Xc and the first electrode group GY1, respectively. The second fan-out structure is disposed on the second substrate 312 and includes a plurality of second fan-out wires 3711, wherein one end of the plurality of second fan-out wires 3711 is electrically connected to the plurality of fourth pins, the plurality of fifth pins, and the plurality of sixth pins, respectively, and the other end of the plurality of second fan-out wires 3711 is electrically connected to the plurality of first electrodes Xc and the second electrode group GY2, respectively.

[0148] In some embodiments, the display panel 310 may further include two conductive adhesive structures CP5 and CP6 and a frame adhesive structure F (illustrated in...). Figure 12 The conductive adhesive structures CP5 and CP6, and the frame adhesive structure F are all disposed between the first substrate 311 and the second substrate 312. The conductive adhesive structure CP5 is coated on the upper side inside the display panel 310 and electrically connects one end of the plurality of first electrodes Xc and the plurality of first fan-out wires 3611 of the first fan-out structure. The conductive adhesive structure CP6 is coated on the lower side inside the display panel 310 and electrically connects the other end of the plurality of first electrodes Xc and the plurality of second fan-out wires 3711. The frame adhesive structure F forms a closed space with the first substrate 311 and the second substrate 312, and the two conductive adhesive structures CP5 and CP6 are located within this closed space. The materials and functions of the two conductive adhesive structures CP5 and CP6 and the frame adhesive structure F are similar to those of the first substrate 311 and the second substrate 312. Figure 1 The conductive adhesive structures CP1 and CP2 and the frame adhesive structure F are the same, so the details will not be repeated.

[0149] Therefore, the display device 300 of this disclosure utilizes a detection method that pairs odd and even electrodes to detect all first electrodes Xc and second electrodes Yr, and determines that the electrode at the corresponding grayscale line position has a short-circuit defect. Furthermore, in the display device 300, the scan line (i.e., the second electrode Yr) is divided into upper and lower parts (first electrode group GY1 and second electrode group GY2), and the method for detecting the upper part of the first electrode group GY1 is similar to... Figure 10 Similar to the display device 100b, it is equivalent to moving part of the first odd-numbered test circuit 121b and the first odd-numbered test circuit 121b to the upper step; similarly, when detecting the lower half of the second electrode group GY2, part of the first odd-numbered test circuit 121b and the first odd-numbered test circuit 121b are also moved to the lower step, thereby achieving the purpose of narrow left and right bezels and dual-sided driving.

[0150] In summary, the display device and display device testing method disclosed herein have the following advantages: First, they optimize the testing circuit of the panel in the front-end process, preventing defective products from being missed in the back-end process, thereby avoiding the loss or rework of chips and related components, and thus reducing the production cost of the product; Second, since all odd lines (or even lines) in the odd line allocation area (or even line allocation area) are connected in series, the connected electrodes can be electrically connected to each other, thereby reducing the probe pressure of the test equipment and avoiding the increased risk of terminal scratches or glass breakage; Third, using a frame adhesive doped with anisotropic conductive gold balls to seal the liquid crystal cell can prevent liquid crystal leakage and conduct the electrodes of the upper substrate.

[0151] Although the present disclosure has been described above with reference to embodiments, it is not intended to limit the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the concept and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the claims.

Claims

1. A display device, characterized in that, Include: A display panel, comprising: Multiple pixels; A first substrate is provided with a plurality of first electrodes connected to the plurality of pixels, wherein the plurality of first electrodes are divided into a plurality of first odd-numbered electrodes and a plurality of first even-numbered electrodes; and A second substrate is disposed opposite to the first substrate and has a plurality of second electrodes connected to the plurality of pixels, wherein the plurality of second electrodes are divided into a plurality of second odd-numbered electrodes and a plurality of second even-numbered electrodes; A first test module is coupled to the plurality of first odd-numbered electrodes and the plurality of first even-numbered electrodes; as well as A second test module is coupled to the plurality of second odd-numbered electrodes and the plurality of second even-numbered electrodes; wherein, one of the first test module and the second test module provides a first timing signal, and the other of the first test module and the second test module provides a second timing signal and a third timing signal with opposite phases; The plurality of pixels display a plurality of lines based on the first timing signal, the second timing signal, and the third timing signal received from the plurality of first odd electrodes, the plurality of first even electrodes, the plurality of second odd electrodes, and the plurality of second even electrodes, and the first timing signal, the second timing signal, and the third timing signal are all pulse width modulation signals. Specifically, when two adjacent lines of the plurality of lines form a grayscale line, two of the plurality of first electrodes or two of the plurality of second electrodes at the position corresponding to the grayscale line are detected as a short-circuit defect.

2. The display device as claimed in claim 1, characterized in that, When the first test module provides the first timing signal to the plurality of first electrodes, and the second test module provides the second timing signal to the plurality of second odd-numbered electrodes and provides the third timing signal to the plurality of second even-numbered electrodes, a pinch voltage is formed between the plurality of first electrodes and the plurality of second odd-numbered electrodes, and a zero voltage is formed between the plurality of first electrodes and the plurality of second even-numbered electrodes. The plurality of pixels display a plurality of black lines and a plurality of white lines of the plurality of lines respectively according to the pinch voltage and the zero voltage, and the plurality of black lines and the plurality of white lines are arranged alternately with each other. and When a grayscale voltage is formed between the pinch voltage and the zero voltage between one of the plurality of first electrodes and one of the plurality of second odd-numbered electrodes, and when the grayscale voltage is formed between one of the plurality of first electrodes and one of the plurality of second even-numbered electrodes, the plurality of pixels display the grayscale line according to the grayscale voltage.

3. The display device as claimed in claim 1, characterized in that, When the first test module provides the second timing signal to the plurality of first odd-numbered electrodes and provides the third timing signal to the plurality of first even-numbered electrodes, and the second test module provides the first timing signal to the plurality of second electrodes, a pinch voltage is formed between the plurality of second electrodes and the plurality of first odd-numbered electrodes, and a zero voltage is formed between the plurality of second electrodes and the plurality of first even-numbered electrodes. The plurality of pixels display a plurality of black lines and a plurality of white lines of the plurality of lines respectively according to the pinch voltage and the zero voltage, and the plurality of black lines and the plurality of white lines are arranged alternately with each other. and When a grayscale voltage is formed between the pinch voltage and the zero voltage between one of the plurality of second electrodes and one of the plurality of first odd-numbered electrodes, and when the grayscale voltage is formed between one of the plurality of second electrodes and one of the plurality of first even-numbered electrodes, the plurality of pixels display the grayscale line according to the grayscale voltage.

4. The display device as claimed in claim 1, characterized in that, The first test module is disposed on the second substrate and includes: A first odd-number test circuit is coupled to the plurality of first odd-number electrodes and is used to electrically connect the plurality of first odd-number electrodes to each other; and A first even-number test circuit is coupled to the plurality of first even-number electrodes and is used to electrically connect the plurality of first even-number electrodes to each other. and The second test module is disposed on the second substrate and includes: A second odd-number test circuit is coupled to the plurality of second odd-number electrodes and is used to electrically connect the plurality of second odd-number electrodes to each other; and A second even-number test circuit is coupled to the plurality of second even-number electrodes and is used to electrically connect the plurality of second even-number electrodes to each other.

5. The display device as claimed in claim 4, characterized in that, Also includes: Two first chip package structures are disposed on the second substrate, wherein each of the two first chip package structures includes a plurality of first pins, a portion of the plurality of first pins of one of the two first chip package structures is electrically connected to the first odd-numbered test circuit, and a portion of the plurality of first pins of the other of the two first chip package structures is electrically connected to the first even-numbered test circuit; and Two second chip package structures are disposed on the second substrate, wherein each of the two second chip package structures includes a plurality of second pins, a portion of the plurality of second pins of one of the two second chip package structures is electrically connected to the second odd-numbered test circuit, and a portion of the plurality of second pins of the other of the two second chip package structures is electrically connected to the second even-numbered test circuit.

6. The display device as claimed in claim 5, characterized in that, Also includes: Two first fan-out structures are disposed on the second substrate, wherein each of the two first fan-out structures includes a plurality of first fan-out wires, the plurality of first fan-out wires of one of the two first fan-out structures are electrically connected to the plurality of first pins and the plurality of first odd-numbered electrodes of that of the two first chip package structures, and the plurality of first fan-out wires of the other of the two first fan-out structures are electrically connected to the plurality of first pins and the plurality of first even-numbered electrodes of that of the other of the two first chip package structures; and Two second fan-out structures are disposed on the second substrate, wherein each of the two second fan-out structures includes a plurality of second fan-out wires, the plurality of second fan-out wires of one of the two second fan-out structures are electrically connected to the plurality of second pins and the plurality of second odd-numbered electrodes of that of the two second chip package structures, and the plurality of second fan-out wires of the other of the two second fan-out structures are electrically connected to the plurality of second pins and the plurality of second even-numbered electrodes of that of the other of the two second chip package structures.

7. The display device as claimed in claim 6, characterized in that, The display panel also includes: Two conductive adhesive structures are disposed between the first substrate and the second substrate, wherein one of the two conductive adhesive structures is electrically connected to one end of the plurality of first electrodes and the plurality of first fan-out wires of the two first fan-out structures, and the other of the two conductive adhesive structures is electrically connected to the other end of the plurality of first electrodes and the plurality of first fan-out wires of the other of the two first fan-out structures. and A frame adhesive structure is disposed between the first substrate and the second substrate, and forms a closed space with the first substrate and the second substrate, wherein the two conductive adhesive structures are located in the closed space.

8. The display device as claimed in claim 7, characterized in that, The material of the two conductive adhesive structures is an anisotropic conductive adhesive.

9. The display device as claimed in claim 7, characterized in that, The display panel is a liquid crystal display panel, and each of the two conductive adhesive structures contains a plurality of conductive units, the density of which is determined by a color of the liquid crystal display panel.

10. The display device as claimed in claim 9, characterized in that, The width of each of the two conductive adhesive structures is determined by the density of the plurality of conductive units.

11. The display device as claimed in claim 6, characterized in that, The display panel also includes: Two conductive adhesive structures are disposed between the first substrate and the second substrate, wherein one of the two conductive adhesive structures is electrically connected to one end of the plurality of first electrodes and the plurality of first fan-out wires of the two first fan-out structures, and the other of the two conductive adhesive structures is electrically connected to the other end of the plurality of first electrodes and the plurality of first fan-out wires of the other of the two first fan-out structures. and A two-frame adhesive structure is disposed between the first substrate and the second substrate, and is interconnected with the two conductive adhesive structures to form a ring-shaped frame adhesive.

12. A display device, characterized in that, Include: A display panel, comprising: Multiple pixels; A first substrate is provided with a plurality of first electrodes connected to the plurality of pixels, wherein the plurality of first electrodes are divided into a plurality of first odd-numbered electrodes and a plurality of first even-numbered electrodes; and A second substrate is disposed opposite to the first substrate and has a plurality of second electrodes connected to the plurality of pixels. The plurality of second electrodes are divided into a first electrode group and a second electrode group. The first electrode group includes a plurality of second odd-numbered electrodes and a plurality of second even-numbered electrodes, and the second electrode group includes a plurality of third odd-numbered electrodes and a plurality of third even-numbered electrodes. A first test module is coupled to the plurality of first odd-numbered electrodes and the first electrode group, and provides a first timing signal to the plurality of first odd-numbered electrodes; as well as A second test module is coupled to the plurality of first even-numbered electrodes and the second electrode group, and provides the first timing signal to the plurality of first even-numbered electrodes; The first test module provides a second timing signal and a third timing signal with opposite phases to the plurality of second odd electrodes and the plurality of second even electrodes, respectively. The second test module provides the second timing signal and the third timing signal to the plurality of third odd-numbered electrodes and the plurality of third even-numbered electrodes, respectively. The plurality of pixels display a plurality of lines based on the first timing signal, the second timing signal, and the third timing signal received from the plurality of first odd electrodes, the plurality of first even electrodes, the plurality of second odd electrodes, the plurality of second even electrodes, the plurality of third odd electrodes, and the plurality of third even electrodes, and the first timing signal, the second timing signal, and the third timing signal are all pulse width modulation signals; Specifically, when two adjacent lines of the plurality of lines form a grayscale line, two of the plurality of first electrodes or two of the plurality of second electrodes at the position corresponding to the grayscale line are detected as a short-circuit defect.

13. The display device as claimed in claim 12, characterized in that, A pinch voltage is formed between the plurality of first electrodes, the plurality of second odd electrodes, and the plurality of third odd electrodes, and a zero voltage is formed between the plurality of first electrodes, the plurality of second even electrodes, and the plurality of third even electrodes. The plurality of pixels display a plurality of black lines and a plurality of white lines of the plurality of lines respectively according to the pinch voltage and the zero voltage, and the plurality of black lines and the plurality of white lines are arranged alternately with each other. and When a grayscale voltage between the pinch voltage and the zero voltage is formed between one of the plurality of first electrodes, the plurality of second odd electrodes, and the plurality of third odd electrodes, and when the grayscale voltage is formed between one of the plurality of first electrodes, the plurality of second even electrodes, and the plurality of third even electrodes, the plurality of pixels display the grayscale line according to the grayscale voltage.

14. The display device as claimed in claim 12, characterized in that, The first test module is disposed on the second substrate and includes: A first odd-number test circuit is coupled to the plurality of first odd-number electrodes and is used to electrically connect the plurality of first odd-number electrodes to each other; A second odd-number test circuit is coupled to the plurality of second odd-number electrodes and is used to electrically connect the plurality of second odd-number electrodes to each other; and A first even-number test circuit is coupled to the plurality of second even-number electrodes and is used to electrically connect the plurality of second even-number electrodes to each other; and The second test module is disposed on the second substrate and includes: A second even-number test circuit is coupled to the plurality of first even-number electrodes and is used to electrically connect the plurality of first even-number electrodes to each other. A third even-number test circuit is coupled to the plurality of third even-number electrodes and is used to electrically connect the plurality of third even-number electrodes to each other. and A third odd-number test circuit is coupled to the plurality of third odd-number electrodes and is used to electrically connect the plurality of third odd-number electrodes to each other.

15. The display device as claimed in claim 14, characterized in that, Also includes: A first chip package structure is disposed on the second substrate and includes a plurality of first pins, wherein a portion of the plurality of first pins is electrically connected to the first odd-numbered test circuit; A second chip package structure is disposed on the second substrate and includes a plurality of second pins, wherein a portion of the plurality of second pins is electrically connected to the second odd-numbered test circuit; A third chip package structure is disposed on the second substrate and includes a plurality of third pins, wherein a portion of the plurality of third pins is electrically connected to the first even-numbered test circuit; A fourth chip package structure is disposed on the second substrate and includes a plurality of fourth pins, wherein a portion of the plurality of fourth pins is electrically connected to the second even-numbered test circuit; A fifth chip package structure is disposed on the second substrate and includes a plurality of fifth pins, wherein a portion of the plurality of fifth pins is electrically connected to the third odd-numbered test circuit; and A sixth chip package structure is disposed on the second substrate and includes a plurality of sixth pins, wherein a portion of the plurality of sixth pins is electrically connected to the third even-numbered test circuit.

16. The display device as claimed in claim 15, characterized in that, Also includes: A first fan-out structure is disposed on the second substrate and includes a plurality of first fan-out wires, wherein one end of the plurality of first fan-out wires is electrically connected to the plurality of first pins, the plurality of second pins and the plurality of third pins respectively, and the other end of the plurality of first fan-out wires is electrically connected to the plurality of first electrodes and the first electrode group respectively. and A second fan-out structure is disposed on the second substrate and includes a plurality of second fan-out wires, wherein one end of the plurality of second fan-out wires is electrically connected to the plurality of fourth pins, the plurality of fifth pins and the plurality of sixth pins respectively, and the other end of the plurality of second fan-out wires is electrically connected to the plurality of first electrodes and the second electrode group respectively.

17. The display device as claimed in claim 16, characterized in that, The display panel also includes: Two conductive adhesive structures are disposed between the first substrate and the second substrate, wherein one of the two conductive adhesive structures is electrically connected to one end of the plurality of first electrodes and the plurality of first fan-out wires of the first fan-out structure, and the other of the two conductive adhesive structures is electrically connected to the other end of the plurality of first electrodes and the plurality of second fan-out wires. and A frame adhesive structure is disposed between the first substrate and the second substrate, and forms a closed space with the first substrate and the second substrate, wherein the two conductive adhesive structures are located in the closed space.

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