Pixel driving circuit and image sensor

Abstract

The utility model provides a pixel driving circuit and an image sensor, the pixel driving circuit comprises a plurality of pixel driving units, each pixel driving unit at least comprises a first driving unit and a second driving unit, and when the pixel units in the nth row are quantized and read out, the first driving unit and the second driving unit are separated from each other. The first driving unit outputs a first pulse signal based on the first read-out control signal to control the pixel units in the n row to read out, meanwhile, the second driving unit connected with the pixel units in the (n + 1) row outputs a second voltage signal based on the first read-out control signal, and when the pixel units in the (n + 1) row are quantized and read out, the second driving unit is connected with the pixel units in the (n + 1) row. The second driving unit outputs a second pulse signal based on a second read-out control signal to control the pixel units in the (n + 1) th row to read out, meanwhile, the first driving unit connected with the pixel units in the nth row outputs a second voltage signal based on the second read-out control signal, and the voltages output in a front-and-back quantized mode are symmetrical and free of noise influence; and the quantization effect and the image display effect are improved.

Description

Technical Field

[0001] This invention belongs to the field of image sensor technology, and particularly relates to a pixel driving circuit and an image sensor. Background Technology

[0002] Image sensors are widely used in many fields such as consumer electronics, security, automatic control and medical care. In particular, with the rise of smart terminals in recent years, the demand for low power consumption has become more important.

[0003] Image sensors typically include pixel circuitry and corresponding pixel driving circuitry. The pixel circuitry consists of an array of pixel units, and the pixel driving circuitry can include multiple pixel driving units. Each pixel driving unit can provide a gate control signal to one or more pixel units, thereby controlling the on and off states of the transmission transistors in the pixel units.

[0004] Among them, such as Figure 1 and Figure 2 As shown, the pixel driving circuit consists of multiple branches connected in parallel to the positive power supply terminal, the first voltage terminal, and the second voltage terminal. The positive power supply terminal is used to input a positive voltage, the first voltage terminal is used to input a first voltage signal, and the second voltage terminal is used to input a second voltage signal. The signals include an exposure control signal, a readout control signal, and a gate control signal. The exposure control signal may include a pre-exposure address digital signal (sp_add) and a pre-exposure transfer digital signal (dd_sp_tx), and the readout control signal may include a readout address digital signal (rp_add) and a readout transfer digital signal (dd_rp_tx).

[0005] The first voltage signal supplies low-level power to the unselected rows, and the second voltage signal supplies low-level power to the selected rows. When the pixel unit of the nth row is quantized and read out, the pixel driving unit connected to the pixel unit of the (n+1)th row outputs the first voltage signal. Since there are often thousands of rows in the unselected rows, the first voltage signal has a lot of noise. The noise of the first voltage signal of the unselected rows will couple to the selected nth row, causing voltage fluctuations in the gate control signal input to the nth row, affecting the quantization result.

[0006] Furthermore, when quantizing and reading out the nth row, the pixel driving unit of the (n+1)th row is in the exposure stage and outputs a low potential. However, when quantizing the (n+1)th row, the pixel driving unit of the nth row is in the non-selection stage and outputs a high potential. During the quantization process, there is voltage asymmetry between adjacent quantization rows, which leads to quantization misalignment and ultimately causes image differences. Utility Model Content

[0007] The purpose of this invention is to provide a pixel driving circuit that solves the problems of quantization noise and quantization mismatch in traditional pixel driving circuits.

[0008] A first aspect of this utility model provides a pixel driving circuit for outputting multiple gate control signals to a pixel circuit. The pixel driving circuit includes multiple pixel driving units, each pixel driving unit transmitting gate control signals to at least two adjacent rows of pixel units in the pixel circuit to control the turning on and off of the transmission transistors in the pixel units. Each pixel driving unit includes at least:

[0009] A first driving unit is connected to the nth row of pixel units. During the exposure period of the nth row of pixel units, the first driving unit is triggered by a first exposure control signal to output a first voltage signal to control the exposure of the nth row of pixel units. During the selection period of the nth row of pixel units, the first driving unit is triggered by a first readout control signal to output a first pulse signal to the nth row of pixel units to read them out. During the selection period of the (n+1)th row of pixel units, the first driving unit outputs a second voltage signal to the nth row of pixel units based on a second readout control signal.

[0010] The second driving unit is connected to the (n+1)th row of pixel units. During the exposure period of the (n+1)th row of pixel units, the second driving unit is triggered by a second exposure control signal to output a first voltage signal to control the exposure of the (n+1)th row of pixel units. During the selection period of the (n+1)th row of pixel units, the second driving unit is triggered by a second readout control signal to output a second pulse signal to the (n+1)th row of pixel units to enable readout. During the selection period of the (n)th row of pixel units, the second driving unit outputs a second voltage signal to the (n+1)th row of pixel units based on the first readout control signal.

[0011] A second aspect of this utility model provides an image sensor, including a pixel circuit and a pixel driving circuit as described above, wherein the pixel driving circuit is connected to the pixel circuit, and the pixel circuit includes a plurality of pixel units arranged in an array.

[0012] The pixel circuit also includes:

[0013] Several reset circuits are provided, each reset circuit being connected to the floating diffusion nodes of multiple pixel units in the same column. The reset circuit is used to receive a reset signal to reset multiple pixel units.

[0014] Each pixel unit includes at least a photosensitive element, a transmission transistor, and a follower transistor connected in sequence, with the second end of the transmission transistor connected to a floating diffusion node.

[0015] The beneficial effects of this utility model embodiment compared with the prior art are as follows: The pixel driving circuit mentioned above includes multiple pixel driving units, and the pixel driving unit includes at least a first driving unit and a second driving unit. When quantizing and reading out the pixel unit of the nth row, the first driving unit outputs a first pulse signal based on the first readout control signal to control the reading out of the pixel unit of the nth row. At the same time, the second driving unit connected to the pixel unit of the (n+1)th row outputs a second voltage signal based on the first readout control signal. When quantizing and reading out the pixel unit of the (n+1)th row, the second driving unit outputs a second pulse signal based on the second readout control signal to control the reading out of the pixel unit of the (n+1)th row. At the same time, the first driving unit connected to the pixel unit of the nth row outputs a second voltage signal based on the second readout control signal. The voltage outputs before and after quantization are symmetrical and have no noise influence, which improves the quantization effect and image display effect. Attached Figure Description

[0016] Figure 1 This is a circuit diagram of a traditional pixel driving circuit;

[0017] Figure 2 This is a schematic diagram of the signal waveforms of a traditional pixel driving circuit.

[0018] Figure 3 This is a schematic diagram of the structure of the image sensor provided in an embodiment of the present invention;

[0019] Figure 4 This is a schematic diagram of the pixel driving circuit and pixel circuit provided in the embodiments of the present utility model;

[0020] Figure 5 This is a schematic diagram of a first structure of a pixel driving unit provided in an embodiment of the present utility model;

[0021] Figure 6 A first structural schematic diagram of the first driving unit and the second driving unit provided in the embodiments of this utility model;

[0022] Figure 7 A first circuit diagram of the first driving unit and the second driving unit provided in the embodiments of this utility model;

[0023] Figure 8 A schematic diagram of a first type of signal waveform of the first driving unit and the second driving unit provided in the embodiments of this utility model;

[0024] Figure 9 This is a schematic diagram of a second structure of the pixel driving unit provided in an embodiment of the present utility model;

[0025] Figure 10 A second structural schematic diagram of the first driving unit and the second driving unit provided in the embodiments of this utility model;

[0026] Figure 11 A second circuit diagram of the first driving unit provided in an embodiment of this utility model;

[0027] Figure 12 This is a second circuit diagram of the second driving unit provided in an embodiment of the present utility model;

[0028] Figure 13 A schematic diagram of a second type of signal waveform for the first driving unit and the second driving unit provided in an embodiment of this utility model;

[0029] Figure 14 This is a schematic diagram of a third structure of the pixel driving unit provided in an embodiment of the present invention;

[0030] Figure 15 A schematic diagram of a third type of signal waveform for the first driving unit and the second driving unit provided in the embodiments of this utility model;

[0031] Figure 16 A circuit diagram of the non-selection signal generation circuit and the two-to-one switch circuit provided in the embodiments of this utility model;

[0032] Figure 17 A circuit diagram of the pixel unit and reset circuit provided in an embodiment of this utility model. Detailed Implementation

[0033] To make the technical problems, technical solutions, and beneficial effects of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present utility model and are not intended to limit the present utility model.

[0034] In this description, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this utility model, "a plurality of" means two or more, unless otherwise explicitly specified.

[0035] The first aspect of this utility model embodiment provides a pixel driving circuit 100, such as... Figure 3As shown, the pixel driving circuit 100 is connected to the pixel circuit 200. The pixel circuit 200 includes multiple pixel units 210 arranged in an array. Pixel units 210 in the same column are connected to the same output line Lp. The pixel driving circuit 100 is used to output multiple gate control signals tx to the pixel circuit 200, thereby selecting the pixel unit 210 at the corresponding position for exposure and readout, and readout to the image sensor processing circuit through the output line Lp. The processing circuit determines the image information based on the readout signal.

[0036] like Figure 4 As shown, the pixel driving circuit 100 includes a plurality of pixel driving units 110. Each pixel driving unit 110 transmits a gate control signal tx to at least two adjacent rows of pixel units 210 in the pixel circuit 200 to control the turning on and off of the transmission transistor TX in the pixel unit 210. For example... Figure 5 As shown, each pixel driving unit 110 includes at least:

[0037] The first driving unit 111 is connected to the nth row pixel unit 210. During the exposure period of the nth row pixel unit 210, the first driving unit 111 is triggered by the first exposure control signal sp1 to output the first voltage signal NVDD1 to control the exposure of the nth row pixel unit 210. During the selection period of the nth row pixel unit 210, the first driving unit 111 is triggered by the first readout control signal rp1 to output the first pulse signal to the nth row pixel unit 210 to read it out. During the selection period of the (n+1)th row pixel unit 210, the first driving unit 111 outputs the second voltage signal NVDD2 to the nth row pixel unit 210 based on the second readout control signal rp2.

[0038] The second driving unit 112 is connected to the (n+1)th row pixel unit 210. During the exposure period of the (n+1)th row pixel unit 210, the second driving unit 112 is triggered by the second exposure control signal sp2 to output the first voltage signal NVDD1 to control the exposure of the (n+1)th row pixel unit 210. During the selection period of the (n+1)th row pixel unit 210, the second driving unit 112 is triggered by the second readout control signal rp2 to output the second pulse signal to the (n+1)th row pixel unit 210 to enable its readout. During the selection period of the (n)th row pixel unit 210, the second driving unit 112 outputs the second voltage signal NVDD2 to the (n+1)th row pixel unit 210 based on the first readout control signal rp1.

[0039] In this embodiment, each pixel driving unit 110 is connected to at least two rows of pixel units 210 and transmits gate control signals tx equal to the number of rows of connected pixel units 210.

[0040] Among them, the multiple rows of pixel units 210 connected to the pixel driving unit 110 can adopt a shared connection structure for multiple pixel units 210 in adjacent rows of the same column. The shared connection structure means that the floating diffusion nodes FD of multiple pixel units 210 are connected to the same reset circuit 220 and are reset through the reset circuit 220 during non-selected time periods, thereby realizing the continuous zeroing of charge in the pixel units 210 before exposure, preventing charge leakage and reducing the charge coupling effect between adjacent pixel rows.

[0041] Alternatively, multiple pixel units 210 in the same column can adopt a discrete structure, and each can be cleared of charge by its own connected reset circuit 220. The specific connection method is not limited.

[0042] The pixel driving circuit 100 and the pixel circuit 200 operate sequentially during the exposure period, the selection period, and the non-selection period (excluding the exposure period and the selection period). During the exposure period, the photosensitive element PD in the pixel unit 210 receives the light signal and exposes itself, generating an exposure signal. During the selection period, the transmission transistor TX in the pixel unit 210 receives the gate control signal tx and transmits the exposure signal to the floating diffusion node FD in the pixel unit 210, thereby reading out the corresponding exposure signal through the pixel unit 210 and realizing the selection readout of the pixel unit 210. During the non-selection period, the reset circuit 220 resets and clears the charge, reducing the influence of coupled charge.

[0043] The pixel driving circuit 100 sequentially exposes and selects each row of pixel units 210, that is, it exposes, selects and reads out pixel units 210 from the first row to the mth row, where m is the row number of pixel units 210, and n+1 is equal to or less than m.

[0044] When the nth row is exposed, the pixel unit 210 of the (n+1)th row is in the non-selected period and is in the reset state. At this time, during the exposure period of the pixel unit 210 of the nth row, the first driving unit 111 receives the first exposure control signal sp1. The first exposure control signal sp1 controls the first driving unit 111 to output the first voltage signal NVDD1. The first voltage signal NVDD1 supplies low-level power to the non-selected row and controls the exposure of the pixel unit 210 of the nth row.

[0045] Then, during the selection period of pixel unit 210 in row n, the first driving unit 111 receives the first readout control signal rp1 and triggers the output of the second voltage signal NVDD2 to pixel unit 210 in row n. The second voltage signal NVDD2 acts as the gate control signal tx to control pixel unit 210 in row n to read out the exposure signal and transmit it to the output line. At this time, the second driving unit 112 simultaneously receives the first readout control signal rp1 and triggers the output of the second voltage signal NVDD2. The second voltage signal NVDD2 acts as the gate control signal tx and is output to pixel unit 210 in row n+1. The second voltage signal NVDD2 provides low-level power supply for the selected row and has low voltage noise. Therefore, it can reduce the impact of noise coupling on row n and improve the quantization effect.

[0046] Then, the pixel unit 210 in the (n+1)th row is exposed. The pixel unit 210 in the nth row is in a non-selected period and is in a reset state. At this time, during the exposure period of the pixel unit 210 in the (n+1)th row, the second driving unit 112 receives the second exposure control signal sp2. The second exposure control signal sp2 controls the second driving unit 112 to output the first voltage signal NVDD1. The first voltage signal NVDD1 supplies low-level power to the non-selected row and controls the exposure of the pixel unit 210 in the (n+1)th row.

[0047] Then, during the selection period of pixel unit 210 in row n+1, the second driving unit 112 receives the second readout control signal rp2 and triggers the output of the second voltage signal NVDD2 to pixel unit 210 in row n+1. The second voltage signal NVDD2 acts as the gate control signal tx to control pixel unit 210 in row n+1 to read out the exposure signal and transmit it to the output line. At this time, the first driving unit 111 synchronously receives the second readout control signal rp2 and triggers the output of the second voltage signal NVDD2. The second voltage signal NVDD2 acts as the gate control signal tx and is output to pixel unit 210 in row n. The second voltage signal NVDD2 provides low-level power supply for the selected row and has low voltage noise. Therefore, it can reduce the impact of noise coupling on row n+1 and improve the quantization effect.

[0048] Furthermore, when pixel unit 210 in row n is selected for quantization, pixel unit 210 in row n+1 receives the second voltage signal NVDD2; and when pixel unit 210 in row n+1 is selected for quantization, pixel unit 210 in row n receives the second voltage signal NVDD2; the voltage output is symmetrical during the quantization process of pixel units in row n and row n+1, which can avoid the quantization misalignment of pixel units 210 in adjacent rows, achieve quantization consistency, and improve the signal output quality.

[0049] The first driving unit 111 and the second driving unit 112 can be composed of corresponding transistors to form an exposure circuit and a readout circuit, etc. In an optional embodiment, such as... Figure 6 As shown, the first drive unit 111 includes:

[0050] The first exposure branch 11 is connected to the positive power supply terminal, the first voltage terminal and the nth row pixel unit 210 respectively. The first voltage terminal is used to input the first voltage signal NVDD1. The first exposure branch 11 is used to output the first voltage signal NVDD1 when triggered by the first exposure control signal sp1 during the exposure period of the nth row pixel unit 210.

[0051] The first readout branch 12 is connected to the positive power supply terminal, the second voltage terminal and the nth row pixel unit 210 respectively. The second voltage terminal is used to input the second voltage signal NVDD2. The first readout branch 12 is used to output the first pulse signal to the nth row pixel unit 210 to read it out when triggered by the first readout control signal rp1 during the selected period of the nth row pixel unit 210.

[0052] The first switch branch 13 is connected to the second voltage terminal and the nth row pixel unit 210 respectively. The first switch branch 13 is used to output the second voltage signal NVDD2 to the nth row pixel unit 210 based on the second readout control signal rp2 during the selected period of the (n+1)th row pixel unit 210.

[0053] In an optional embodiment, the second drive unit 112 includes:

[0054] The second exposure branch 21 is connected to the positive power supply terminal, the first voltage terminal and the n+1th row pixel unit 210 respectively. The first voltage terminal is used to input the first voltage signal NVDD1. The second exposure branch 21 is used to output the first voltage signal NVDD1 when triggered by the second exposure control signal sp2 during the exposure period of the n+1th row pixel unit 210.

[0055] The second readout branch 22 is connected to the positive power supply terminal, the second voltage terminal and the n+1 row pixel unit 210 respectively. The second voltage terminal is used to input the second voltage signal NVDD2. The second readout branch 22 is used to output the second pulse signal to the n+1 row pixel unit 210 to read it out when triggered by the second readout control signal rp2 during the selected period of the n+1 row pixel unit 210.

[0056] The second switch branch 23 is connected to the second voltage terminal and the n+1th row pixel unit 210 respectively. The second switch branch 23 is used to output the second voltage signal NVDD2 to the n+1th row pixel unit 210 based on the first readout control signal rp1 during the selected period of the nth row pixel unit 210.

[0057] In this embodiment, when the nth row is exposed, the pixel unit 210 of the (n+1)th row is in a non-selected period and is in a reset state. At this time, during the exposure period of the pixel unit 210 of the nth row, the first exposure branch 11 of the first driving unit 111 receives the first exposure control signal sp1. The first exposure control signal sp1 controls the first exposure branch 11 to connect the first voltage terminal and its own output terminal, and outputs the first voltage signal NVDD1. The first voltage signal NVDD1 supplies low-level power to the non-selected row and controls the exposure of the pixel unit 210 of the nth row.

[0058] Then, during the selection period of pixel unit 210 in row n, the first readout branch 12 of the first driving unit 111 receives the first readout control signal rp1. The first readout branch 12 connects the second voltage terminal and its own output terminal, and outputs the second voltage signal NVDD2 to pixel unit 210 in row n. The second voltage signal NVDD2 acts as the gate control signal tx to control pixel unit 210 in row n to read out the exposure signal and transmit it to the output line. At this time, the second switching branch 23 of the second driving unit 112 synchronously receives the first readout control signal rp1. The second switching branch 23 is turned on and outputs the second voltage signal NVDD2 from the second voltage terminal. The second voltage signal NVDD2 acts as the gate control signal tx and is output to pixel unit 210 in row n+1. The second voltage signal NVDD2 provides low-level power supply for the selected row and has low voltage noise. Therefore, it can reduce the impact of noise coupling on row n and improve the quantization effect.

[0059] Then, the pixel unit 210 in the (n+1)th row is exposed. The pixel unit 210 in the nth row is in a non-selected period and is in a reset state. At this time, during the exposure period of the pixel unit 210 in the (n+1)th row, the second exposure branch 21 of the second driving unit 112 receives the second exposure control signal sp2. The second exposure branch 21 connects the first voltage terminal and its own output terminal and outputs the first voltage signal NVDD1. The first voltage signal NVDD1 supplies low-level power to the non-selected row and controls the exposure of the pixel unit 210 in the (n+1)th row.

[0060] Then, during the selection period of pixel unit 210 in row n+1, the second readout branch 22 of the second driving unit 112 receives the second readout control signal rp2. The second readout branch 22 triggers the connection between its own output terminal and second voltage terminal, and outputs the second voltage signal NVDD2 to pixel unit 210 in row n+1. The second voltage signal NVDD2 acts as the gate control signal tx to control pixel unit 210 in row n+1 to read out the exposure signal and transmit it to the output line. At this time, the first switch branch 13 of the first driving unit 111 synchronously receives the second readout control signal rp2. The first switch branch 13 is triggered to conduct and outputs the second voltage signal NVDD2. The second voltage signal NVDD2 acts as the gate control signal tx and is output to pixel unit 210 in row n. The second voltage signal NVDD2 provides low-level power supply for the selected row and has low voltage noise. Therefore, it can reduce the impact of noise coupling on row n+1 and improve the quantization effect.

[0061] Furthermore, when pixel unit 210 in row n is selected for quantization, pixel unit 210 in row n+1 receives the second voltage signal NVDD2. During the quantization process, the voltage is output symmetrically, which can avoid the quantization of pixel units 210 in adjacent rows from becoming misaligned, achieve quantization consistency, and improve the signal output quality.

[0062] Each exposure branch, readout branch, and switching branch can be composed of transistors of the corresponding type and number, and the specific structure is not limited.

[0063] In an alternative embodiment, such as Figure 7 As shown, the first exposure control signal sp1 includes a first pre-exposure address digital signal sp_add_n and a first pre-exposure transmission digital signal sp_txb_n, and the second exposure control signal sp2 includes a second pre-exposure address digital signal sp_add_n+1 and a second pre-exposure transmission digital signal sp_txb_n+1.

[0064] The first readout control signal rp1 includes the first readout address digital signal rp_add_n and the first readout transmission digital signal rp_txb_n, and the second readout control signal rp2 includes the second readout address digital signal rp_add_n+1 and the second readout transmission digital signal rp_txb_n+1.

[0065] The first exposure branch 11 includes a first transistor M1, a second transistor M2, a third transistor M3 and a fourth transistor M4 connected in series with the positive power supply terminal and the first voltage terminal.

[0066] The connection node of the second transistor M2 and the third transistor M3 constitutes the output terminal of the first exposure branch 11. The control terminals of the first transistor M1 and the fourth transistor M4 are used to input the first pre-exposure address digital signal sp_add_n, and the control terminals of the second transistor M2 and the third transistor M3 are used to input the first pre-exposure transmission digital signal sp_txb_n.

[0067] The first readout branch 12 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8 connected in series with the positive power supply terminal and the second voltage terminal.

[0068] The connection node of the sixth transistor M6 and the seventh transistor M7 constitutes the output terminal of the first exposure branch 11. The control terminals of the fifth transistor M5 and the eighth transistor M8 are used to input the first readout address digital signal rp_add_n, and the control terminals of the sixth transistor M6 and the seventh transistor M7 are used to input the first readout transmission digital signal rp_txb_n.

[0069] The first switch branch 13 includes the ninth transistor M9;

[0070] The first terminal of the ninth transistor M9 forms the output terminal of the first switch branch 13, the second terminal of the ninth transistor M9 is connected to the second voltage terminal, and the control terminal of the ninth transistor M9 is used to input the second read address digital signal rp_add_n+1.

[0071] The second exposure branch 21 includes a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, and a thirteenth transistor M13 connected in series with the positive power supply terminal and the first voltage terminal.

[0072] The connection node of the eleventh transistor M11 and the twelfth transistor M12 forms the output terminal of the second exposure branch 21. The control terminals of the tenth transistor M10 and the thirteenth transistor M13 are used to input the second pre-exposure address digital signal sp_add_n+1. The control terminals of the eleventh transistor M11 and the twelfth transistor M12 are used to input the second pre-exposure transmission digital signal sp_txb_n+1.

[0073] The second readout branch 22 includes a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, and a seventeenth transistor M17 connected in series with the positive power supply terminal and the second voltage terminal.

[0074] The connection node of the fifteenth transistor M15 and the sixteenth transistor M16 forms the output terminal of the second exposure branch 21. The control terminals of the fourteenth transistor M14 and the seventeenth transistor M17 are used to input the second readout address digital signal rp_add_n+1. The control terminals of the fifteenth transistor M15 and the sixteenth transistor M16 are used to input the second readout transmission digital signal rp_txb_n+1.

[0075] The second switch branch 23 includes the eighteenth transistor M18;

[0076] The first terminal of the eighteenth transistor M18 forms the output terminal of the second switch branch 23, the second terminal of the eighteenth transistor M18 is connected to the second voltage terminal, and the control terminal of the eighteenth transistor M18 is used to input the first read address digital signal rp_add_n.

[0077] In this embodiment, sp_addb_n is the opposite level of the first pre-exposure address digital signal sp_add_n, rp_addb_n is the opposite level of the first readout address digital signal rp_add_n, sp_addb_n+1 is the opposite level of the second pre-exposure address digital signal sp_add_n+1, rp_addb_n+1 is the opposite level of the second readout address digital signal rp_add_n+1, sp_txb is the pre-exposure transmission digital signal, and rp_txb is the readout transmission digital signal.

[0078] refer to Figure 8 As shown, when the nth row is exposed, during the exposure period of the pixel unit 210 in the nth row, the first transistor M1 of the first exposure branch 11 receives the opposite level signal sp_addb_n of the first pre-exposure address digital signal sp_add_n, and the first transistor M1 is turned off. The pre-exposure transmission digital signal sp_txb is a high-level pulse signal. The second transistor M2 and the third transistor M3 receive the high-level pulse of the first pre-exposure transmission digital signal sp_txb_n, and the second transistor M2 is triggered to turn off, the third transistor M3 is triggered to turn on, and the fourth transistor M4 receives the high-level first pre-exposure address digital signal sp_add_n, and the fourth transistor M4 is triggered to turn on. The first voltage signal NVDD1 is transmitted to the output terminal of the first exposure branch 11 through the third transistor M3 and the fourth transistor M4. The first voltage signal NVDD1 is the low-level power supply for the unselected row, and the first voltage signal NVDD1 controls the exposure of the pixel unit 210 in the nth row. At this time, the second exposure branch 21 and the second readout branch 22 of the second drive unit 112 do not receive the second pre-exposure address digital signal sp_add_n+1 and the second readout address digital signal rp_add_n+1, and the second drive unit 112 outputs a high potential.

[0079] When the exposure of pixel unit 210 in row n ends and the selected period begins, the fifth transistor M5 of the first readout branch 12 receives the opposite level signal rp_add_n of the first readout address digital signal rp_add_n, triggering the fifth transistor M5 to turn off. The eighth transistor M8 receives the first readout address digital signal rp_add_n, triggering the eighth transistor M8 to turn on. At the same time, the sixth transistor M6 and the seventh transistor M7 receive the first readout transmission digital signal rp_txb_n with a high-level pulse, triggering the sixth transistor M6 to turn off and the seventh transistor M7 to turn on. The second voltage signal NVDD2 is transmitted to pixel unit 210 in row n through the eighth transistor M8 and the seventh transistor M7. The second voltage signal NVDD2 acts as the gate control signal tx to control the readout exposure signal of pixel unit 210 in row n and transmits it to the output line.

[0080] Meanwhile, the eighteenth transistor M18 of the second switch branch 23 receives the first read address digital signal rp_add_n, triggering the eighteenth transistor M18 to conduct. The second voltage signal NVDD2 is output to the pixel unit 210 of the (n+1)th row through the eighteenth transistor M18. The second voltage signal NVDD2 provides low-level power supply for the selected row, with low voltage noise. Therefore, it can reduce the impact of noise coupling on the nth row and improve the quantization effect.

[0081] Then, when exposing the (n+1)th row, during the exposure period of pixel unit 210 in the (n+1)th row, the tenth transistor M10 of the second exposure branch 21 receives the opposite level signal sp_addb_n+1 of the second pre-exposure address digital signal sp_add_n+1, and the tenth transistor M10 is turned off. The pre-exposure transmission digital signal sp_txb is a high-level pulse signal. The eleventh transistor M11 and the twelfth transistor M12 receive the high-level pulse of the second pre-exposure transmission digital signal sp_txb_n+1, and the eleventh transistor M11 is triggered to turn off, the twelfth transistor M12 is triggered to turn on, and the thirteenth transistor M13 receives the high-level second pre-exposure address digital signal sp_add_n+1, and the thirteenth transistor M13 is triggered to turn on. The first voltage signal NVDD1 is transmitted to the output terminal of the second exposure branch 21 through the thirteenth transistor M13 and the twelfth transistor M12. The first voltage signal NVDD1 provides low-level power supply for the unselected row and controls the exposure of pixel unit 210 in the nth row. At this time, the first exposure branch 11 and the first readout branch 12 of the first driving unit 111 do not receive the first pre-exposure address digital signal sp_add_n and the first readout address digital signal rp_add_n, and the first driving unit 111 outputs a high potential.

[0082] When the exposure of pixel unit 210 in row n+1 ends and the selected period begins, the fourteenth transistor M14 of the second readout branch 22 receives the opposite level signal rp_addb_n+1 of the second readout address digital signal rp_add_n+1, triggering its turn-off. The seventeenth transistor M17 receives the second readout address digital signal rp_add_n+1, triggering its turn-on. Simultaneously, the fifteenth transistor M15 and the sixteenth transistor M16 receive the high-level pulse of the second readout transmission digital signal rp_txb_n+1, triggering their turn-off and turn-on. The second voltage signal NVDD2 is transmitted to pixel unit 210 in row n+1 through transistors M17 and M16. The second voltage signal NVDD2 acts as the gate control signal tx to control the readout exposure signal of pixel unit 210 in row n+1 and transmits it to the output line.

[0083] Meanwhile, the ninth transistor M9 of the first switch branch 13 receives the second read address digital signal rp_add_n+1, triggering the ninth transistor M9 to conduct. The second voltage signal NVDD2 is output to the pixel unit 210 of the nth row through the ninth transistor M9. The second voltage signal NVDD2 provides low-level power supply for the selected row, with low voltage noise. Therefore, it can reduce the impact of noise coupling on the (n+1)th row and improve the quantization effect.

[0084] Furthermore, when pixel unit 210 in row n is selected for quantization, pixel unit 210 in row n+1 receives the second voltage signal NVDD2. During the quantization process, the voltage is output symmetrically, which can avoid the quantization of pixel units 210 in adjacent rows from becoming misaligned, achieve quantization consistency, and improve the signal output quality.

[0085] In order to achieve signal output during non-selected periods, the first driving unit 111 and the second driving unit 112 switch to a high potential during their respective non-selected periods and control the corresponding row's pixel unit 210 to perform charge reset and zeroing. In an optional embodiment, such as... Figure 9 As shown, the first driving unit 111 is also used to output a third voltage signal TXVDD to the nth row pixel unit 210 to reset it during the non-selection period of the nth row pixel unit 210 and the (n+1)th row pixel unit 210, triggered by the first non-selection signal lat_addb_n.

[0086] The second driving unit 112 is also used to output a third voltage signal TXVDD to the n+1 row pixel unit 210 to reset it during the non-selection period of the n+1 row pixel unit 210 and the n+1 row pixel unit 210, triggered by the second non-selection signal lat_addb_n+1.

[0087] The pixel driving unit 110 also includes:

[0088] The non-selection signal generation circuit 113 is connected to the first driving unit 111 and the second driving unit 112 respectively. The non-selection signal generation circuit 113 is used to trigger the output of the first non-selection signal lat_addb_n or the second non-selection signal lat_addb_n+1 when the first readout control signal rp1 or the second readout control signal rp2 is received during the selection period of the nth row pixel unit 210 and the (n+1)th row pixel unit 210.

[0089] In this embodiment, the output time periods of the first non-selection signal lat_addb_n and the second non-selection signal lat_addb_n+1 can be determined by the first readout control signal rp1 or the second readout control signal rp2. During the selected time period of the pixel unit 210 in the nth row, the non-selection signal generation circuit 113 can receive the first readout control signal rp1. After the first readout control signal rp1 is output, the non-selection signal generation circuit 113 outputs the first non-selection signal lat_addb_n. At this time, the pixel unit 210 in the nth row enters the non-selection time period. The first non-selection signal lat_addb_n controls the first driving unit 111 to switch the output of the third voltage signal TXVDD and controls the pixel unit 210 in the nth row to perform charge reset and clearing.

[0090] During the selected period of pixel unit 210 in row n+1, the non-selection signal generation circuit 113 can receive the second readout control signal rp2. After the second readout control signal rp2 is output, the non-selection signal generation circuit 113 outputs the second non-selection signal lat_addb_n+1. At this time, pixel unit 210 in row n+1 enters the non-selection period. The second non-selection signal lat_addb_n+1 controls the second driving unit 112 to switch the output of the third voltage signal TXVDD and controls the pixel unit 210 in row n+1 to perform charge reset and clearing.

[0091] The non-selection signal generation circuit 113 can be a corresponding signal generator U1. In an optional embodiment, such as... Figure 16 As shown, the non-selection signal generation circuit 113 includes a signal generator U1, which can determine the output duration and output time of the first non-selection signal lat_addb_n and the second non-selection signal lat_addb_n+1 based on the received readout control signal.

[0092] Correspondingly, in order to achieve signal output for the corresponding non-selected time period, such as Figure 10 As shown, in an optional embodiment, the first driving unit 111 further includes:

[0093] The first non-selection branch 14 is connected to the positive power supply terminal, the first voltage terminal and the corresponding nth row pixel unit 210 respectively. When the first non-selection branch 14 receives the first non-selection signal lat_addb_n during the non-selection period of the nth row pixel unit 210 and the (n+1)th row pixel unit 210, it outputs the third voltage signal TXVDD, which is the voltage signal of the positive power supply terminal.

[0094] The second drive unit 112 also includes:

[0095] The second non-selection branch 24 is connected to the positive power supply terminal, the first voltage terminal and the corresponding n+1 row pixel unit 210 respectively. When the second non-selection branch 24 receives the second non-selection signal lat_addb_n+1 during the non-selection period of the n+1 row pixel unit 210 and the nth row pixel unit 210, the second non-selection branch 24 outputs the third voltage signal TXVDD.

[0096] In this embodiment, during the selected period of the pixel unit 210 in the nth row, the non-selection signal generation circuit 113 can receive the first readout control signal rp1. After the first readout control signal rp1 is output, the non-selection signal generation circuit 113 outputs the first non-selection signal lat_addb_n to the first non-selection branch 14. At this time, the pixel unit 210 in the nth row enters the non-selection period. The first non-selection signal lat_addb_n controls the first non-selection branch 14 to conduct the third voltage terminal and its own output terminal, and switches to output the third voltage signal TXVDD, and controls the pixel unit 210 in the nth row to perform charge reset and clearing.

[0097] During the selected period of pixel unit 210 in row n+1, the non-selection signal generation circuit 113 can receive the second readout control signal rp2. After the second readout control signal rp2 is output, the non-selection signal generation circuit 113 outputs the second non-selection signal lat_addb_n+1 to the second non-selection branch 24. At this time, pixel unit 210 in row n+1 enters the non-selection period. The second non-selection signal lat_addb_n+1 controls the second non-selection branch 24 to switch the output of the third voltage signal TXVDD and controls the pixel unit 210 in row n+1 to perform charge reset and clearing.

[0098] Among them, the first non-selected branch 14 and the second non-selected branch 24 can use a corresponding number and type of transistors, such as Figure 11As shown, in an optional embodiment, the first non-selectable branch 14 includes a nineteenth transistor M19, a twentieth transistor M20, a twenty-first transistor M21, a twenty-second transistor M22, a twenty-third transistor M23, a twenty-fourth transistor M24, and a twenty-fifth transistor M25 connected in series between the positive power supply terminal and the first voltage terminal.

[0099] The connection node of the twenty-first transistor M21 and the twenty-second transistor M22 forms the output terminal of the first non-selection branch 14. The control terminal of the nineteenth transistor M19 and the control terminal of the twenty-fifth transistor M25 are used to input the first non-selection signal lat_addb_n. The control terminal of the twentieth transistor M20 and the control terminal of the twenty-third transistor M23 are used to input the first readout address digital signal rp_add_n. The control terminal of the twenty-first transistor M21 and the control terminal of the twenty-fourth transistor M24 are used to input the second readout address digital signal rp_add_n+1. The control terminal of the twenty-second transistor M22 is used to input the first pre-exposure address digital signal sp_add_n.

[0100] When entering the non-selection period, after the first readout control signal rp1 is output, the non-selection signal generation circuit 113 outputs the first non-selection signal lat_addb_n to the first non-selection branch 14. At this time, the nineteenth transistor M19 and the twenty-fifth transistor M25 receive the first non-selection signal lat_addb_n. The nineteenth transistor M19 is triggered to turn on, and the twenty-fifth transistor M25 is triggered to turn off. At this time, the first readout address digital signal rp_add_n and the second readout address digital signal rp_add_n+1 are at a low level. The twentieth transistor M20 and the twenty-first transistor M21 are triggered to turn on, and the twenty-third transistor M23 and the twenty-fourth transistor M24 are triggered to turn off. The first pre-exposure address digital signal sp_add_n is at a low level, and the twenty-second transistor M22 is triggered to turn off. The third voltage signal TXVDD is output to the pixel unit 210 of the nth row through the nineteenth transistor M19, the twentieth transistor M20 and the twenty-first transistor M21, and controls the pixel unit 210 of the nth row to perform charge reset and clearing.

[0101] like Figure 12 As shown, in an optional embodiment, the second non-selectable branch 24 includes a 26th transistor M26, a 27th transistor M27, a 28th transistor M28, a 29th transistor M29, a 30th transistor M30, a 31st transistor M31, and a 32nd transistor M32 connected in series between the positive power supply terminal and the first voltage terminal.

[0102] The connection node of the twenty-eighth transistor M28 and the twenty-ninth transistor M29 forms the output terminal of the second non-selection branch 24. The control terminals of the twenty-sixth transistor M26 and the thirty-second transistor M32 are used to input the second non-selection signal lat_addb_n+1. The control terminals of the twenty-seventh transistor M27 and the thirtieth transistor M30 are used to input the second readout address digital signal rp_add_n+1. The control terminals of the twenty-eighth transistor M28 and the thirty-first transistor M31 are used to input the first readout address digital signal rp_add_n. The control terminal of the twenty-ninth transistor M29 is used to input the second pre-exposure address digital signal sp_add_n+1.

[0103] When entering the non-selection period, after the second readout control signal rp2 is output, the non-selection signal generation circuit 113 outputs the second non-selection signal lat_addb_n+1 to the second non-selection branch 24. At this time, the 26th transistor M26 and the 32nd transistor M32 receive the first non-selection signal lat_addb_n. The 26th transistor M26 is triggered to turn on, and the 32nd transistor M32 is triggered to turn off. At this time, the first readout address digital signal rp_add_n and the second readout address digital signal rp_add_n+1 are at a low level. The 27th transistor M27 and the 28th transistor M28 are triggered to turn on, and the 30th transistor M30 and the 31st transistor M31 are triggered to turn off. The second pre-exposure address digital signal sp_add_n+1 is at a low level, and the 29th transistor M29 is triggered to turn off. The third voltage signal TXVDD is output to the pixel unit 210 of the n+1th row through the 26th transistor M26, the 27th transistor M27 and the 28th transistor M28, and controls the pixel unit 210 of the n+1th row to perform charge reset and clearing.

[0104] In an optional embodiment, the non-select signal generation circuit 113 is further configured to determine the end time of the non-select signal during forward readout based on the readout period of the high-order second readout control signal rp2, i.e., it only takes effect at the end of the address in the nth and (n+1)th rows, such as... Figure 13 As shown, during the exposure period of pixel unit 210 in row n, when the non-selection signal generation circuit 113 receives the first exposure control signal sp1, it switches the first non-selection signal lat_addb_n from a low potential to a high potential during the non-selection period. The first non-selection branch 14 is turned off, and the first exposure branch 11 outputs the first voltage signal NVDD1. During the selected period, the non-selection signal generation circuit 113 can receive the first readout control signal rp1 and maintain the level state of the first non-selection signal lat_addb_n. After the first readout control signal rp1 is output, the non-selection signal generation circuit 113 maintains the level state of the first non-selection signal lat_addb_n.

[0105] During the exposure period of pixel unit 210 in row n+1, when the non-selection signal generation circuit 113 receives the second exposure control signal sp2, it switches the second non-selection signal lat_addb_n+1 from a low potential to a high potential during the non-selection period. The second non-selection branch 24 is turned off, and the second exposure branch 21 outputs the first voltage signal NVDD1. During the selected period, the non-selection signal generation circuit 113 can receive the second readout control signal rp2 and simultaneously switch the first non-selection signal lat_addb_n and the second non-selection signal lat_addb_n+1 to a low potential. The first non-selection signal lat_addb_n controls the first non-selection branch 14 to switch the output of the third voltage signal TXVDD and controls the pixel unit 210 in row n to perform charge reset and clearing. The second non-selection signal lat_addb_n+1 controls the second non-selection branch 24 to switch the output of the third voltage signal TXVDD and controls the pixel unit 210 in row n+1 to perform charge reset and clearing.

[0106] By making the non-select signal active only at the end of the address in the nth and n+1th rows, the pixel unit 210 in the nth row can be prevented from entering the non-select period prematurely when the pixel unit 210 in the n+1th row is read out, thus avoiding the output high potential instead of the second voltage signal NVDD2, thereby ensuring the consistency of the output voltage during the quantization process.

[0107] Furthermore, since pixel unit 210 can perform forward or reverse readout, when performing reverse readout, the (n+1)th row and the nth row are sequentially quantized. At this time, the non-select signal generation circuit 113, upon receiving the second readout control signal rp2 from pixel unit 210 in the (n+1)th row, prematurely controls the generation of the first non-select signal lat_addb_n, causing both non-select signals to be low. This results in the gate control signal tx output by the first driving unit 111 having... Figure 13 The signal glitches at the location indicated by the middle arrow, in order to eliminate signal glitches between adjacent rows, in an optional embodiment, such as... Figure 14 and Figure 15 As shown, the pixel driving unit 110 further includes:

[0108] The two-to-one switch circuit 114 has a first input terminal for inputting a second readout control signal rp2 and a second input terminal for inputting a first readout control signal rp1. The output terminal of the two-to-one switch circuit 114 is connected to the non-selection signal generation circuit 113. The two-to-one switch circuit 114 can output the second readout control signal rp2 when triggered by a positive readout signal, or output the first readout control signal rp1 when triggered by a reverse readout signal.

[0109] The non-selection signal generation circuit 113 is further configured to output the first non-selection signal lat_addb_n and the second non-selection signal lat_addb_n+1 when the first readout control signal rp1 is received, or to output the first non-selection signal lat_addb_n and the second non-selection signal lat_addb_n+1 when the second readout control signal rp2 is received.

[0110] In this embodiment, during forward readout, the two-to-one switch circuit 114 receives the forward readout signal and outputs the second readout control signal rp2. The second readout control signal rp2 is the high-order readout control signal during forward readout. The initial time point at which the first non-selective signal lat_addb_n and the second non-selective signal lat_addb_n+1 switch to a high level, i.e., the exit time point, is determined by the time point of their respective exposure control signals. The effective time point at which the first non-selective signal lat_addb_n and the second non-selective signal lat_addb_n+1 switch to a low potential is determined by the second readout control signal rp2. In the n+th... When the selected period is of pixel unit 210 in row 1, the non-selection signal generation circuit 113 can receive the second readout control signal rp2 and simultaneously switch the first non-selection signal lat_addb_n and the second non-selection signal lat_addb_n+1 to a low potential. The first non-selection signal lat_addb_n controls the first non-selection branch 14 to switch the output of the third voltage signal TXVDD and controls the pixel unit 210 in row n to perform charge reset and clearing. The second non-selection signal lat_addb_n+1 controls the second non-selection branch 24 to switch the output of the third voltage signal TXVDD and controls the pixel unit 210 in row n+1 to perform charge reset and clearing.

[0111] The non-select signal is only activated when the addresses of the nth and n+1th rows are finished. This avoids the pixel unit 210 of the nth row from entering the non-select period prematurely when the pixel unit 210 of the n+1th row is read out during quantization, resulting in a high output potential instead of the second voltage signal NVDD2. This ensures the consistency of the output voltage during quantization.

[0112] During reverse readout, the two-to-one switch circuit 114 receives the reverse readout signal and outputs the first readout control signal rp1. The first readout control signal rp1 is the high-order readout control signal during reverse readout. The initial and exit times when the first NOT signal lat_addb_n and the second NOT signal lat_addb_n+1 switch to a high level are determined by the timing of their respective exposure control signals. The effective time when the first NOT signal lat_addb_n and the second NOT signal lat_addb_n+1 switch to a low level is determined by the first readout control signal rp1. (In the nth row...) During the selected period of pixel unit 210, the non-selection signal generation circuit 113 can receive the first readout control signal rp1 and simultaneously switch the first non-selection signal lat_addb_n and the second non-selection signal lat_addb_n+1 to a low potential. The first non-selection signal lat_addb_n controls the first non-selection branch 14 to switch the output of the third voltage signal TXVDD and controls the pixel unit 210 in the nth row to perform charge reset and clearing. The second non-selection signal lat_addb_n+1 controls the second non-selection branch 24 to switch the output of the third voltage signal TXVDD and controls the pixel unit 210 in the n+1th row to perform charge reset and clearing.

[0113] By selecting different readout control signals to control the generation time of the non-selected signal in different readout directions, the gate control signal tx of the nth row and the gate control signal tx of the (n+1)th row can be kept smooth in different readout directions, eliminating the glitches in the gate control signal tx caused by the non-overlapping of addresses between adjacent rows, and improving signal quality.

[0114] The two-to-one switching circuit 114 can be selected from corresponding switching circuits. In one optional embodiment, such as... Figure 16 As shown, the 2-to-1 switch circuit 114 includes a 2-to-1 selector MUX. The first input terminal of the 2-to-1 selector MUX is used to input the second read address digital signal rp_add_n+1, the second input terminal of the 2-to-1 selector MUX is used to input the first read address digital signal rp_add_n, and the enable terminal of the 2-to-1 selector MUX is used to receive the positive read signal or the reverse read signal.

[0115] During forward readout, in the exposure period of the nth row, signal generator U1 receives the first pre-exposure address digital signal sp_add_n and the first pre-exposure transmission digital signal sp_txb_n. Signal generator U1 switches the first non-select signal lat_addb_n to a high potential, the first non-select branch 14 is turned off, and the first exposure branch 11 outputs the first voltage signal NVDD1. During the selected period, the 2-to-1 selector MUX outputs the second readout address digital signal rp_add_n+1. Signal generator U1 can receive the second readout address digital signal rp_add_n+1 and the first readout transmission digital signal rp_txb_n, and maintain the level state of the first non-select signal lat_addb_n. After the first readout transmission digital signal rp_txb_n is output, the non-select signal generation circuit 113 maintains the level state of the first non-select signal lat_addb_n.

[0116] During the exposure period of pixel unit 210 in row n+1, when signal generator U1 receives the second pre-exposure address digital signal sp_add_n+1 and the second pre-exposure transmission digital signal sp_txb_n+1, it switches the second non-select signal lat_addb_n+1 from a low potential during the non-selection period to a high potential, the second non-selection branch 24 is turned off, and the second exposure branch 21 outputs the first voltage signal NVDD1. During the selected period, the 2-to-1 selector MUX outputs the second readout address digital signal rp_add_n+1, and signal generator U1 can receive the second readout control signal r. p2 and the second readout transmission digital signal rp_txb_n+1, and simultaneously switch the first non-select signal lat_addb_n and the second non-select signal lat_addb_n+1 to a low potential. The first non-select signal lat_addb_n controls the first non-select branch 14 to switch the output of the third voltage signal TXVDD, and controls the pixel unit 210 in the nth row to perform charge reset and clearing. The second non-select signal lat_addb_n+1 controls the second non-select branch 24 to switch the output of the third voltage signal TXVDD, and controls the pixel unit 210 in the (n+1)th row to perform charge reset and clearing.

[0117] The beneficial effects of this utility model embodiment compared with the prior art are as follows: The pixel driving circuit 100 mentioned above includes a plurality of pixel driving units 110, and the pixel driving unit 110 includes at least a first driving unit 111 and a second driving unit 112. When quantizing and reading out the pixel unit 210 of the nth row, the first driving unit 111 outputs a first pulse signal based on the first readout control signal rp1 to control the readout of the pixel unit 210 of the nth row. At the same time, the second driving unit 112 connected to the pixel unit 210 of the (n+1)th row outputs a second voltage signal NVDD2 based on the first readout control signal rp1. When quantizing and reading out the pixel unit 210 of the (n+1)th row, the second driving unit 112 outputs a second pulse signal based on the second readout control signal rp2 to control the readout of the pixel unit 210 of the (n+1)th row. At the same time, the first driving unit 111 connected to the pixel unit 210 of the nth row outputs a second voltage signal NVDD2 based on the second readout control signal rp2. The voltages output before and after quantization are symmetrical and have no noise influence, which improves the quantization effect and image display effect.

[0118] This utility model also proposes an image sensor, such as Figure 3 As shown, the image sensor includes a pixel circuit 200 and a pixel driving circuit 100. The specific structure of the pixel driving circuit 100 is as described in the above embodiments. Since this image sensor adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be described in detail here. The pixel driving circuit 100 is connected to the pixel circuit 200. The pixel circuit 200 includes a plurality of pixel units 210 arranged in an array. The pixel units 210 in the same column are connected to the same output line Lp. The pixel driving circuit 100 is used to output multiple gate control signals tx to the pixel circuit 200, thereby selecting the pixel unit 210 at the corresponding position for exposure and readout, and readout to the image sensor processing circuit through the output line Lp. The processing circuit determines the image information based on the readout signal.

[0119] Among them, the multiple rows of pixel units 210 connected to the pixel driving unit 110, the multiple pixel units 210 in adjacent rows of the same column adopt a shared connection structure, as in an optional embodiment, such as Figure 17 As shown, the pixel circuit 200 also includes:

[0120] Several reset circuits 220 are provided, each reset circuit 220 being connected to the floating diffusion node FD of multiple pixel units 210 in the same column. The reset circuit 220 is used to receive reset signals and reset multiple pixel units 210.

[0121] The floating diffusion nodes FD of multiple pixel units 210 are connected to the same reset circuit 220 and are reset through the reset circuit 220 during non-selected periods, thereby continuously clearing the charge in the pixel unit 210 before exposure, preventing charge leakage and reducing the charge coupling effect between adjacent pixel rows.

[0122] Pixel unit 210 may employ corresponding photosensitive elements such as PD and transistors. In an optional embodiment, such as... Figure 17 As shown,

[0123] Each pixel unit 210 includes at least a photosensitive element PD, a transmission transistor TX, and a follower transistor SF connected in sequence, with the second end of the transmission transistor TX connected to the floating diffusion node FD.

[0124] The photosensitive element PD is used to convert the received light signal into an exposure signal. The transmission transistor TX is used to receive the gate control signal tx and turn it on or off accordingly, and transmit the exposure signal to the floating diffusion node FD. The exposure signal can be transmitted to the output line Lp through the follower transistor SF.

[0125] In this process, the gate control signal tx is the first voltage signal NVDD1 during the exposure period, and controls the transmission transistor TX and the photosensitive element PD to perform exposure. During the selected period, it switches to a pulse signal, controls the transmission transistor TX to turn on and transmits the exposure signal to the follower transistor SF. During the non-selected period, the gate control signal tx switches to the third voltage signal TXVDD, and controls the transmission transistor TX to remain on. The reset circuit 220 remains on and continuously clears the charge of the floating diffusion nodes FD of each connected pixel unit 210, reducing the charge coupling effect between adjacent row pixel units 210.

[0126] The reset circuit 220 includes multiple transistors. During the non-selection period, the reset circuit 220 receives a reset signal and is triggered to turn on. At the same time, the transmission transistor tx receives a non-selection signal and is triggered to turn on. The reset terminal of the reset circuit 220 forms a path with the photosensitive element PD and clears the charge of the photosensitive element PD, reducing the charge coupling effect between adjacent row pixel units 210.

[0127] The above-described embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model, and should all be included within the protection scope of this utility model.

Claims

1. A pixel driving circuit for outputting multiple gate control signals to a pixel circuit, characterized in that, The pixel driving circuit includes multiple pixel driving units. Each pixel driving unit transmits gate control signals to at least two adjacent rows of pixel units in the pixel circuit to control the turning on and off of the transmission transistors in the pixel units. Each pixel driving unit includes at least the following: A first driving unit is connected to the nth row of pixel units. During the exposure period of the nth row of pixel units, the first driving unit is triggered by a first exposure control signal to output a first voltage signal to control the exposure of the nth row of pixel units. During the selection period of the nth row of pixel units, the first driving unit is triggered by a first readout control signal to output a first pulse signal to the nth row of pixel units to read them out. During the selection period of the (n+1)th row of pixel units, the first driving unit outputs a second voltage signal to the nth row of pixel units based on a second readout control signal. The second driving unit is connected to the (n+1)th row of pixel units. During the exposure period of the (n+1)th row of pixel units, the second driving unit is triggered by a second exposure control signal to output a first voltage signal to control the exposure of the (n+1)th row of pixel units. During the selection period of the (n+1)th row of pixel units, the second driving unit is triggered by a second readout control signal to output a second pulse signal to the (n+1)th row of pixel units to enable readout. During the selection period of the (n)th row of pixel units, the second driving unit outputs a second voltage signal to the (n+1)th row of pixel units based on the first readout control signal.

2. The pixel driving circuit as described in claim 1, characterized in that, The first driving unit includes: The first exposure branch is connected to the positive power supply terminal, the first voltage terminal and the nth row pixel unit respectively. The first voltage terminal is used to input the first voltage signal. The first exposure branch is used to output the first voltage signal when triggered by the first exposure control signal during the exposure period of the nth row pixel unit. The first readout branch is connected to the positive power supply terminal, the second voltage terminal and the nth row pixel unit respectively. The second voltage terminal is used to input the second voltage signal. The first readout branch is used to output a first pulse signal to the nth row pixel unit to read it out when triggered by the first readout control signal during the selected period of the nth row pixel unit. The first switch branch is connected to the second voltage terminal and the nth row pixel unit respectively. The first switch branch is used to output a second voltage signal to the nth row pixel unit based on the second readout control signal during the selected period of the (n+1)th row pixel unit.

3. The pixel driving circuit as described in claim 2, characterized in that, The first exposure control signal includes a first pre-exposure address digital signal and a first pre-exposure transmission digital signal; The first exposure branch includes a first transistor, a second transistor, a third transistor, and a fourth transistor connected in series with the positive power supply terminal and the first voltage terminal. The connection node of the second transistor and the third transistor constitutes the output terminal of the first exposure branch. The control terminal of the first transistor and the control terminal of the fourth transistor are used to input the first pre-exposure address digital signal, and the control terminal of the second transistor and the control terminal of the third transistor are used to input the first pre-exposure transmission digital signal.

4. The pixel driving circuit as described in claim 3, characterized in that, The first readout control signal includes a first readout address digital signal and a first readout transmission digital signal; The first readout branch includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor connected in series with the positive power supply terminal and the second voltage terminal. The connection node of the sixth transistor and the seventh transistor constitutes the output terminal of the first exposure branch. The control terminals of the fifth transistor and the eighth transistor are used to input the first readout address digital signal, and the control terminals of the sixth transistor and the seventh transistor are used to input the first readout transmission digital signal.

5. The pixel driving circuit as described in claim 3, characterized in that, The second readout control signal includes a second readout address digital signal and a second readout transmission digital signal; The first switching branch includes a ninth transistor; The first terminal of the ninth transistor forms the output terminal of the first switch branch, the second terminal of the ninth transistor is connected to the second voltage terminal, and the control terminal of the ninth transistor is used to input the second read address digital signal.

6. The pixel driving circuit as described in claim 1, characterized in that, The second drive unit includes: The second exposure branch is connected to the positive power supply terminal, the first voltage terminal and the n+1th row pixel unit respectively. The first voltage terminal is used to input the first voltage signal. The second exposure branch is used to output the first voltage signal when triggered by the second exposure control signal during the exposure period of the n+1th row pixel unit. The second readout branch is connected to the positive power supply terminal, the second voltage terminal and the n+1th row pixel unit respectively. The second voltage terminal is used to input the second voltage signal. The second readout branch is used to output a second pulse signal to the n+1th row pixel unit to read it out when triggered by the second readout control signal during the selected period of the n+1th row pixel unit. The second switch branch is connected to the second voltage terminal and the (n+1)th row pixel unit respectively. The second switch branch is used to output a second voltage signal to the (n+1)th row pixel unit based on the first readout control signal during the selected period of the nth row pixel unit.

7. The pixel driving circuit as described in claim 6, characterized in that, The second exposure control signal includes a second pre-exposure address digital signal and a second pre-exposure transmission digital signal; The second exposure branch includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor connected in series with the positive power supply terminal and the first voltage terminal. The connection node of the eleventh transistor and the twelfth transistor constitutes the output terminal of the second exposure branch. The control terminals of the tenth transistor and the thirteenth transistor are used to input the second pre-exposure address digital signal, and the control terminals of the eleventh transistor and the twelfth transistor are used to input the second pre-exposure transmission digital signal.

8. The pixel driving circuit as described in claim 7, characterized in that, The second readout control signal includes a second readout address digital signal and a second readout transmission digital signal; The second readout branch includes a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor connected in series with the positive power supply terminal and the second voltage terminal. The connection node of the fifteenth transistor and the sixteenth transistor constitutes the output terminal of the second exposure branch. The control terminals of the fourteenth transistor and the seventeenth transistor are used to input the second readout address digital signal, and the control terminals of the fifteenth transistor and the sixteenth transistor are used to input the second readout transmission digital signal.

9. The pixel driving circuit as described in claim 6, characterized in that, The first readout control signal includes a first readout address digital signal and a first readout transmission digital signal; The second switching branch includes the eighteenth transistor; The first terminal of the eighteenth transistor forms the output terminal of the second switch branch, the second terminal of the eighteenth transistor is connected to the second voltage terminal, and the control terminal of the eighteenth transistor is used to input the first read address digital signal.

10. The pixel driving circuit according to any one of claims 1 to 9, characterized in that, The first driving unit is further configured to, during the non-selection period of the nth row pixel unit and the (n+1)th row pixel unit, output a third voltage signal to the nth row pixel unit to reset it, triggered by the first non-selection signal. The second driving unit is further configured to output a third voltage signal to the (n+1)th row pixel unit to reset it during the non-selection period of the (n+1)th row pixel unit and the nth row pixel unit, triggered by the second non-selection signal. The pixel driving unit further includes: The non-selection signal generation circuit is connected to the first driving unit and the second driving unit respectively. The non-selection signal generation circuit is used to trigger the output of the first non-selection signal or the second non-selection signal when the first readout control signal or the second readout control signal is received during the selection period of the nth row pixel unit and the (n+1)th row pixel unit.

11. The pixel driving circuit as described in claim 10, characterized in that, The first driving unit further includes: The first non-selection branch is connected to the positive power supply terminal, the first voltage terminal and the corresponding nth row pixel unit respectively. When the first non-selection branch receives the first non-selection signal during the non-selection period of the nth row pixel unit and the (n+1)th row pixel unit, the first non-selection branch outputs the third voltage signal, which is the voltage signal of the positive power supply terminal. The second drive unit further includes: The second non-selection branch is connected to the positive power supply terminal, the first voltage terminal, and the corresponding n+1 row pixel unit, respectively. When the second non-selection branch receives the second non-selection signal during the non-selection period of the n+1 row pixel unit and the nth row pixel unit, the second non-selection branch outputs the third voltage signal.

12. The pixel driving circuit as described in claim 11, characterized in that, The first exposure control signal includes a first pre-exposure address digital signal and a first pre-exposure transmission digital signal; The second exposure control signal includes a second pre-exposure address digital signal and a second pre-exposure transmission digital signal; The first readout control signal includes a first readout address digital signal and a first readout transmission digital signal; The second readout control signal includes a second readout address digital signal and a second readout transmission digital signal; The first non-selective branch includes the nineteenth transistor, the twentieth transistor, the twenty-first transistor, the twenty-second transistor, the twenty-third transistor, the twenty-fourth transistor, and the twenty-fifth transistor, which are connected in series between the positive power supply terminal and the first voltage terminal. The connection node of the 21st transistor and the 22nd transistor constitutes the output terminal of the first non-selection branch. The control terminals of the 19th transistor and the 25th transistor are used to input the first non-selection signal. The control terminals of the 20th transistor and the 23rd transistor are used to input the first readout address digital signal. The control terminals of the 21st transistor and the 24th transistor are used to input the second readout address digital signal. The control terminal of the 22nd transistor is used to input the first pre-exposure address digital signal.

13. The pixel driving circuit as described in claim 12, characterized in that, The second non-selective branch includes the 26th transistor, the 27th transistor, the 28th transistor, the 29th transistor, the 30th transistor, the 31st transistor, and the 32nd transistor, which are connected in series between the positive power supply terminal and the first voltage terminal. The connection node of the 28th and 29th transistors constitutes the output terminal of the second non-select branch. The control terminals of the 26th and 32nd transistors are used to input the second non-select signal. The control terminals of the 27th and 30th transistors are used to input the second readout address digital signal. The control terminals of the 28th and 31st transistors are used to input the first readout address digital signal. The control terminal of the 29th transistor is used to input the second pre-exposure address digital signal.

14. The pixel driving circuit as described in claim 10, characterized in that, The pixel driving unit further includes: A two-to-one switch circuit, wherein the first input terminal of the two-to-one switch circuit is used to input the second readout control signal, the second input terminal of the two-to-one switch circuit is used to input the first readout control signal, and the output terminal of the two-to-one switch circuit is connected to the non-selection signal generation circuit. The two-to-one switch circuit can output the second readout control signal when triggered by a positive readout signal, or output the first readout control signal when triggered by a reverse readout signal. The non-selection signal generation circuit is further configured to output the first non-selection signal and the second non-selection signal when the first readout control signal is received, or to output the first non-selection signal and the second non-selection signal when the second readout control signal is received.

15. An image sensor, characterized in that, It includes a pixel circuit and a pixel driving circuit as described in any one of claims 1 to 14, wherein the pixel driving circuit is connected to the pixel circuit, and the pixel circuit includes a plurality of pixel units arranged in an array; The pixel circuit also includes: Several reset circuits are provided, each reset circuit being connected to the floating diffusion nodes of multiple pixel units in the same column. The reset circuit is used to receive a reset signal to reset multiple pixel units. Each pixel unit includes at least a photosensitive element, a transmission transistor, and a follower transistor connected in sequence, with the second end of the transmission transistor connected to a floating diffusion node.

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