Packaging body and lead frame

Abstract

The utility model provides a packaging body and a lead frame. The packaging body comprises a chip packaging structure; the first lead frame comprises a plurality of first pins, and the first ends of the plurality of first pins are respectively connected to the chip packaging structure; and the first packaging body is configured to package the chip packaging structure and the first end of the first pin therein. According to the packaging body, the packaging type of the chip body can be replaced according to the change of the application scene of the terminal, and the flexibility is high.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor packaging technology, and in particular to a package and lead frame. Background Technology

[0002] In the semiconductor industry, chips are packaged into different types to suit different end-user applications. However, for pre-packaged chips, their packaging form cannot currently be changed to adapt to changes in end-user applications, resulting in a lack of flexibility. Utility Model Content

[0003] The package and lead frame provided in this application are intended to solve the problem that chip packages cannot change their packaging form to cope with changes in end application scenarios and lack flexibility.

[0004] To solve the above-mentioned technical problems, one technical solution adopted in this application is: to provide a package, the package including a chip package structure, a first lead frame and a first package body; the first lead frame includes a plurality of first pins, the first ends of the plurality of first pins being respectively connected to the chip package structure; the first package body is configured to encapsulate the chip package structure and the first ends of the first pins therein.

[0005] In one embodiment of this application, a plurality of first pins are arranged around a first carrier area, and the first ends of the first pins are detachably disposed in the first carrier area to carry the chip package structure; the second ends of the first pins are located away from the first carrier area along a first direction; wherein, the first direction intersects the height direction of the chip package structure.

[0006] In one embodiment of this application, the first end of the first pin has a first surface and a second surface that are opposite to each other.

[0007] The first package is further configured to encapsulate a first surface and a second surface of a first end of the first pin therein; the chip package structure is placed on the first surface of the first end of the first pin within the first carrier region.

[0008] In one embodiment of this application, the chip packaging structure includes:

[0009] The second lead frame has a first surface and a second surface that are opposite to each other;

[0010] The chip body is disposed on the first surface of the second lead frame and is electrically connected to the second lead frame;

[0011] The second package is configured to encapsulate at least a portion of the second lead frame and the chip body therein.

[0012] In one embodiment of this application, the second lead frame includes:

[0013] Support disk; the chip body is supported on the first surface of the support disk;

[0014] The chip body has multiple second pins, and the multiple second pins are electrically connected to each other.

[0015] In one embodiment of this application, the first pin and the second pin are detachably electrically connected.

[0016] In one embodiment of this application, any one or more of the first surface of the first end of the first pin, the second surface of the second pin, and the second surface of the support disk have a concave-convex structure.

[0017] In one embodiment of this application, the first pin is soldered to the second surface of the second pin.

[0018] In one embodiment of this application, the first pin is recessed toward the side where the chip package structure is located, and a U-shaped groove is defined therein.

[0019] In one embodiment of this application, the first lead frame is composed of a plurality of mutually independent first pins; or

[0020] The first lead frame also includes an insulating connector, through which at least a portion of the first pins are connected together.

[0021] To solve the above-mentioned technical problems, another technical solution adopted in this application is to provide a lead frame, which includes a plurality of first pins, each first pin including a first segment and a second segment; the end of the first segment opposite to the second segment is a tip and is configured to connect to a chip package structure.

[0022] To solve the above-mentioned technical problems, another technical solution adopted in this application is: to provide a lead frame, the lead frame including: a plurality of first pins, the first ends of the plurality of first pins being respectively configured to connect to a chip package structure; an insulating connector, at least a portion of the plurality of first pins being connected together through the insulating connector.

[0023] The beneficial effects of the embodiments of this application, which differ from the prior art, are as follows: The package provided in the embodiments of this application includes a chip package structure, a first lead frame, and a first package body. The first lead frame includes a plurality of first pins, and the first ends of the plurality of first pins are respectively connected to the chip package structure. The first package body is configured to encapsulate the chip package structure and the first ends of the first pins within it. By connecting a plurality of first pins to the chip package structure and encapsulating the chip package structure and the first ends of the first pins within it, the package body can convert the packaged chip package structure into another package type. Simultaneously, the package body can also be separated from the chip package structure along with the plurality of first pins according to changes in the terminal application scenario, so that the expanded package body can be converted back into the package type of the chip package structure, thereby allowing the chip package structure to be applied to another terminal scenario, effectively increasing the flexibility of the package body. Attached Figure Description

[0024] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiments below. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0025] Figure 1 A cross-sectional view of a package provided in an embodiment of this application;

[0026] Figure 2 A schematic diagram of one side of the second surface of the second lead frame of the chip packaging structure provided in an embodiment of this application;

[0027] Figure 3 A schematic diagram of a chip packaging structure with a groove formed on the second lead frame, as provided in an embodiment of this application;

[0028] Figure 4 The first pin provided in one embodiment of this application and Figure 3 The diagram shows the connected chip package structure.

[0029] Figure 5 A schematic diagram showing the arrangement of a plurality of first pins according to an embodiment of this application;

[0030] Figure 6 This is a schematic diagram showing the arrangement of a plurality of first pins according to another embodiment of this application.

[0031] Explanation of reference numerals in the attached figures

[0032] 10 Package body; 1 Chip package structure; 11 Second lead frame; 111 Groove; 112 Second pin; 12 Chip body; 13 Second package body; 14 Lead; 2 First lead frame; 20 First carrier area; 21 First pin; 21a First segment; 21b Second segment; 211 U-groove; 22 Insulating connector; 3 First package body. Detailed Implementation

[0033] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0034] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0035] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0036] In related technologies, common packaging types include SOP (Small Outline Package), QFP (Quad Flat Package), QFN (Quad Flat No-lead Package), and SON (Small Outline No-leads Package). In specific application scenarios, different package types can be selected based on the specific end-user application. However, for pre-packaged chips, their packaging form cannot currently be changed to adapt to changes in end-user application scenarios, lacking flexibility.

[0037] Therefore, this application provides a package that can extend a SON / QFN series package to a SOP / QFP series package, or convert a packaged SOP / QFP series package back to a SON / QFN series package, in order to cope with changes in end application scenarios and effectively increase the flexibility of the package.

[0038] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0039] Please see Figure 1 , Figure 1 This is a cross-sectional view of a package provided in an embodiment of this application; in this embodiment, a package 10 is provided, which includes a chip package structure 1, a first lead frame 2 and a first package 3.

[0040] Among them, see Figure 1 and Figure 2 , Figure 2 This is a schematic diagram of one side of the chip packaging structure provided in an embodiment of this application, showing the second surface of the second lead frame. The chip packaging structure 1 includes a second lead frame 11, a chip body 12, and a second package body 13. The second lead frame 11 has a first surface and a second surface facing away from each other. In some embodiments, the second lead frame 11 can be implemented using any one of an aluminum substrate, an aluminum alloy substrate, a copper-aluminum substrate, or a copper alloy substrate. The second lead frame 11 serves as a mounting carrier for the chip body 12. The shape of the second lead frame 11 can be determined according to the specific location, number, and size of the chip body 12, and can be square, but is not limited to square.

[0041] The second lead frame 11 includes a support pad and a plurality of second pins 112. In some embodiments, the second pins 112 are solder pads. The chip body 12 is supported on a first surface of the support pad. In some embodiments, the first surface of the support pad may be provided with an uneven structure. Figure 3 This increases the contact area between the support disk and the second package 13, reducing the risk of delamination between the support disk and the second package 13.

[0042] Multiple second pins 112 may be distributed around the outer periphery of the support disk. The chip body 12 is electrically connected to the first surfaces of the multiple second pins 112. The chip body 12 may be a surface-mount electronic component or a die (bare die, such as a die cut from a wafer).

[0043] In some embodiments, the second surface of the second pin 112 may be provided with a concave-convex structure to increase the contact area between the first pin 21 of the first lead frame 2 and the second pin 112 or the connection structure of the second pin 112 (not shown), thereby improving the reliability of the electrical connection between the first pin 21 and the second pin 112.

[0044] In one embodiment, see Figure 3 and Figure 4 , Figure 3 A schematic diagram of a chip packaging structure with a groove formed on the second lead frame, as provided in an embodiment of this application; Figure 4 The first pin provided in one embodiment of this application and Figure 3 The diagram shows the connected chip package structure. The second surface of the second lead frame 11 may have a groove 111, which extends along the first direction X to the edge of the second lead frame 11. The first end of the first pin 21 extends into the groove 111 and is engaged with the second lead frame 11 through the groove 111, thereby achieving the connection between the first pin 21 and the second lead frame 11. In this embodiment, by providing the groove 111 on the second surface of the second lead frame 11, the connection between the second lead frame 11 and the first lead frame 2 can be made tighter.

[0045] In some embodiments, by extending the first pin 21 into the groove 111 to connect with the chip package structure 1, the overall thickness of the package 10 can be reduced compared to the scheme in which the first pin 21 is directly connected to the second surface of the second lead frame 11. At the same time, the groove wall of the groove 111 can limit the relative position between the first end of the first pin 21 and the chip package structure 1, thereby reducing the risk that the first pin 21 may be displaced and unable to be effectively electrically connected to the chip package structure 1.

[0046] The number of grooves 111 can be the same as the number of first pins 21, with one first pin 21 corresponding to one groove 111.

[0047] Of course, in other embodiments, while the first pin 21 is snapped into the second lead frame 11 by the groove 111, the first pin 21 can be further soldered to the second pin 112 on the second lead frame 11 to further improve the reliability of the electrical connection between the first pin 21 and the second pin 112.

[0048] Alternatively, the second surface of the second lead frame 11 may not have a groove 111, and the first pin 21 may be directly soldered to the second pin 112 on the second lead frame 11. When the first pin 21 and the second pin 112 are connected by soldering, if it is necessary to separate the first pin 21 from the chip package structure 1, the separation can be achieved through a desoldering process.

[0049] As an example, such as Figure 3 As shown, the chip body 12 is mounted face-up on the support pad of the second lead frame 11, meaning the front of the chip body 12 faces away from the second lead frame 11. In this example, the chip package structure 1 also includes a lead 14, one end of which is electrically connected to the chip body 12, and the other end is electrically connected to the first surface of the second pin 112 or a connection structure (not shown) to the second pin 112. The lead 14 can be connected to the chip body 12 and the second pin 112 respectively using solder, conductive adhesive, etc.

[0050] The lead wire 14 can be made of gold, silver, copper or aluminum.

[0051] As another example, the chip body 12 is flip-chip mounted on the second lead frame 11, meaning the front side of the chip body 12 faces the second lead frame 11. In this example, the pads on the front side of the chip body 12 are electrically connected to the second lead frame 11.

[0052] The second package 13 is configured to encapsulate the second lead frame 11 and the chip body 12 therein, for protecting the chip body 12 and the second lead frame 11. Where the chip package structure 1 also includes leads 14, the second package 13 further encapsulates the leads 14 therein. The material of the second package 13 may include epoxy resin.

[0053] Combination Figure 1 and Figure 5 , Figure 5 This is a schematic diagram illustrating the arrangement of multiple first pins 21 according to an embodiment of this application. The first lead frame 2 includes multiple first pins 21, each having a first end and a second end; the first ends of the multiple first pins 21 are detachably connected to the chip package structure 1. In this way, the package body 10 can detach the first pins 21 from the chip package structure 1 according to changes in the application scenario of the terminal, thereby changing the package type of the chip body 12 and adapting to different terminal application scenarios, offering high flexibility.

[0054] In some embodiments, combined with Figure 5The first pin 21 includes a first segment 21a and a second segment 21b. The end of the first segment 21a facing away from the second segment 21b is the first end of the first pin 21. The first end of the first pin 21 is a pointed tip to facilitate the engagement of the first pin 21 with the groove 111 and the second pin 112. The second segment 21b of the first pin 21 can be a long strip of equal width.

[0055] In some embodiments, the first segment 21a and the second segment 21b of the first pin 21 are inclined at a preset angle; this facilitates the connection of the first segment 21a of the first pin 21 to the smaller second lead frame 11, and the spacing between the second segments 21b of two adjacent first pins 21 is not too small, reducing the risk of short circuit. The preset angle can be 120°, 130°, 140°, 150°, 160°, etc.

[0056] The second end of the first pin 21 is configured to be electrically connected to the circuit board. Specifically, the second end of the first pin 21 can be electrically connected to the circuit board using a conductive material.

[0057] In some embodiments, combined with Figure 5 Multiple first pins 21 are arranged around the first carrier region 20, for example, in an array, such as two columns and multiple rows. The first ends of the first pins 21 are respectively disposed in the first carrier region 20 to carry and electrically connect to the chip package structure 1. The multiple first pins 21 surrounding the first carrier region 20 can be either a complete circle of the first carrier region 20 along its circumferential direction, or a portion of the multiple first pins 21 surrounding the first carrier region 20 along its circumferential direction.

[0058] Combination Figure 4 The second end of the first pin 21 is located away from the first carrier region 20 along the first direction X. The first direction X intersects the height direction Y of the chip package structure 1. The angle between the first direction X and the height direction Y of the chip package structure 1 can be less than 60° and less than or equal to 90°. As an example, this angle can be 70°, 80°, or 90°.

[0059] In some embodiments, the first pin 21 may be a conductive sheet, i.e., the first pin 21 is sheet-shaped. The sheet-shaped first pin 21 has a first surface and a second surface facing away from each other at its first end. The chip package structure 1 is placed on the first surface of the first end of the first pin 21 within the first carrier area 20; that is, the first surface of the first end of the first pin 21 faces the chip package structure 1 and is in contact with and electrically connected to the second pin 112 of the chip package structure 1.

[0060] In some embodiments, the first surface of the first pin 21 may also be provided with a concave-convex structure to further increase the contact area between the first pin 21 and the second pin 112 or the connection structure of the second pin 112 (not shown), thereby further improving the connection reliability between the first pin 21 and the second pin 112.

[0061] By making the first pin 21 a conductive sheet, the contact area between the first end of the first pin 21 and the chip package structure 1, as well as the contact area between the second end of the first pin 21 and the circuit board, can be increased, thereby increasing the connection reliability.

[0062] The shape of the first pin 21 can be formed according to the specific package to be extended. In some embodiments, combined with Figure 1 The first pin 21 is recessed towards the side where the chip package structure 1 is located, forming a U-shaped groove 211. That is, the first end and the second end of the first pin 21 are located on the same side of the chip package structure 1; the portion between the first end and the second end of the first pin 21 is recessed towards the side where the chip package structure 1 is located; it can also be understood that the first end of the first pin 21 is bent downwards. This bent first pin 21 can increase the support capacity of the first pin 21 for the chip package structure 1; at the same time, after the chip package structure 1 is placed on the first pin 21, the overall thickness of the package 10 can be reduced, which is beneficial for the thinning and lightening of the package 10.

[0063] Wherein, along the height direction Y of the chip package structure 1, the first end of the first pin 21 is higher than the second end of the first pin 21.

[0064] In some embodiments, such as Figure 5 As shown, the first lead frame 2 is composed of multiple independent first pins 21; thus, the structure of the first lead frame 2 is relatively simple, and when it is necessary to convert the package type of the package 10 into the chip package structure 1, it is easier to separate the first lead frame 2, which facilitates the rapid conversion of the package type.

[0065] Of course, in some other embodiments, see Figure 6 , Figure 6 This is a schematic diagram illustrating the arrangement of multiple first pins according to another embodiment of this application. The first lead frame 2 further includes an insulating connector 22, through which at least a portion of the multiple first pins 21 are connected together. This facilitates the storage of the multiple first pins 21 before or after they are connected to the chip package structure 1, preventing them from being easily lost. The insulating connector 22 may be made of epoxy resin.

[0066] Please return to the reference. Figure 1The first package 3 is configured to encapsulate at least a portion of the first end of the chip package structure 1 and the first pin 21 within it. The material of the first package 3 may be the same as that of the second package 13. By further configuring the first package 3, the package 10 can provide dual encapsulation protection for the chip body 12 through the first package 3 and the second package 13, which can effectively improve the reliability of the package 10. At the same time, the first package 3 can enhance the connection reliability between the first pin 21 and the chip package structure 1.

[0067] In some embodiments, the first package 3 is further configured to encapsulate the first surface and the second surface of the first end of the first pin 21 therein, so as to encapsulate and protect the connection position of the first pin 21 with the chip package structure 1.

[0068] The package 10 provided in this application includes: a chip package structure 1, a first lead frame 2, and a first package body 3. The first lead frame 2 includes a plurality of first pins 21, the first ends of which are respectively connected to the chip package structure 1. The first package body 3 is configured to encapsulate the chip package structure 1 and the first ends of the first pins 21 within it. By connecting a plurality of first pins 21 to the chip package structure 1 and encapsulating the chip package structure 1 and the first ends of the first pins 21 within it, the package 10 can convert the packaged chip package structure 1 into another package type. Simultaneously, the package 10 can also be separated from the chip package structure 1 by separating the first package body 3 and the plurality of first pins 21 according to changes in the terminal application scenario, so that the expanded package 10 can be converted back into the package type of the chip package structure 1, thereby allowing the chip package structure 1 to be applied to another terminal scenario, effectively increasing the flexibility of the package 10.

[0069] Of course, in some other embodiments, the package 10 may not include the first package 3.

[0070] In some embodiments, combined with Figure 5 Furthermore, a lead frame is provided, which includes a plurality of first pins 21. Each first pin 21 includes a first segment 21a and a second segment 21b. The end of the first segment 21a facing away from the second segment 21b is the first end of the first pin 21, and the first end of the first pin 21 is a pointed tip, which is configured to connect to the chip package structure 1. The pointed first end of the first pin 21 facilitates engagement between the first pin 21 and the recess 111 and the second pin 112. The second segment 21b of the first pin 21 can be an elongated strip of equal width.

[0071] In some embodiments, the first segment 21a and the second segment 21b of the first pin 21 are inclined at a preset angle; this facilitates the connection of the first segment 21a of the first pin 21 to the smaller second lead frame 11, and the spacing between the second segments 21b of two adjacent first pins 21 is not too small, reducing the risk of short circuit. The preset angle can be 120°, 130°, 140°, 150°, 160°, etc.

[0072] In some embodiments, another lead frame is also provided, which is the same as described above. Figure 5 The lead frame differs in that it also includes an insulating connector, and at least some of the first pins 21 are connected together via the insulating connector 22. This facilitates the storage of the multiple first pins 21 before or after they are connected to the chip package structure 1, preventing them from being easily lost. The insulating connector 22 can be made of epoxy resin.

[0073] The above are merely embodiments of this application and do not limit the scope of this patent application. Any equivalent structural or procedural changes made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A package, characterized in that, include: Chip packaging structure; The first lead frame includes a plurality of first pins, and the first ends of the plurality of first pins are respectively connected to the chip package structure; A first package is configured to encapsulate the chip package structure and the first end of the first pin therein.

2. The package according to claim 1, characterized in that, Multiple first pins are arranged around a first carrier area, and the first ends of the first pins are detachably disposed in the first carrier area to carry the chip package structure; the second ends of the first pins are located away from the first carrier area along a first direction; wherein, the first direction intersects the height direction of the chip package structure.

3. The package according to claim 2, characterized in that, The first end of the first pin has a first surface and a second surface that are opposite to each other. The first package is further configured to encapsulate a first surface and a second surface of a first end of the first pin therein; The chip package structure is placed on the first surface of the first end of the first pin within the first carrier area.

4. The package according to claim 1, characterized in that, The chip packaging structure includes: The second lead frame has a first surface and a second surface that are opposite to each other; The chip body is disposed on the first surface of the second lead frame and is electrically connected to the second lead frame; The second package is configured to encapsulate at least a portion of the second lead frame and the chip body therein.

5. The package according to claim 4, characterized in that, The second lead frame includes: Support disk; the chip body is supported on the first surface of the support disk; The chip body has multiple second pins, and the multiple second pins are electrically connected to each other.

6. The package according to claim 5, characterized in that, The first pin and the second pin are detachably electrically connected.

7. The package according to claim 5, characterized in that, The first surface of the first end of the first pin, the second surface of the second pin, and the second surface of the support disk have a concave-convex structure.

8. The package according to claim 7, characterized in that, The first pin is soldered to the second surface of the second pin.

9. The package according to any one of claims 1-8, characterized in that, The first pin is recessed toward the side where the chip package structure is located, and defines a U-shaped groove.

10. The package according to any one of claims 1-8, characterized in that, The first lead frame consists of a plurality of independent first pins; or The first lead frame also includes an insulating connector, through which at least a portion of the first pins are connected together.

11. A lead frame, characterized in that, include: Multiple first pins, each first pin comprising a first segment and a second segment; The end of the first segment that is opposite to the second segment is a pointed tip and is configured to connect to the chip package structure.

12. A lead frame, characterized in that, include: Multiple first pins, the first ends of which are respectively configured to connect to the chip package structure; An insulating connector is provided, through which at least a portion of the first pins of a plurality of first pins are connected together.

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