A high-resolution grating subdivision module and an analog grating ruler

Abstract

This utility model relates to the field of precision instrument measurement technology, and in particular to a high-resolution grating subdivision module and an analog grating ruler. The high-resolution grating subdivision module, applied to a grating ruler, includes a signal input interface, a central control unit, a high-speed signal amplification unit, and a signal output interface. The central control unit incorporates a ZYNQ series processor. The signal input interface acquires analog signals from external devices and transmits them to the high-speed signal amplification unit, which uses a subdivision algorithm to process the signals to sub-nanometer resolution. Subsequently, the ZYNQ series processor within the central control unit utilizes an FPGA to perform high-speed parallel acquisition and adjustment processing on the subdivided high-speed analog signal, ultimately outputting a transmission signal with a communication rate of up to 1.25G through the signal output interface, thus achieving both high output rate and high-precision long-distance transmission.

Description

Technical Field

[0001] This utility model relates to the field of precision instrument measurement technology, and in particular to a high-resolution grating subdivision module and an analog grating ruler. Background Technology

[0002] A wafer is a silicon wafer used to fabricate semiconductor chips. It is generally circular in shape, hence the name "wafer." In the fields of photolithography, wafer fabrication and inspection, and packaging testing, grating rulers are used in motion control to achieve sub-nanometer (<1nm) positioning accuracy. Absolute grating rulers significantly improve photolithography efficiency because they can acquire position information without resetting.

[0003] However, while conventional analog grating ruler read heads offer high output rates, their subdivision accuracy is insufficient, resulting in shorter effective transmission distances. Therefore, a device is needed that can meet the demands of high-speed data refresh and long-distance signal transmission, while maintaining the high output rate of analog grating rulers, similar to that of absolute grating rulers, and simultaneously supporting long-distance transmission. Utility Model Content

[0004] To overcome the shortcomings of existing technologies, this application provides a high-resolution grating subdivision module and an analog grating ruler to solve the technical problems of conventional analog grating rulers having high output rates but insufficient subdivision accuracy and short effective transmission distances.

[0005] To address the aforementioned technical problems, this application provides the following technical solutions.

[0006] In a first aspect, this application provides a high-resolution grating subdivision module for use in grating rulers, including a signal input interface, a central control unit, a high-speed signal amplification unit, and a signal output interface;

[0007] The signal input interface is used to read analog signals. The input terminal of the high-speed signal amplification unit is connected to the signal input interface. The output terminal of the high-speed signal amplification unit is connected to the input terminal of the central control unit. The output terminal of the central control unit is connected to the signal output interface.

[0008] The central control unit contains a ZYNQ series processor. The high-speed signal amplification unit acquires and subdivides the analog signal from the signal input interface. After receiving the subdivided analog signal, the central control unit adjusts it and outputs a transmission signal with a communication rate of 1.25G to the signal output interface.

[0009] Furthermore, the analog signal includes a first signal and a second signal, wherein the first signal and the second signal are data signals of different types, and the high-speed signal amplification unit includes:

[0010] The first amplification unit has its input end connected to the signal input interface and its output end connected to the input end of the central control unit. The first amplification unit acquires and subdivides the first signal.

[0011] The second amplification unit has its input end connected to the signal input interface and its output end connected to the input end of the central control unit. The second amplification unit acquires and subdivides the second signal.

[0012] The first amplification unit and the second amplification unit are connected in parallel between the signal input interface and the central control unit.

[0013] Furthermore, the second amplification unit includes a first operational amplifier, a second operational amplifier, and an inverter. The non-inverting and inverting inputs of the first operational amplifier are connected to the signal input interface. The output of the first operational amplifier is connected to the non-inverting input of the second operational amplifier. An external voltage level is connected to the inverting input of the second operational amplifier. The output of the second operational amplifier is connected to the input of the inverter. The output of the inverter is connected to the input of the central control unit.

[0014] Furthermore, the high-resolution grating subdivision module also includes:

[0015] A synchronous clock signal unit is provided, wherein the input terminal of the synchronous clock signal unit is connected to the signal input interface, and the output terminal of the synchronous clock signal unit is connected to the clock signal terminal of the central control unit. The high-speed signal amplification unit and the synchronous clock signal unit are connected in parallel between the input interface and the central control unit.

[0016] The synchronous clock signal unit is used to receive the synchronous clock signal from the signal input interface and convert the synchronous clock signal into a digital signal that can be acquired by the clock port of the PL part of the central control chip.

[0017] Furthermore, the signal input interface includes:

[0018] The first external plug-in is connected to the input terminal of the high-speed signal amplification unit;

[0019] The second external plug-in is connected to the input terminal of the synchronous clock signal unit.

[0020] Furthermore, the signal output interface includes:

[0021] An optical fiber interface, the input end of which is connected to the output end of the central control unit;

[0022] A gigabit Ethernet interface, the input of which is connected to the output of the central control unit.

[0023] Furthermore, the central control unit is a hardware control unit that can be configured through programming.

[0024] Furthermore, the high-resolution grating subdivision module also includes:

[0025] The circuit board has three input interfaces on one side edge along its length. The three input interfaces are used to set the synchronous clock signal unit, the first external plug-in, and the second external plug-in, respectively. Two output interfaces are set on the opposite side edge along the length of the circuit board. The two output interfaces are used to set the fiber optic interface and the gigabit Ethernet interface, respectively. The high-speed signal amplification unit and the central control unit are both located at the center of the circuit board.

[0026] The power supply unit is located on the side edge of the circuit board in the width direction and is electrically connected to the central control unit, the synchronous clock signal unit, and the high-speed signal amplification unit.

[0027] This application also proposes an analog grating ruler, including the aforementioned high-resolution grating subdivision module and a housing, wherein the circuit board is disposed within the housing, and the housing has slots corresponding to the three input interfaces and the two output interfaces.

[0028] Furthermore, the housing includes:

[0029] A base plate, on which the circuit board is mounted;

[0030] Two supports are provided, which are spaced apart and symmetrically arranged. A first groove and a second groove are provided on the opposite side of each support, and the extending directions of the first groove and the second groove are parallel to each other.

[0031] The two side plates are spaced apart and symmetrically arranged. One side plate has a slot corresponding to the three input interfaces, and the other side plate has a slot corresponding to the two output interfaces. The bottom plate is slidably connected to the first groove.

[0032] The top plate is slidably connected to the second sliding groove, and the two side plates, the bottom plate, the top plate, and the two supports enclose and form a box-type structure.

[0033] Compared with the prior art, the beneficial effects of this application are as follows:

[0034] This application addresses the issues of insufficient subdivision accuracy and short effective transmission distance in traditional analog grating ruler readers by incorporating a subdivision module consisting of a central control unit and a high-speed signal amplification unit along the signal transmission path. The signal input interface acquires analog signals from external devices (such as grating rulers outputting 1Vpp signals) and transmits them to the high-speed signal amplification unit. This unit uses a subdivision algorithm to process the signal to sub-nanometer resolution. Subsequently, the ZYNQ series processor within the central control unit utilizes an FPGA to perform high-speed parallel acquisition and adjustment processing on the subdivided high-speed analog signal. Finally, a transmission signal with a communication rate of 1.25G is output through the signal output interface, thus achieving a balance between high output rate and high-precision long-distance transmission. Attached Figure Description

[0035] This application can be better understood by describing its embodiments in conjunction with the accompanying drawings, in which:

[0036] Figure 1 This diagram shows a structural schematic of one embodiment of the high-resolution raster subdivision module according to this application;

[0037] Figure 2 This diagram shows a structural schematic of one embodiment of the high-resolution raster subdivision module according to this application;

[0038] Figure 3 A circuit reference diagram showing one embodiment of the second amplification unit according to this application is displayed;

[0039] Figure 4 This displays a signal simulation diagram of one embodiment of the high-resolution raster subdivision module according to this application;

[0040] Figure 5 This diagram shows a structural schematic of one embodiment of the high-resolution raster subdivision module according to this application;

[0041] Figure 6 yes Figure 5 Product display images;

[0042] Figure 7 This diagram shows a structural schematic of one embodiment of the analog grating ruler according to the present application;

[0043] Figure 8 This diagram shows an exploded structural view of one embodiment of the analog grating ruler according to this application.

[0044] In the above figures, the meanings of the reference numerals are as follows:

[0045] 1. Signal input interface; 11. First external plug-in; 12. Second external plug-in; 2. Central control unit; 3. High-speed signal amplification unit; 31. First amplification unit; 32. Second amplification unit; 321. First operational amplifier; 322. Second operational amplifier; 323. Inverter; 4. Signal output interface; 41. Fiber optic interface; 42. Gigabit Ethernet interface; 5. Synchronous clock signal unit; 6. Circuit board; 7. Input interface; 8. Output interface; 9. Power supply unit; 100. Analog grating ruler; 200. Housing; 201. Base plate; 202. Bracket; 203. Side plate; 204. Top plate; 205. First slide rail; 206. Second slide rail; 207. Slot. Detailed Implementation

[0046] Unless otherwise defined, the technical or scientific terms used in this specification and claims shall have the ordinary meaning as understood by one of ordinary skill in the art to which this utility model pertains.

[0047] All the values ​​listed in this article, ranging from the lowest to the highest, refer to all values ​​obtained by incrementing the lowest and highest values ​​by one unit when the difference between the lowest and highest values ​​is more than two units.

[0048] In the description of this utility model, it should be understood that the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0049] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this utility model, unless otherwise stated, "a plurality of" means two or more.

[0050] A wafer is a silicon wafer used to fabricate semiconductor chips. It is generally circular in shape, hence the name "wafer." In the fields of photolithography, wafer fabrication and inspection, and packaging testing, grating rulers are used in motion control to achieve sub-nanometer (<1nm) positioning accuracy. Absolute grating rulers significantly improve photolithography efficiency because they can acquire position information without resetting.

[0051] However, conventional grating ruler read heads have high output rates but insufficient subdivision accuracy and short effective transmission distances. Therefore, a device is needed that can meet the requirements of high-speed data refresh and long-distance signal transmission, while being compatible with the high output rate of analog systems, similar to the output of absolute grating rulers, and also meeting the requirements of long-distance transmission.

[0052] like Figures 1-6 As shown, in view of this, this application proposes a high-resolution grating subdivision module for use in grating rulers, including a signal input interface 71, a central control unit 2, a high-speed signal amplification unit 3, and a signal output interface 84.

[0053] The signal input interface 71 is used to read analog signals. The input terminal of the high-speed signal amplification unit 3 is connected to the signal input interface 71. The output terminal of the high-speed signal amplification unit 3 is connected to the input terminal of the central control unit 2. The output terminal of the central control unit 2 is connected to the signal output interface 84.

[0054] The central control unit 2 contains a ZYNQ series processor. The high-speed signal amplification unit 3 collects and subdivides the analog signal from the signal input interface 71. After receiving the subdivided analog signal, the central control unit 2 adjusts it and outputs a transmission signal with a communication rate of 1.25G to the signal output interface 84.

[0055] In this embodiment, conventional grating ruler read heads, limited by their digital signal interfaces, cannot meet the requirements for long-distance (e.g., greater than 2m) and simultaneously high-bandwidth (e.g., greater than 100K) closed-loop use in semiconductor equipment. Figure 1 As shown, this application establishes a subdivision module with signal amplification and refinement processing by setting a central control unit 2 and a high-speed signal amplification unit 3 on the signal transmission path of the signal input interface 71 and the signal output interface 84. The signal input interface 71, after connecting to an external device, is used to acquire analog signals and transmit them to the high-speed signal amplification unit 3. The high-speed signal amplification unit 3, after acquiring the analog signal (e.g., a 1Vpp grating ruler signal), subdivides the analog signal using a subdivision algorithm and outputs an analog signal with sub-nanometer resolution, which is then transmitted to the central control unit 2. The central control unit 2 contains a ZYNQ series processor that uses an FPGA to process the high-speed signal (the subdivided analog signal) in parallel, performs adjustments, and outputs a transmission signal with a 1.25G communication rate to the signal output interface 84. This solves the technical problem that conventional grating ruler readers have high output rates but insufficient subdivision accuracy and short effective transmission distances.

[0056] It is worth mentioning that, to improve the resolution of the output signal of the signal output interface 84, this application processes the analog signal 1Vpp from the signal input interface 71 through a subdivision algorithm to achieve a sub-nanometer level output resolution. A ZYNQ series processor is used, communicating with the high-speed signal amplification unit 3 via a parallel bus interface to achieve the acquisition and subdivision processing of the 1Vpp grating ruler signal, meeting the technical requirements of a data refresh rate of 500KHz / s and a data bit depth of up to 38 bits. Furthermore, this application uses the GTP module of the ZYNQ series processor to achieve a 1.25G fiber optic signal rate, outputting the subdivided data via two FC optical ports or an SFP+ electrical module to achieve high-speed data transmission. The fiber optic transmission distance can reach 10 kilometers, meeting the requirements for long-distance transmission.

[0057] like Figure 2 As shown, specifically, the analog signal includes a first signal and a second signal, the first signal and the second signal being data signals of different types, and the high-speed signal amplification unit 3 includes:

[0058] The first amplification unit 31 has its input end connected to the signal input interface 71 and its output end connected to the input end of the central control unit 2. The first amplification unit 31 collects and subdivides the first signal.

[0059] The second amplification unit 32 has its input terminal connected to the signal input interface 71 and its output terminal connected to the input terminal of the central control unit 2. The second amplification unit 32 acquires and subdivides the second signal.

[0060] The first amplification unit 31 and the second amplification unit 32 are connected in parallel between the signal input interface 71 and the central control unit 2.

[0061] In this embodiment, since the analog signal contains multiple types of signals, such as the first signal being a 1Vpp grating ruler signal and the second signal being a pulse signal, in order to adjust and process different signals, the high-speed signal amplification unit 3 has two amplification units inside, namely the first amplification unit 31 and the second amplification unit 32. The first amplification unit 31 acquires and subdivides the 1Vpp grating ruler signal, and the second amplification unit 32 acquires and subdivides the pulse signal.

[0062] like Figure 3As shown, specifically, the second amplification unit 32 includes a first operational amplifier 321, a second operational amplifier 322, and an inverter 323. The non-inverting input and inverting input of the first operational amplifier 321 are connected to the signal input interface 71. The output of the first operational amplifier 321 is connected to the non-inverting input of the second operational amplifier 322. The inverting input of the second operational amplifier 322 is connected to an external voltage level. The output of the second operational amplifier 322 is connected to the input of the inverter 323. The output of the inverter 323 is connected to the input of the central control unit 2.

[0063] In this embodiment, in order to process the pulse signal, the pulse signal is processed by the first arithmetic unit and the second operational amplifier 322. The process processes the zero position signal of the 1Vpp grating ruler signal, compares it with a preset threshold by the inverter 323 to output high and low levels, and outputs a standard LVTTL signal after digital circuit processing to facilitate subsequent acquisition and processing by the FPGA circuit.

[0064] like Figure 4 As shown, this application can output to the host computer interface via signal output interface 84 to draw sine and cosine Lissajous circles for monitoring the sampled data.

[0065] like Figures 1-2 As shown, specifically, the high-resolution grating subdivision module further includes:

[0066] A synchronous clock signal unit 5 is provided, with its input terminal connected to the signal input interface 71 and its output terminal connected to the clock signal terminal of the central control unit 2. The high-speed signal amplification unit 3 and the synchronous clock signal unit 5 are connected in parallel between the input interface 71 and the central control unit 2.

[0067] The synchronous clock signal unit 5 is used to receive the synchronous clock signal from the signal input interface 71 and convert the synchronous clock signal into a digital signal that can be acquired by the clock port of the PL part of the central control chip.

[0068] In this embodiment, time deviation can lead to asynchronous position information and differences in time bases between different devices or systems, thus affecting the synchronization of data acquisition and processing. To address this, this application adds a synchronization clock signal unit 5, which receives the synchronization clock signal (a differential signal) from the signal input interface 71 and converts it into a digital signal that can be acquired by the clock port of the PL section of the central control chip.

[0069] Specifically, the number input interface 7 includes:

[0070] The first external plug-in 11 is connected to the input terminal of the high-speed signal amplification unit 3;

[0071] The second external plug-in 12 is connected to the input terminal of the synchronous clock signal unit 5.

[0072] In this embodiment, in order to realize multi-interface signal processing, a first external plug-in 11 and a second external plug-in 12 can be set to facilitate the synchronous clock signal unit 5 and the high-speed signal amplification unit 3 to acquire the corresponding signals.

[0073] Specifically, the signal output interface 84 includes:

[0074] Fiber optic interface 41, the input end of which is connected to the output end of the central control unit 2;

[0075] Gigabit Ethernet interface 42, the input of which is connected to the output of the central control unit 2.

[0076] In this embodiment, to facilitate the use of different external device interfaces, this application adopts both fiber optic interface 41 and gigabit Ethernet interface 42.

[0077] Specifically, the central control unit 2 is a programmable hardware control unit. In this embodiment, the programmable hardware control unit (FPGA) is a further development based on devices such as programmable array logic (PAL), general-purpose array logic (GAL), and erasable programmable logic devices (EPLD). It is a programmable logic chip that can perform general functions, that is, it can be programmed to implement certain logic processing functions. FPGA has higher integration, stronger logic functions, and greater flexibility. FPGA has wide applications in many fields, such as communications, electronics, video signal processing, and aerospace, and many powerful products have been launched, such as Intel's Stratix, Arria, and Cyclone series products, which have the advantages of low cost, low power consumption, and high performance. This application uses a programmable hardware control unit to acquire high-speed signals (analog signals with subdivision processing) through high-speed parallel processing of FPGA, and performs adjustment, and outputs a transmission signal with a communication rate of 1.25G to the signal output interface 84, which solves the technical problem that conventional grating ruler read heads have high output rates but insufficient subdivision accuracy and short effective transmission distances.

[0078] like Figures 5-6 As shown, specifically, the high-resolution grating subdivision module further includes:

[0079] The circuit board 6 has three input interfaces 7 on one side edge along its length. The three input interfaces 7 are respectively used to set the synchronous clock signal unit 5, the first external plug-in 11, and the second external plug-in 12. The circuit board 6 has two output interfaces 8 on the opposite side edge along its length. The two output interfaces 8 are respectively used to set the optical fiber interface 41 and the gigabit Ethernet interface 42. The high-speed signal amplification unit 3 and the central control unit 2 are both located at the center of the circuit board 6.

[0080] The power supply unit 9 is located on the side edge of the circuit board 6 in the width direction and is electrically connected to the central control unit 2, the synchronous clock signal unit 5, and the high-speed signal amplification unit 3.

[0081] In this embodiment, to optimize the circuit stacking structure of the high-resolution raster subdivision module, this application integrates three input interfaces 7, two output interfaces 8, a power supply unit 9, a high-speed signal amplification unit 3, and a central control unit 2 on the circuit board 6. The three input interfaces 7 are located on one side edge along the length of the circuit board 6, arranged sequentially. The synchronization clock signal unit 5, the first external plug-in 11, and the second external plug-in 12 are sequentially located within the three input interfaces 7. To facilitate interface with external devices, the two output interfaces 8 are located on the opposite side edge along the length of the circuit board 6. The fiber optic interface 41 and the Gigabit Ethernet interface 42 are sequentially located on the two output interfaces 8. The most crucial high-speed signal amplification unit 3 and central control unit 2 are both located at the center of the circuit board 6 to prevent other components from affecting them. Furthermore, the power supply unit 9 is located on the side edge along the width of the circuit board 6 and supplies power to the central control unit 2, the synchronization clock signal unit 5, and the high-speed signal amplification unit 3.

[0082] like Figures 1 to 8 As shown, this utility model also proposes an analog grating ruler 100, including the high-resolution grating subdivision module as described above, and a housing 200. The circuit board 6 is disposed within the housing 200, and the housing 200 has slots 207 corresponding to the three input interfaces 7 and the two output interfaces 8. The specific structure of the high-resolution grating subdivision module is as described in the above embodiments. Since the analog grating ruler 100 adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be elaborated here.

[0083] Specifically, the housing 200 includes:

[0084] The base plate 201, and the circuit board 6 is disposed on the base plate 201;

[0085] Two supports 202 are arranged symmetrically and at intervals from each other. A first sliding groove 205 and a second sliding groove 206 are provided on the opposite side of each support 202. The extending directions of the first sliding groove 205 and the second sliding groove 206 are parallel to each other.

[0086] Two side plates 203 are arranged symmetrically and spaced apart from each other. One side plate 203 has a slot 207 corresponding to the three input interfaces 7, and the other side plate 203 has a slot 207 corresponding to the two output interfaces 8. The bottom plate 201 is slidably connected to the first slide groove 205.

[0087] The top plate 204 is slidably connected to the second slide groove 206. The two side plates 203, the bottom plate 201, the top plate 204, and the two supports 202 enclose and form a box-type structure.

[0088] In this embodiment, for ease of manufacturing and processing, the housing 200 of this application is mainly composed of a bottom plate 201, two supports 202, two side plates 203, and a top plate 204 forming a box structure. The bottom plate 201, two supports 202, two side plates 203, and top plate 204 are all individual components, facilitating manufacturing and processing. One side plate 203 has slots 207 corresponding to the three input interfaces 7, and the other side plate 203 has slots 207 corresponding to the two output interfaces 8. The bottom plate 201 is slidably connected to the first sliding groove 205, and the top plate 204 is slidably connected to the second sliding groove 206, facilitating the installation of the bottom plate 201 and the top plate 204. Furthermore, after the two side plates 203, bottom plate 201, top plate 204, and two supports 202 are assembled to form a box structure, the two side plates 203 can be fixed to the corresponding positions of the two supports 202 with screws, facilitating installation and disassembly.

[0089] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this utility model. It should be understood that the above descriptions are merely specific embodiments of this utility model and are not intended to limit this utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. A high resolution grating subdivision module for use in a grating ruler, characterized by, Includes signal input interface, central control unit, high-speed signal amplification unit, and signal output interface; The signal input interface is used to read analog signals. The input terminal of the high-speed signal amplification unit is connected to the signal input interface. The output terminal of the high-speed signal amplification unit is connected to the input terminal of the central control unit. The output terminal of the central control unit is connected to the signal output interface. The central control unit contains a ZYNQ series processor. The high-speed signal amplification unit acquires and subdivides the analog signal from the signal input interface. After receiving the subdivided analog signal, the central control unit adjusts it and outputs a transmission signal with a communication rate of 1.25G to the signal output interface.

2. The high-resolution raster sub-module of claim 1, wherein, The analog signal includes a first signal and a second signal, wherein the first signal and the second signal are data signals of different types, and the high-speed signal amplification unit includes: The first amplification unit has its input end connected to the signal input interface and its output end connected to the input end of the central control unit. The first amplification unit acquires and subdivides the first signal. The second amplification unit has its input end connected to the signal input interface and its output end connected to the input end of the central control unit. The second amplification unit acquires and subdivides the second signal. The first amplification unit and the second amplification unit are connected in parallel between the signal input interface and the central control unit.

3. The high-resolution raster sub-module of claim 2, wherein, The second amplification unit includes a first operational amplifier, a second operational amplifier, and an inverter. The non-inverting and inverting inputs of the first operational amplifier are connected to the signal input interface. The output of the first operational amplifier is connected to the non-inverting input of the second operational amplifier. An external voltage level is connected to the inverting input of the second operational amplifier. The output of the second operational amplifier is connected to the input of the inverter. The output of the inverter is connected to the input of the central control unit.

4. The high-resolution raster sub-module of claim 2, wherein, Also includes: A synchronous clock signal unit is provided, wherein the input terminal of the synchronous clock signal unit is connected to the signal input interface, and the output terminal of the synchronous clock signal unit is connected to the clock signal terminal of the central control unit. The high-speed signal amplification unit and the synchronous clock signal unit are connected in parallel between the input interface and the central control unit. The synchronous clock signal unit is used to receive the synchronous clock signal from the signal input interface and convert the synchronous clock signal into a digital signal that can be acquired by the clock port of the PL part of the central control chip.

5. The high-resolution raster sub-module of claim 4, wherein, The signal input interface includes: The first external plug-in is connected to the input terminal of the high-speed signal amplification unit; The second external plug-in is connected to the input terminal of the synchronous clock signal unit.

6. The high-resolution grating subdivision module according to claim 5, characterized in that, The signal output interface includes: An optical fiber interface, the input end of which is connected to the output end of the central control unit; A gigabit Ethernet interface, the input of which is connected to the output of the central control unit.

7. The high-resolution grating subdivision module according to any one of claims 1-6, characterized in that, The central control unit is a hardware control unit that can be configured through programming.

8. The high-resolution grating subdivision module according to claim 6, characterized in that, Also includes: The circuit board has three input interfaces on one side edge along its length. The three input interfaces are used to set the synchronous clock signal unit, the first external plug-in, and the second external plug-in, respectively. Two output interfaces are set on the opposite side edge along the length of the circuit board. The two output interfaces are used to set the fiber optic interface and the gigabit Ethernet interface, respectively. The high-speed signal amplification unit and the central control unit are both located at the center of the circuit board. The power supply unit is located on the side edge of the circuit board in the width direction and is electrically connected to the central control unit, the synchronous clock signal unit, and the high-speed signal amplification unit.

9. An analog grating ruler, characterized in that, The device includes the high-resolution raster subdivision module as described in claim 8, and a housing, wherein the circuit board is disposed within the housing, and the housing has slots corresponding to the three input interfaces and the two output interfaces.

10. The analog grating ruler according to claim 9, characterized in that, The housing includes: A base plate, on which the circuit board is mounted; Two supports are provided, which are spaced apart and symmetrically arranged. A first groove and a second groove are provided on the opposite side of each support, and the extending directions of the first groove and the second groove are parallel to each other. Two side plates are arranged symmetrically and at intervals from each other. One side plate has a slot corresponding to the three input interfaces, and the other side plate has a slot corresponding to the two output interfaces. The bottom plate is slidably connected to the first groove. The top plate is slidably connected to the second sliding groove, and the two side plates, the bottom plate, the top plate, and the two supports enclose and form a box-type structure.

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