image sensor

Abstract

This application discloses an image sensor, which includes a pixel array, a control module, and a data line. The pixel unit in the pixel array includes a first pixel circuit, a second pixel circuit, and a row selection transistor. The first pixel circuit and the second pixel circuit in the pixel unit are connected to the data line through the same row selection transistor. The first pixel circuit is connected to a shared pixel unit through a reset transistor, and the second pixel circuit is connected to the shared pixel unit through a reset transistor. The control module is used to output a target control signal to control the delay in entering the charge clearing stage when the pixel row including the pixel circuit completes quantization control. This ensures that the time or speed at which the image sensor establishes reset nodes between different pixel rows is kept as consistent as possible during row-by-row quantization, thereby enabling the image sensor to complete quantization better.

Description

Technical Field

[0001] This application relates to the field of image sensor technology, and in particular to an image sensor. Background Technology

[0002] Image sensors are widely used in various electronic devices to capture and identify images of people or scenes, such as video surveillance systems, smartphones, digital cameras, medical devices, drones, AI, and facial recognition. In particular, the rapid development of CMOS (Complementary Metal-Oxide-Semiconductor) image sensor technology has led to higher demands on the output image quality of image sensors. An image sensor is a semiconductor-based sensor that generates electrical signals in response to light. As a crucial component of digital cameras, it converts incident light signals into electrical charges, then into voltage or current signals, and finally outputs the converted electrical signals. An image sensor contains a photosensitive pixel array, which collects light signal information from the image array and converts it into electrical signal data for use by the terminal.

[0003] In image sensors, pixels in the pixel array can be arranged in a shared structure (i.e., a compact pixel structure). This shared structure means that transistors in at least two pixels are reused. For example, two pixels in two different pixel rows may reuse reset transistors, and / or two pixels in two different pixel rows may reuse row selection transistors. In this case, the environment or behavior of establishing reset nodes through reset transistors differs between different pixel rows, leading to variations in the time or speed at which reset nodes are established, thus affecting the quantization results of the image sensor. Therefore, how to ensure that the time or speed at which reset nodes are established between different pixel rows in an image sensor remains as consistent as possible is a technical problem that urgently needs to be solved by those skilled in the art. Utility Model Content

[0004] The purpose of this application is to provide an image sensor that enables the image sensor to maintain a consistent time or speed for establishing reset nodes between different pixel rows during line-by-line quantization, thereby allowing the image sensor to perform quantization better.

[0005] To achieve the above objectives:

[0006] This application provides an image sensor, including a pixel array, a control module, and a data line. The pixel array includes multiple pixel units and multiple reset transistors. Each pixel unit includes a first pixel circuit, a second pixel circuit, and a row selection transistor. The first pixel circuit and the second pixel circuit in the pixel unit are connected to the data line through the same row selection transistor. The first pixel circuit is connected to a shared pixel unit through a reset transistor, and the second pixel circuit is connected to the shared pixel unit through a reset transistor. The control module is used to output a target control signal to control the delay in entering the charge clearing stage when the pixel row including the pixel circuit completes quantization control.

[0007] Through the above technical solution of this application, the image sensor with a pixel array using a shared reset transistor and a shared row selection transistor layout can delay the entry into the charge clearing stage when the pixel row is quantized. This makes the environment or behavior of the reset transistors corresponding to each pixel row in the pixel array establishing reset nodes as similar or the same as the environment or behavior of the reset transistors corresponding to other pixel rows establishing reset nodes as similar as possible. This allows the image sensor to maintain the same time or speed for establishing reset nodes between different pixel rows as much as possible when performing row-by-row quantization, thereby enabling the image sensor to complete quantization better. Attached Figure Description

[0008] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0009] Figure 1 This is a schematic diagram of the frame structure of the pixel column in the pixel array of the image sensor provided in the first embodiment of this application.

[0010] Figure 2 This is a first structural schematic diagram of a signal generation circuit exemplified in the second embodiment of this application.

[0011] Figure 3 This is a schematic diagram of the second structure of the signal generation circuit exemplified in the second embodiment of this application.

[0012] Figure 4 This is a third structural schematic diagram of the signal generation circuit exemplified in the second embodiment of this application.

[0013] Figure 5 This is a fourth structural schematic diagram of the signal generation circuit exemplified in the second embodiment of this application.

[0014] Figure 6 This is a circuit diagram of a pixel column in the pixel array of an image sensor, as exemplified in this application.

[0015] Figure 7 This is a waveform diagram of a key node controlling the entry into the charge clearing stage in some implementations of the examples in this application.

[0016] Figure 8 This is a waveform diagram of a key node in the image sensor control entering the charge clearing stage, as provided in the example of this application.

[0017] Figure 9 This is a flowchart of the control method for the image sensor provided in this application.

[0018] The objectives, functional features, and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. The accompanying drawings have illustrated specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to specific embodiments. Detailed Implementation

[0019] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0020] It should be understood that although the terms first, second, third, etc., may be used in this document to describe various information, elements, units, or modules, these information, elements, units, or modules should not be limited to these terms. These terms are only used to distinguish information, elements, units, or modules of the same type from one another.

[0021] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0022] In the following description, the use of suffixes such as "module," "part," or "unit" to denote elements is solely for the purpose of illustrative purposes and has no specific meaning in itself. Therefore, "module," "part," or "unit" may be used interchangeably.

[0023] First Embodiment

[0024] This embodiment provides an image sensor, including a pixel array, a control module, and a data line. The pixel array includes multiple pixel units and multiple reset transistors. Each pixel unit includes a first pixel circuit, a second pixel circuit, and a row selection transistor.

[0025] In one embodiment, the pixel array further includes at least one of a first boundary unit and a second boundary unit.

[0026] In one embodiment, the pixel column of the pixel array includes multiple pixel units and multiple reset transistors. Correspondingly, the pixel column also includes at least one of a first boundary unit and a second boundary unit. The pixel column can be found in [reference needed]. Figure 1 As shown.

[0027] In this design, the first pixel circuit and the second pixel circuit in the pixel unit are connected to the data line via a selection transistor in the same row. The first pixel circuit is connected to a shared pixel unit or a first boundary unit via a reset transistor, and the second pixel circuit is connected to a shared pixel unit or a second boundary unit via a reset transistor. The sharing between pixel units can be adjacent or staggered. For example, in the case of adjacent sharing, the first pixel circuit is connected to the preceding pixel unit or the first boundary unit via a reset transistor, and the second pixel circuit is connected to the following pixel unit or the second boundary unit via a reset transistor. The sharing method between pixel units can also be selected according to the actual circuit connection method.

[0028] The control module is used to output a target control signal to control the delay of entering the charge clearing stage when the pixel row, including the pixel circuit, completes the quantization control.

[0029] In one embodiment, the control module is used to drive pixel rows including pixel circuits in the pixel array to perform quantization control. When a pixel row including pixel circuits completes quantization control, it outputs a target control signal to control its delayed entry into the charge clearing stage until at least one pixel row whose quantization sequence follows it completes quantization control. It should be noted that the description of "row" here refers to quantization. For example, when using a row-by-row quantization method, one quantization row corresponds to one whole pixel row; when using a half-row quantization method, one quantization row is half a pixel row. In this embodiment, a whole pixel row is used as the quantization row for explanation.

[0030] In one embodiment, the control module can also be used to drive the pixel rows in the pixel array to perform quantization control individually; that is, the control module can also be used to drive the pixel array to perform row-by-row quantization (or step-by-step quantization). Understandably, quantization control characterizes the process of converting the analog signals read from each pixel row of the pixel array configured in the image sensor into digital signals. In this process, the light intensity (usually represented by charge) of the pixel point formed by each pixel circuit in the pixel row is converted into a digital value, which represents the brightness or color information of that pixel point.

[0031] In one embodiment, the delay time for a pixel row that has completed quantization control to enter the charge clearing stage is greater than or equal to the time required for a first preset number of pixel rows whose quantization order follows it to complete quantization control. Thus, the technical solution of this embodiment can prevent the pixel row from entering the charge clearing stage after it has completed quantization control, but before the first preset number of pixel rows whose quantization order follows it have all completed quantization control. In other words, the pixel row enters the charge clearing stage only after the first preset number of pixel rows whose quantization order follows it have all completed quantization control. The first preset number is an integer greater than or equal to 1.

[0032] The multiple pixel units in the pixel column may include the first pixel unit, the middle pixel unit, the last pixel unit, and further include the corresponding first boundary unit and second boundary unit.

[0033] In this unit, the first pixel circuit and the second pixel circuit in the first pixel unit are connected to the data line through the same row of selection transistors. The first pixel circuit is connected to the first boundary unit through a reset transistor, and the second pixel circuit is connected to the pixel unit in the next row (i.e., the middle pixel unit) through a reset transistor.

[0034] In one embodiment, the first boundary unit can characterize any device or combination of devices that can serve as the boundary of the pixel array, such as an input interface for a specific signal, a wire for transmitting a specific signal, a boundary circuit including a dual-conversion gain transistor, or the same circuit as the pixel unit in the pixel array.

[0035] In this intermediate pixel unit, the first pixel circuit and the second pixel circuit are connected to the data line through the same row selection transistor. The first pixel circuit is connected to the preceding pixel unit (e.g., the first pixel unit or the preceding intermediate pixel unit) through the reset transistor, and the second pixel circuit is connected to the following pixel unit (e.g., the following intermediate pixel unit) through the reset transistor.

[0036] In this configuration, the first pixel circuit and the second pixel circuit in the last pixel unit are connected to the data line through the same row selection transistor. The first pixel circuit is connected to the preceding pixel unit (e.g., the middle pixel unit) through the reset transistor, and the second pixel circuit is connected to the second boundary unit through the reset transistor.

[0037] In one embodiment, the second boundary unit can characterize any device or combination of devices that can serve as the boundary of the pixel array, such as an input interface for a specific signal, a wire for transmitting a specific signal, a boundary circuit including a dual-conversion gain transistor, or the same circuit as the pixel unit in the pixel array.

[0038] In this pixel unit, the first pixel circuit and the second pixel circuit belong to two pixel rows in the pixel array, respectively. Optionally, the first pixel circuit and the second pixel circuit in the pixel unit belong to two adjacent pixel rows in the pixel array, respectively. Optionally, the pixel row to which the first pixel circuit in the pixel unit belongs can be either the preceding or succeeding stage of the pixel row to which the second pixel circuit in the pixel unit belongs.

[0039] Understandably, when two pixel circuits in a pixel unit correspond to the first pixel row and the second pixel row respectively, when performing quantization control on the first pixel row, it is necessary to change the reset transistor shared by the pixel circuits in the second pixel row and the pixel circuits in other pixel rows from high voltage to low voltage. For example, the drain voltage of the reset transistor is changed from high voltage to low voltage. This prevents the second pixel row from clamping the quantization signal of the first pixel row because the two pixel circuits in the pixel units corresponding to the first and second pixel rows share the row selection transistor connection data line. Therefore, changing the drain voltage of the reset transistor shared by the pixel circuits in the second pixel row and the pixel circuits in other pixel rows from high voltage to low voltage is called establishing a reset node.

[0040] by Figure 1 For example, when quantizing the (k+2)th level pixel row, the pixel circuits in the (k+3)th level pixel row need to be... <4> Pixel circuits in the (k+4)th pixel row <5> Shared reset transistor rst <3> The drain voltage changes from high voltage to low voltage, thereby preventing the two pixel circuits (such as those in the pixel units corresponding to the (k+2)th and (k+3)th level pixel rows from changing from high voltage to low voltage. Figure 1 Pixel circuits in <3> and pixel circuit <4> Common row selection transistor rs <2> The connection of the data cable caused the quantization signal of the (k+3)th pixel row to be clamped, thus affecting the pixel circuitry in the (k+3)th pixel row. <4> Pixel circuit with the (k+4)th pixel row <5> Shared reset transistor rst <3> The transition from high voltage to low voltage is called establishing a reset node.

[0041] The time or speed at which a reset node is established is affected by the presence of capacitive nodes in the connection structure at the reset transistor's path (i.e., by the environment or behavior in which the reset node is established). Examples of capacitive nodes in the connection structure at the reset transistor's path include low-gain nodes in dual-conversion-gain transistors, floating diffusion nodes, and optoelectronic devices when a transmission transistor is turned on.

[0042] In some implementations, because the pixel array is quantized level by level, and each pixel row immediately enters the charge clearing stage after quantization control, the environment or behavior for establishing a reset node during quantization control of the preceding pixel row differs from that of the following pixel row. This results in a significant difference in the time or speed at which the reset node is established during quantization control of the preceding and following pixel rows. Figure 1 Taking the k-th pixel row, k+1-th pixel row, k+2-th pixel row, and k+3-th pixel row as examples, the following example illustrates the concept:

[0043] When performing quantization control on the k-th pixel row, the reset transistor rst connected between the (k+1)-th and (k+2)-th pixel rows needs to be reset. <2> The voltage changes from high to low to establish a reset node. At this time, since neither the (k+1)th nor the (k+2)th pixel row has undergone quantization control, the transmission transistors in the (k+1)th and (k+2)th pixel rows are in the off state. Therefore, the reset transistor rst connected between the (k+1)th and (k+2)th pixel rows... <2> It will not charge the photosensitive devices connected to the transmission transistor in the pixel circuit of the (k+1)th pixel row and the pixel circuit of the (k+2)th pixel row; and when the kth pixel completes quantization control, it will immediately turn on the transmission transistor of its pixel circuit to enter the charge clearing stage.

[0044] When performing quantization control on the (k+1)th level pixel row, it is necessary to reset the reset transistor rst connected between the kth level pixel row and the first boundary unit. <1> The voltage changes from high to low to establish a reset node. At this time, since the k-th pixel row has completed quantization control and entered the charge clearing stage, the reset transistor rst connected between the k-th pixel row and the first boundary cell is activated. <1> Compared to the reset transistor rst connected between the (k+1)th and (k+2)th pixel rows, <2> Therefore, at least the photosensitive device connected to the transmission transistor in the k-th pixel row needs to be charged (i.e., the environment or behavior of establishing a reset node when performing quantization control on the k-th pixel row is different from the environment or behavior of establishing a reset node when performing quantization control on the (k+1)-th pixel row). Thus, compared to the reset transistor rst connected between the (k+1)-th and (k+2)-th pixel rows... <2> The reset transistor rst connected between the k-th pixel row and the first boundary unit <1> At least additional charging is required for the photosensitive device connected to the transmission transistor in the pixel circuit of the k-th pixel row, which results in a longer or slower time to establish the reset node.

[0045] In addition, when the (k+1)th level pixel completes quantization control, the transmission transistor of the pixel circuit will be turned on immediately to enter the charge clearing stage;

[0046] When performing quantization control on the (k+2)th pixel row, the reset transistor rst connected between the (k+3)th and (k+4)th pixel rows needs to be reset. <3> The voltage changes from high to low to establish a reset node. At this time, since neither the (k+3)th nor the (k+4)th pixel row has quantization control, the transfer transistors in the pixel circuits of the (k+3)th and (k+4)th pixel rows are in the off state. Therefore, the reset transistor rst connected between the (k+3)th and (k+4)th pixel rows... <3> It will not charge the photosensitive devices connected to the transmission transistors in the (k+3)th and (k+4)th pixel rows; in addition, when the (k+2)th pixel completes quantization control, it will immediately turn on the transmission transistors of the pixel circuits therein to enter the charge clearing stage.

[0047] When performing quantization control on the (k+3)th pixel row, the reset transistor rst connected between the (k+1)th and (k+2)th pixel rows needs to be reset. <2> The voltage changes from high to low to establish a reset node. At this point, since both the (k+1)th and (k+2)th pixel rows have completed quantization control and entered the charge clearing stage, the reset transistor rst connected between the (k+1)th and (k+2)th pixel rows... <2> Compared to the reset transistor rst connected between the (k+3)th and (k+4)th pixel rows, <3> Therefore, at least the photosensitive devices connected to the transmission transistors in the pixel circuits of the (k+1)th and (k+2)th pixel rows also need to be charged (i.e., the environment or behavior of establishing a reset node when performing quantization control on the (k+3)th pixel row is different from the environment or behavior of establishing a reset node when performing quantization control on the (k+2)th pixel row). Therefore, compared to the reset transistors rst connected between the (k+3)th and (k+4)th pixel rows... <3> The reset transistor rst connected between the (k+1)th level pixel row and the (k+2)th level pixel row <2> At least additional charging is required for the photosensitive devices connected to the transmission transistors in the pixel circuits of the (k+1)th and (k+2)th pixel rows, which results in a longer or slower time to establish the reset node.

[0048] When performing quantization control on other pixel rows of the pixel array in some implementations, the situation of establishing a reset node can be deduced from the above content, and will not be repeated here.

[0049] To address the shortcomings of some implementation methods, the technical solution of this embodiment can achieve the following effects:

[0050] When performing quantization control on the k-th pixel row, the reset transistor rst connected between the (k+1)-th and (k+2)-th pixel rows is... <2> The voltage changes from high to low to establish a reset node. At this time, since neither the (k+1)th nor the (k+2)th pixel row has undergone quantization control, the transfer transistors in the pixel circuits of the (k+1)th and (k+2)th pixel rows are in the off state. Therefore, the reset transistor rst connected between the (k+1)th and (k+2)th pixel rows... <2> The system will not charge the photosensitive devices connected to the transmission transistors in the pixel circuits of the (k+1)th and (k+2)th pixel rows; and when the quantization control of the kth pixel row is completed, the control module outputs a target control signal to control the kth pixel row to delay entering the charge clearing stage. For example, it will delay until at least one pixel row after the kth pixel row (such as the 3rd pixel row after the kth pixel row) has completed the quantization control before controlling the transmission transistors in the kth pixel row to turn on to enter the charge clearing stage.

[0051] When performing quantization control on the (k+1)th pixel row, the reset transistor rst connected between the kth pixel row and the first boundary unit is... <1> The voltage changes from high to low to establish a reset node. At this time, since the k-th pixel row has completed quantization control but has not yet entered the charge clearing stage (i.e., the transfer transistor in the pixel circuit of the k-th pixel row is in the off state), the reset transistor rst connected between the k-th pixel row and the first boundary cell is activated. <1> It will not charge the photosensitive device connected to the transmission transistor in the pixel circuit of the k-th pixel row; therefore, the environment or behavior of establishing a reset node when performing quantization control on the (k+1)-th pixel row is similar to or the same as the environment or behavior of establishing a reset node when performing quantization control on the k-th pixel row, thus the reset transistor rst connected between the k-th pixel row and the first boundary unit will not be charged. <1> The time or speed at which the reset node is established, and the reset transistor rst connected between the (k+1)th and (k+2)th level pixel rows. <2> The time or speed at which reset nodes are established is similar or the same;

[0052] Furthermore, when the quantization control of the (k+1)th level pixel row is completed, the control module outputs a target control signal to control the (k+1)th level pixel row to delay entering the charge clearing stage. For example, it is delayed until at least one level pixel row after the (k+1)th level pixel row (such as the 3rd level pixel row after the (k+1)th level pixel row) has completed the quantization control before controlling the transmission transistor in the (k+1)th level pixel row to turn on to enter the charge clearing stage.

[0053] When performing quantization control on the (k+2)th pixel row, the reset transistor rst connected between the (k+3)th and (k+4)th pixel rows is... <3> The voltage changes from high to low to establish a reset node. At this time, since neither the (k+3)th nor the (k+4)th pixel row has quantization control, the transfer transistors in the pixel circuits of the (k+3)th and (k+4)th pixel rows are in the off state. Therefore, the reset transistor rst connected between the (k+3)th and (k+4)th pixel rows... <3> The system will not charge the photosensitive devices connected to the transmission transistors in the pixel circuits of the (k+3)th and (k+4)th pixel rows; and when the quantization control of the (k+2)th pixel row is completed, the control module outputs a target control signal to control the (k+2)th pixel row to delay entering the charge clearing stage. For example, it will delay until at least one pixel row after the (k+2)th pixel row (such as the 3rd pixel row after the (k+2)th pixel row) has completed the quantization control before controlling the transmission transistors in the (k+2)th pixel row to turn on to enter the charge clearing stage.

[0054] When performing quantization control on the (k+3)th pixel row, the reset transistor rst connected between the (k+1)th and (k+2)th pixel rows is... <2> The voltage changes from high to low to establish a reset node. At this time, since both the (k+1)th and (k+2)th pixel rows have completed quantization control but have not yet entered the charge clearing stage (i.e., the transfer transistors in the pixel circuits of the (k+1)th and (k+2)th pixel rows are in the off state), the reset transistor rst connected between the (k+1)th and (k+2)th pixel rows is off. <2> Nor will it charge the photosensitive devices connected to the transmission transistors in the pixel circuits of the (k+1)th and (k+2)th pixel rows; therefore, the environment or behavior for establishing a reset node when performing quantization control on the (k+3)th pixel row is the same as that for establishing a reset node when performing quantization control on the (k+2)th pixel row, thus the reset transistor rst connected between the (k+1)th and (k+2)th pixel rows will be deactivated. <2> The time or speed at which the reset node is established, and the reset transistor rst connected between the (k+3)th and (k+4)th level pixel rows. <3> The time or speed at which the reset node is established is the same;

[0055] Furthermore, when the quantization control of the (k+3)th pixel row is completed, the control module outputs a target control signal to control the (k+3)th pixel row to delay entering the charge clearing stage. For example, it delays until at least one pixel row after the (k+3)th pixel row (such as three pixel rows after the (k+3)th pixel row) has completed the quantization control before controlling the transmission transistor in the (k+3)th pixel row to turn on to enter the charge clearing stage.

[0056] When performing quantization control on other pixel rows of the pixel array in this embodiment, the situation of establishing a reset node can be deduced from the above content, and will not be repeated here.

[0057] According to the above technical content, the technical solution of this application can make the environment or behavior of the reset transistor corresponding to the quantization control of each pixel row in the pixel array establishing the reset node as similar or the same as the environment or behavior of the reset transistor corresponding to the quantization control of other pixel rows establishing the reset node, so that the image sensor can maintain the same or similar time or speed for establishing the reset node between different pixel rows when performing row-by-row quantization, thereby enabling the image sensor to complete quantization better.

[0058] Second Embodiment

[0059] This embodiment provides an image sensor, including a pixel array, a control module, and a data line. The pixel array includes multiple pixel units and multiple reset transistors. Each pixel unit includes a first pixel circuit, a second pixel circuit, and a row selection transistor.

[0060] In one embodiment, the pixel array further includes at least one of a first boundary unit and a second boundary unit.

[0061] In one embodiment, the pixel column of the pixel array includes a plurality of pixel units and a plurality of reset transistors. Correspondingly, the pixel column also includes at least one of a first boundary unit and a second boundary unit.

[0062] In this pixel unit, the first pixel circuit and the second pixel circuit are connected to the data line through the same row of selection transistors. The first pixel circuit is connected to the shared pixel unit or the first boundary unit through a reset transistor, and the second pixel circuit is connected to the shared pixel unit or the second boundary unit through a reset transistor.

[0063] The control module is used to output a target control signal to control the delay of entering the charge clearing stage when the pixel row, including the pixel circuit, completes the quantization control.

[0064] In one embodiment, the control module is used to output a target control signal to control the delay of entering the charge clearing stage when the pixel row including the pixel circuit completes the quantization control, until the quantization sequence of at least one pixel row after it completes the quantization control.

[0065] In one embodiment, the delay time for a pixel row that has completed quantization control to enter the charge clearing stage is greater than or equal to the time required for a first preset number of pixel rows whose quantization order follows it to complete quantization control. Thus, the technical solution of this embodiment can prevent a specific pixel row from entering the charge clearing stage after it has completed quantization control, and before the first preset number of pixel rows whose quantization order follows it have all completed quantization control. In other words, the specific pixel row enters the charge clearing stage only after the first preset number of pixel rows whose quantization order follows it have all completed quantization control.

[0066] In one embodiment, the first preset number is at least 3.

[0067] In one embodiment, the control module includes a signal generation circuit, which includes a selector and a latch (see...). Figure 2 ).

[0068] In one embodiment, the control module is further configured to sequentially provide a second preset number of first address signals, wherein the second preset number is greater than or equal to the number of pixel rows corresponding to the pixel array. Optionally, the control module may provide address signals (e.g., first address signals) based on the data circuitry therein.

[0069] The image sensor's pixel array is configured with a second preset number of first address signals, where the second preset number is greater than or equal to the number of pixel rows in the pixel array. For example, multiple first address signals can be provided based on digital circuitry, or alternatively, other existing methods in the image sensor. The pixel units can be configured according to existing address configuration methods in image sensors; that is, each pixel unit is configured with its own address, and control signals for the pixel units are formed based on different addresses.

[0070] The selector includes at least one input terminal and one output terminal. The selector is connected to the first signal interface of the latch through the output terminal. It is used to select a first address signal provided by the digital circuit as the target control signal according to a preset selection rule, and output it through the output terminal and provide it to the first signal interface of the latch.

[0071] The target control signal output by the selector is used to support the pixel rows in the pixel array to enter the charge clearing stage according to the delay time when the quantization control is completed.

[0072] It should be understood that the selector's output can output target control signals respectively when quantization control is completed for at least some (partial or all) of the pixel rows in the pixel array. In an image sensor, address signals can be used to select corresponding pixels based on a preset timing sequence. The latch can use multiple MOS transistors and inverters, etc., to output control signals based on the relevant input address signals according to a preset timing sequence to realize the operation of the image sensor. For example, as shown... Figure 2 As shown, the latch receives sp_add (exposure line address signal), sp_tx (exposure line transmission signal), rp_tx (sampling line transmission signal), and rp_add (sampling line address signal) to form lat_addb (the inverse signal of the latch line address signal) to control the transmission transistor and determine whether to turn it on to enter the charge clearing latch state. The above address signals can be provided by the digital circuit part of the image sensor in the existing way.

[0073] Among them, the preset selection rule can be to take the first address signal corresponding to the first address signal after pushing the first preset number of positions in a sequential or reverse manner as the target control signal for the second preset number of first address signals provided by the digital circuit.

[0074] In one embodiment, the latch can also receive other control signals, such as sp_add as the exposure line address signal, sp_tx as the exposure line transmission signal, and rp_tx as the sampling line transmission signal. In addition, rp_add as the sampling line address signal, rp_addb as the inverse signal of the sampling line address signal, lat_add as the latch line address signal, and lat_addb as the inverse signal of the latch line address signal.

[0075] In one embodiment, see Figure 2 The selector includes an enable terminal, a first input terminal, and a second input terminal. Driven by the enable signal dd_flip_en received at the enable terminal, the selector uses the first address signal received at the first input terminal, after sequentially pushing back a first preset number of positions, as the target control signal (e.g., ...). Figure 2 rp_add<a+b> ), and output through the output terminal; or, the selector is driven by the enable signal dd_flip_en connected to the enable terminal, and takes the first address signal corresponding to the first preset number of positions forward in reverse order received by the second input terminal as the target control signal (such as Figure 2 rp_add <a-b>The signal generation circuit in this embodiment, through the function of the selector, can support the flip mode (or inverted mode) of the image sensor, thereby determining the target control signal in a sequential or reverse manner in both forward and reverse readout states. Users can select and set the installation and readout order of the image sensor chip based on the flip mode for flexible device configuration.

[0076] In one implementation, when the first preset number is b (b≥3), taking the quantization control of the a-th pixel row as an example, the signal generation circuit in the control module selects the first address signal corresponding to the a+b-th or ab-th sequence position from the register as the target control signal (e.g., Figure 2 rp_add<a+b> Or rp_add <a-b>), where the ordinal position of the data 'a' can correspond to the level position of the 'a'-th pixel row in the pixel array.

[0077] In one embodiment, when the second preset number of first address signals provided by the control module is equal to the number of pixel rows corresponding to the pixel array, after each of the first preset number of pixel rows of the adjacent boundary unit (first boundary unit or second boundary unit) (hereinafter referred to as the tail-level pixel row) completes quantization control, the selector cannot select the first address signal corresponding to the a+b or ab sequence position from the control module as the target control signal according to the preset rules. At this time, the output of the selector can be connected to a Class D flip-flop to generate and output a second address signal as the target control signal through the Class D flip-flop, so as to support the tail-level pixel row to enter the charge clearing stage according to the delay time when quantization control is completed.

[0078] In one embodiment, each of the pixel rows in the pixel array that are adjacent to a first preset number of first boundary units or second boundary units can be defined as a tail-level pixel row. For example, when the first preset number is 3, the first-level pixel row, the second-level pixel row, and the third-level pixel row adjacent to the first boundary unit or second boundary unit in the pixel array can all be called tail-level pixel rows, and the first-level pixel row adjacent to the first boundary unit or second boundary unit can be the last valid pixel row of the pixel array. Based on the above description, pixel rows in the pixel array can include tail-level pixel rows and non-tail-level pixel rows.

[0079] In one embodiment, the signal generation circuit further includes a first preset number of Class D flip-flops. The input of the selector is connected in series with the first preset number of Class D flip-flops, which are used to generate and output a target control signal to the input of the selector when, according to a preset selection rule, a first address signal cannot be selected from the control module as the target control signal.

[0080] Among them, see Figure 3 or Figure 4 A Class D flip-flop includes an input data terminal D, an output terminal Q, and a clock control terminal CLK. The input data terminal D receives the address signal, the clock control terminal CLK receives the clock control signal, and the output terminal Q is used to output the second address signal generated by the Class D flip-flop.

[0081] See Figure 3 The first preset number is 3 (i.e., b=3), in a positive readout state, and the last row of pixels in the pixel array is the last row of valid pixels adjacent to the second boundary unit (e.g., Figure 1 Take the (k+n)th pixel row as an example:

[0082] The signal generation circuit includes a first Class D flip-flop, a second Class D flip-flop, and a third Class D flip-flop;

[0083] Among them, the input data terminal D of the first type D flip-flop receives the first address signal rp_add corresponding to the end of the sequence in the register.<k+n> The output Q of the first Class D flip-flop is connected to the input data D of the second Class D flip-flop, and the output Q of the second Class D flip-flop is connected to the input data D of the third Class D flip-flop. The clock control terminals CLK of the first Class D flip-flop, CLK of the second Class D flip-flop, and CLK of the third Class D flip-flop receive the clock signal rp_row_en, thereby causing the output Q of the third Class D flip-flop to output the target control signal to support the delayed entry into the charge clearing stage when the k+n level pixel row completes quantization control.

[0084] Optionally, the output Q of the second Class D flip-flop can also output the target control signal to support the delayed entry into the charge clearing stage when the k+n-1 level pixel row completes quantization control;

[0085] Optionally, the output Q of the first Class D flip-flop can also output a target control signal to support the delayed entry into the charge clearing stage when the k+n-2th pixel row completes quantization control.

[0086] See Figure 4 The first preset number is 3 (i.e., b=3), the reverse readout state, and the pixel row of the tail level is the last effective pixel row of the pixel array adjacent to the first boundary unit (e.g. Figure 1 For example, the k-th pixel row in the image:

[0087] The signal generation circuit includes a first Class D flip-flop, a second Class D flip-flop, and a third Class D flip-flop;

[0088] Among them, the input data terminal D of the first type D flip-flop receives the first address signal rp_add corresponding to the end of the sequence in the register. <k>The output Q of the first Class D flip-flop is connected to the input data D of the second Class D flip-flop, and the output Q of the second Class D flip-flop is connected to the input data D of the third Class D flip-flop. The clock control terminals CLK of the first Class D flip-flop, CLK of the second Class D flip-flop, and CLK of the third Class D flip-flop receive the clock signal rp_row_en, thereby causing the output Q of the third Class D flip-flop to output the target control signal to support the delayed entry into the charge clearing stage when the k-th pixel row completes quantization control.

[0089] Optionally, the output Q of the second Class D flip-flop can also output the target control signal to support the delayed entry into the charge clearing stage when the k+1th pixel row completes quantization control;

[0090] Optionally, the output Q of the first Class D flip-flop can also output a target control signal to support the delayed entry into the charge clearing stage when the k+2 level pixel row completes quantization control.

[0091] In one embodiment, the target control signal output by the selector according to a preset selection rule is used to cause the signal generation circuit to enter the charge clearing stage after a delay time when controlling the non-tail-level pixel row to complete the quantization control. In this embodiment, it also corresponds to the target control signal output by the selector.

[0092] In one embodiment, the selector outputs a target control signal through a second preset number of Class D flip-flops, which is used to cause the signal generation circuit to control the pixel row of the tail stage to enter the charge clearing stage according to the delay time when the pixel row completes the quantization control.

[0093] In one embodiment, the control module may further include a control circuit, which may include multiple control circuit units. The aforementioned signal generation circuit may be included in the control circuit unit. Optionally, each control circuit unit corresponds to a pixel row in the pixel array. The control circuit unit may control the pixel circuit in the pixel row based on various signals output by the image sensor. For example, when the signal generation circuit outputs a target control signal, the control circuit unit may control the transmission transistor in the pixel circuit of the pixel row it is connected to (e.g., delay its conduction), thereby delaying the aforementioned pixel row from entering the charge clearing stage.

[0094] In another embodiment, see Figure 5 The signal generation circuit in the control module may include a latch, a first selector, and a signal generation unit.

[0095] The first selector includes two input terminals (e.g. Figure 5 in rp_add_d3 The corresponding input terminals and rp_add_d3 <a-b> The first selector has corresponding input terminals, output terminals, and enable terminals. Its input terminal is connected to the signal generation unit, its output terminal is connected to the first signal interface of the latch, and its enable terminal receives a first enable signal (e.g., ...).< / a-b> Figure 5 (dd_flip_en in the text).

[0096] In one embodiment, the two input terminals of the first selector can be connected to a signal generation unit, respectively. Figure 5 Only one of the two input terminals is shown connected to the signal generation unit.

[0097] The first selector is driven by the first enable signal to select one of the two input terminals as the target control signal and transmit it to the first signal interface of the latch. The target control signal is generated and output by the signal generation unit.

[0098] The latch is used to control the pixel row in the pixel array to enter the charge clearing stage according to the received target control signal when the pixel row completes the quantization control.

[0099] The signal generation unit includes a second selector and multiple Class D flip-flops (e.g., Figure 5 (Class D flip-flops 1 to Class D flip-flops n).

[0100] The second selector includes multiple input terminals, an output terminal, and an enable terminal. The multiple input terminals of the second selector are respectively connected to the output terminals of multiple Class D flip-flops (e.g., one-to-one connection). The output terminal of the second selector is connected to the input terminal of the first selector. The enable terminal of the second selector receives a second enable (e.g., ...). Figure 5 The signal dd_delay_add_sel in the context of this.

[0101] The second selector is driven by the second enable signal to select one of the multiple Class D flip-flops and output the address signal output from the output terminal of the selected Class D flip-flop to the input terminal of the first selector.

[0102] In one embodiment, the input data terminal of the Class D flip-flop receives a start address signal, which can be a preset address signal or an address signal output by the output terminal of another Class D flip-flop.

[0103] In one embodiment, the address signals output by the output terminals of multiple Class D flip-flops are different from each other, and / or can form an address signal sequence.

[0104] Based on the above technical concepts and Figure 5 Example, Figure 5 The outputs of the n Class D flip-flops in the array are rp_add_d1 rp_add_d2 …rp_add_dn If, according to the preset selection rules, any number of address signals need to be pushed forward or backward, rp_add_d1 can be selected through the second enable signal dd_delay_add_sel. rp_add_d2 …rp_add_dn The address signal of any output is output to the circuits that follow (e.g., output to the input of the first selector).

[0105] In another embodiment, the aforementioned signal generation circuit may be included in the control circuit unit.

[0106] Through the above technical solution of this application, the image sensor with a pixel array using a shared reset transistor and a shared row selection transistor layout can, when completing the quantization control of a pixel row, delay its entry into the charge clearing stage by controlling the target control signal output by the signal generation circuit in the control module. This makes the environment or behavior of the reset transistors corresponding to each pixel row in the pixel array establishing reset nodes as similar or the same as the environment or behavior of the reset transistors corresponding to other pixel rows establishing reset nodes as similar or the same. This allows the image sensor to maintain a consistent time or speed for establishing reset nodes between different pixel rows during row-by-row quantization, thereby enabling the image sensor to complete quantization better and establish reset nodes faster (the reset node does not contain optoelectronic devices) to compress readout time.

[0107] Furthermore, the control module of the signal generation circuit in this embodiment is equivalent to a pixel driving circuit, which enables the behavior or environment of establishing a reset node when each pixel row is quantized to be symmetrical (for example, the behavior or environment of establishing a reset node is symmetrical between odd-numbered pixel rows and even-numbered pixel rows), so that the image sensor can achieve high-quality signal quantization.

[0108] Based on the same inventive concept as the foregoing embodiments, the image sensor described in the foregoing embodiments will be illustrated by specific examples below:

[0109] See Figure 6 This example provides a pixel array for an image sensor. The pixel column of the pixel array includes multiple pixel units, multiple reset transistors rst, a first boundary unit and a second boundary unit. The pixel unit includes a first pixel circuit, a second pixel circuit and a row selection transistor rs. The first pixel circuit and the second pixel circuit belong to two adjacent pixel rows in the pixel array (e.g., an odd-numbered pixel row and an even-numbered pixel row).

[0110] The first pixel circuit includes a first optoelectronic device pd, a first transmission transistor tx, a first floating diffusion node fd, a first source follower transistor sf, and a first dual conversion gain transistor dcg.

[0111] The control terminal of the first transmission transistor tx receives the control signal, and the two terminals of the first transmission transistor tx are respectively connected to the first optoelectronic device pd and the first floating diffusion node fd.

[0112] In this configuration, the control terminal of the first source follower transistor sf is connected to the first floating diffusion node fd, the second path terminal of the first source follower transistor sf is connected to the data line through the two path terminals of the row select transistor rs, the first path terminal of the first source follower transistor sf receives the power supply signal, and the control terminal of the row select transistor rs receives the control signal.

[0113] In this configuration, the control terminal of the first dual-conversion-gain transistor DCG receives a control signal, the first path terminal of the first dual-conversion-gain transistor DCG is connected to a shared pixel unit or a first boundary unit through the second path terminal of a reset transistor RST, and the second path terminal of the first dual-conversion-gain transistor DCG is connected to a first floating diffusion node FD; wherein, the control terminal of the reset transistor RST receives a control signal, and the first path terminal RSTD of the reset transistor RST receives a charging signal.

[0114] In the case where the first path terminal of the first dual-conversion-gain transistor dcg is connected to the shared pixel unit through the second path terminal of a reset transistor rst, it can be that the first path terminal of the first dual-conversion-gain transistor dcg is connected to the first path of the second dual-conversion-gain transistor dcg in the second pixel circuit of the preceding pixel unit through the second path terminal of a reset transistor rst.

[0115] Optionally, the first boundary unit may be composed of a dual-conversion-gain transistor (dcg).

[0116] The second pixel circuit includes a second optoelectronic device pd, a second transmission transistor tx, a second floating diffusion node fd, a second source follower transistor sf, and a second double conversion gain transistor dcg.

[0117] The control terminal of the second transmission transistor tx receives the control signal, and the two terminals of the second transmission transistor tx are respectively connected to the second optoelectronic device pd and the second floating diffusion node fd.

[0118] The control terminal of the second source follower transistor sf is connected to the second floating diffusion node fd, the second path terminal of the second source follower transistor sf is connected to the data line through the two path terminals of the shared row select transistor rs, and the first path terminal of the second source follower transistor sf receives the power signal.

[0119] In this configuration, the control terminal of the second dual-conversion gain transistor dcg receives a control signal, the second path terminal of the second dual-conversion gain transistor dcg is connected to the second floating diffusion node fd, and the first path terminal of the second dual-conversion gain transistor dcg is connected to the shared pixel unit or the second boundary unit through the second path terminal of another reset transistor rst; wherein, the control terminal of the other reset transistor rst receives a control signal, and the first path terminal of the other reset transistor rst receives a charging signal.

[0120] In the case where the first path terminal of the second dual-conversion gain transistor dcg is connected to the shared pixel unit through the second path terminal of another reset transistor rst, it can be that the first path terminal of the second dual-conversion gain transistor dcg is connected to the first path of the first dual-conversion gain transistor dcg of the first pixel circuit in the subsequent pixel unit through the second path terminal of another reset transistor rst.

[0121] Optionally, the second boundary unit can be composed of a dual-conversion-gain transistor (dcg).

[0122] In some implementations, because the pixel array is quantized level by level, and each pixel row immediately enters the charge clearing stage after quantization control, the environment or behavior for establishing a reset node during quantization control of an adjacent pixel row differs from that of a subsequent pixel row. This results in a significant difference in the time or speed at which a reset node is established during quantization control of an earlier pixel row compared to that of a subsequent pixel row. Combined with... Figure 1 and Figure 6 Taking the k-th pixel row, the (k+1)-th pixel row, the (k+2)-th pixel row, and the (k+3)-th pixel row as examples, the following is an illustration:

[0123] When performing quantization control on the k-th pixel row, the reset transistor rst connected between the (k+1)-th and (k+2)-th pixel rows needs to be reset. <2> The drain voltage changes from high to low to establish a reset node. At this time, since neither the (k+1)th nor the (k+2)th pixel row has quantization control, the transfer transistor tx in the (k+1)th and (k+2)th pixel rows is in the off state. Therefore, the reset transistor rst connected between the (k+1)th and (k+2)th pixel rows... <2> It will affect the two corresponding floating diffusion nodes (such as Figure 6 fd in<k+1> ,fd<k+2> ), two double-conversion gain transistors (such as Figure 6 DCG in<k+1> dcg<k+2> The corresponding LCG node () Figure 6 (not shown), but will not charge the photosensitive device pd connected to the transmission transistor tx in the pixel circuit of the (k+1)th pixel row and the pixel circuit of the (k+2)th pixel row; and when the kth pixel completes quantization control, it will immediately turn on the transmission transistor tx of the pixel circuit to enter the charge clearing stage.

[0124] When performing quantization control on the (k+1)th level pixel row, it is necessary to reset the reset transistor rst connected between the kth level pixel row and the first boundary unit. <1> The drain voltage changes from high to low to establish a reset node. At this time, since the k-th pixel row has completed quantization control and the transmission transistor tx has entered the charge clearing stage, the reset transistor rst connected between the k-th pixel row and the first boundary cell is activated. <1> It will affect the corresponding floating diffusion nodes (such as Figure 6 fd in <k>), two double-conversion gain transistors (such as Figure 6 DCG in <k>、dcg <k-1>The corresponding LCG node () Figure 6 (Not shown) and the photosensitive device pd connected to the transmission transistor tx in the pixel circuit of the k-th pixel row. <k>Charging; that is, the environment or behavior of establishing a reset node when performing quantization control on the k-th pixel row is different from the environment or behavior of establishing a reset node when performing quantization control on the (k+1)-th pixel row, and will result in the time to establish a reset node being longer or the speed being slower than that of establishing a reset node.

[0125] In addition, when the (k+1)th level pixel completes quantization control, the transmission transistor tx of the pixel circuit will be turned on immediately to enter the charge clearing stage;

[0126] When performing quantization control on the (k+2)th pixel row, the reset transistor rst connected between the (k+3)th and (k+4)th pixel rows needs to be reset. <3> The drain voltage changes from high to low to establish a reset node. At this time, since neither the (k+3)th nor the (k+4)th pixel row is quantized, the transfer transistor tx in the pixel circuits of the (k+3)th and (k+4)th pixel rows is off. Therefore, the reset transistor rst connected between the (k+3)th and (k+4)th pixel rows... <3> It will affect the two corresponding floating diffusion nodes (such as Figure 6 fd in<k+3> ,fd<k+4> ), two double-conversion gain transistors (such as Figure 6 DCG in<k+3> dcg<k+4> The corresponding LCG node () Figure 6 (not shown), but will not provide the photosensitive devices (such as pd) connected to the transmission transistor tx in the (k+3)th and (k+4)th pixel rows.<k+3> ,pd<k+4> ) Charging; In addition, when the (k+2)th level pixel completes quantization control, it will immediately turn on the transmission transistor tx of the pixel circuit to enter the charge clearing stage;

[0127] When performing quantization control on the (k+3)th pixel row, the reset transistor rst connected between the (k+1)th and (k+2)th pixel rows needs to be reset. <2> The drain voltage changes from high to low to establish a reset node. At this time, since both the (k+1)th and (k+2)th pixel rows have completed quantization control and both are conducting, the transmission transistor tx has entered the charge clearing stage. Therefore, the reset transistor rst connected between the (k+1)th and (k+2)th pixel rows... <2> It will affect the two corresponding floating diffusion nodes (such as Figure 6 fd in<k+1> ,fd<k+2> ), two double-conversion gain transistors (such as Figure 6 DCG in<k+1> dcg<k+2> The corresponding LCG node () Figure 6 (Not shown), the photosensitive devices (such as pd) connected to the transmission transistor tx in the (k+3)th and (k+4)th pixel rows respectively.<k+1> ,pd<k+2> Charging; that is, the environment or behavior of establishing a reset node when performing quantization control on the (k+3)th pixel row is different from the environment or behavior of establishing a reset node when performing quantization control on the (k+2)th pixel row, and will result in the establishment of a reset transistor rst. <2> Compared to establishing a reset transistor rst <3> The time taken is long or the speed is slow;

[0128] In addition, when the (k+3)th level pixel completes quantization control, the transmission transistor tx of the pixel circuit will be turned on immediately to enter the charge clearing stage;

[0129] When performing quantization control on other pixel rows of the pixel array in some implementations, the situation of establishing a reset node can be deduced from the above content, and will not be repeated here.

[0130] For waveform diagrams of key nodes controlling the entry into the charge clearing phase in some implementations, please refer to [link / reference]. Figure 7 .

[0131] To address the shortcomings of some implementation methods, the technical solution in this example configures a control module in the image sensor that, after quantizing each pixel row, delays its entry into the charge clearing stage by three address signals. This ensures that the environment or behavior of the reset transistors establishing reset nodes during quantization control of each pixel row in the pixel array is similar or identical to the environment or behavior of the reset transistors establishing reset nodes during quantization control of other pixel rows. This allows the image sensor to maintain as consistent a time or speed as possible for establishing reset nodes between different pixel rows during row-by-row quantization, thereby enabling the image sensor to perform quantization more effectively. A specific example is shown below:

[0132] When performing quantization control on the k-th pixel row, the reset transistor rst connected between the (k+1)-th and (k+2)-th pixel rows is... <2> The drain voltage changes from high to low to establish a reset section. At this time, since neither the (k+1)th nor the (k+2)th pixel row is quantized, the transfer transistor tx in the pixel circuits of the (k+1)th and (k+2)th pixel rows is off. Therefore, the reset transistor rst connecting the (k+1)th and (k+2)th pixel rows is off. <2> It will affect the two corresponding floating diffusion nodes (such as Figure 6 fd in<k+1> ,fd<k+2> ), two double-conversion gain transistors (such as Figure 6 DCG in<k+1> dcg<k+2> The corresponding LCG node () Figure 6 (Not shown), but it will not charge the photosensitive device pd connected to the transmission transistor tx in the pixel circuit of the (k+1)th pixel row and the pixel circuit of the (k+2)th pixel row; and when the kth pixel completes quantization control, it will delay the three address signals and then turn on the transmission transistor tx of the pixel circuit to enter the charge clearing stage. That is to say, when the kth pixel completes quantization control, it will be controlled by the control module to complete quantization control of the subsequent 3 pixel rows before entering the charge clearing stage.

[0133] When performing quantization control on the (k+1)th pixel row, the reset transistor rst connected between the kth pixel row and the first boundary unit is... <1> The voltage changes from high to low to establish a reset node. At this time, since the k-th pixel row has completed quantization control but has not yet entered the charge clearing stage (i.e., the transfer transistor tx in the pixel circuit of the k-th pixel row is in the off state), the reset transistor rst connected between the k-th pixel row and the first boundary cell is activated. <1> It will affect the corresponding floating diffusion nodes (such as Figure 6 fd in <k>), two double-conversion gain transistors (such as Figure 6 DCG in <k>、dcg <k-1>The corresponding LCG node () Figure 6 (Not shown) Charging, but not charging the photosensitive device connected to the transmission transistor tx in the pixel circuit of the k-th pixel row; therefore, the environment or behavior of establishing a reset node when performing quantization control on the (k+1)-th pixel row is similar to the environment or behavior of establishing a reset node when performing quantization control on the k-th pixel row, thus the reset transistor rst connected between the k-th pixel row and the first boundary unit. <1> The time or speed at which the reset node is established, and the reset transistor rst connected between the (k+1)th and (k+2)th level pixel rows. <2> The time or speed for establishing reset nodes is similar;

[0134] Furthermore, when the quantization control of the (k+1)th level pixel row is completed, the transmission transistor tx of the pixel circuit will be turned on after a delay of three address signals to enter the charge clearing stage. In other words, when the quantization control of the (k+1)th level pixel is completed, it will enter the charge clearing stage only after the subsequent three levels of pixel rows have completed quantization control, under the control of the control module.

[0135] When performing quantization control on the (k+2)th pixel row, the reset transistor rst connected between the (k+3)th and (k+4)th pixel rows is... <3> The drain voltage changes from high to low to establish a reset node. At this time, since neither the (k+3)th nor the (k+4)th pixel row has quantization control, the transfer transistors in the pixel circuits of the (k+3)th and (k+4)th pixel rows are in the off state. Therefore, the reset transistor rst connected between the (k+3)th and (k+4)th pixel rows... <3> ), will affect its two corresponding floating diffusion nodes (such as Figure 6 fd in<k+3> ,fd<k+4> ), two double-conversion gain transistors (such as Figure 6 DCG in<k+3> dcg<k+4> The corresponding LCG node () Figure 6 (not shown), but will not provide the photosensitive devices (such as pd) connected to the transmission transistor tx in the pixel circuits of the (k+3)th pixel row and the pixel circuits of the (k+4)th pixel row.<k+3> ,pd<k+4> ) charging; and when the quantization control of the (k+2)th level pixel row is completed, the transmission transistor tx of the pixel circuit will be turned on after the three address signals are delayed to enter the charge clearing stage. That is to say, when the (k+2)th level pixel is completed, it will be controlled by the control module to enter the charge clearing stage only after the subsequent 3 levels of pixel rows have completed the quantization control.

[0136] When performing quantization control on the (k+3)th pixel row, the reset transistor rst connected between the (k+1)th and (k+2)th pixel rows is... <2> The drain voltage changes from high to low to establish a reset node. At this time, since both the (k+1)th and (k+2)th pixel rows have completed quantization control but have not yet entered the charge clearing stage (i.e., the transfer transistors tx in the pixel circuits of the (k+1)th and (k+2)th pixel rows are in the off state), the reset transistor rst connected between the (k+1)th and (k+2)th pixel rows is turned off. <2> It will affect the two corresponding floating diffusion nodes (such as Figure 6 fd in<k+1> ,fd<k+2> ), two double-conversion gain transistors (such as Figure 6 DCG in<k+1> dcg<k+2> The corresponding LCG node () Figure 6 (Not shown), but it will not provide the photosensitive devices (such as pd) connected to the transmission transistor tx in the pixel circuits of the (k+1)th pixel row and the respective pixel circuits of the (k+2)th pixel row.<k+1> ,pd<k+2> Charging; therefore, the environment or behavior of establishing a reset node when performing quantization control on the (k+3)th pixel row is the same as that when performing quantization control on the (k+2)th pixel row, thus the reset transistor rst connected between the (k+1)th and (k+2)th pixel rows is activated. <2> The time or speed at which the reset node is established, and the reset transistor rst connected between the (k+3)th and (k+4)th level pixel rows. <3> The time or speed at which the reset node is established is the same;

[0137] Furthermore, when the quantization control of the (k+3)th pixel row is completed, the transmission transistor tx of the pixel circuit will be turned on after a delay of three address signals to enter the charge clearing stage. In other words, when the quantization control of the (k+3)th pixel is completed, it will be controlled by the control module to enter the charge clearing stage only after the subsequent three pixel rows have completed quantization control.

[0138] When performing quantization control on other pixel rows of the pixel array in this example, the situation of establishing a reset node can be deduced from the above content, and will not be repeated here.

[0139] In this example, the waveform diagram of the key node entering the charge clearing stage under the control of the control module can be found in [reference needed]. Figure 8 .

[0140] Based on the same inventive concept as the foregoing embodiments, see [link to previous document]. Figure 9 This application provides a control method for an image sensor. The image sensor includes a pixel array, a control module, and data lines. The pixel column of the pixel array includes multiple pixel units, multiple reset transistors, and / or at least one of a first boundary unit and a second boundary unit. The pixel unit includes a first pixel circuit, a second pixel circuit, and a row selection transistor. The first pixel circuit and the second pixel circuit in the pixel unit are connected to the data line through the same row selection transistor. The first pixel circuit is connected to the preceding pixel unit or the first boundary unit through the reset transistor, and the second pixel circuit is connected to the following pixel unit or the second boundary unit through the reset transistor. The control method includes the following steps: S11: Quantization control is performed on the pixel rows in the pixel array that include pixel circuits, and when the pixel row completes the quantization control, a target control signal is output to control it to enter the charge clearing stage according to the delay time.

[0141] In one embodiment, the delay time is greater than or equal to the time required for a first preset number of pixel rows to complete quantization control.

[0142] The image sensor control method provided in this application embodiment enables an image sensor with a pixel array using a shared reset transistor and a shared row selection transistor layout to delay entering the charge clearing stage when performing quantization control on a pixel row. This ensures that the environment or behavior of the reset transistors corresponding to each pixel row in the pixel array establishing reset nodes during quantization control is similar or identical to the environment or behavior of the reset transistors corresponding to other pixel rows during quantization control. This allows the image sensor to maintain a consistent time or speed for establishing reset nodes between different pixel rows during row-by-row quantization, thereby enabling the image sensor to perform quantization better.

[0143] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0144] In this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, which includes not only the elements listed but also other elements not expressly listed.

[0145] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims. < / k> < / k> < / k> < / k> < / k> < / k>

Claims

1. An image sensor, characterized by, It includes a pixel array, a control module, and data lines. The pixel array includes multiple pixel units and multiple reset transistors. The pixel unit includes a first pixel circuit, a second pixel circuit, and a row selection transistor. The first pixel circuit and the second pixel circuit in the pixel unit are connected to the data line through the same row selection transistor. The first pixel circuit is connected to the shared pixel unit through a reset transistor, and the second pixel circuit is connected to the shared pixel unit through a reset transistor. The control module is used to output a target control signal to control the delay in entering the charge clearing stage when the pixel row, including the pixel circuit, completes quantization control.

2. The image sensor of claim 1, wherein, The pixel array includes a pixel column comprising multiple pixel units and multiple reset transistors. The pixel column of the pixel array further includes at least one of a first boundary unit and a second boundary unit. The first pixel circuit is connected to the shared pixel unit or the first boundary unit through a reset transistor, and the second pixel circuit is connected to the shared pixel unit or the second boundary unit through a reset transistor.

3. The image sensor of claim 1, wherein, The delay time for the pixel row that has completed the quantization control to enter the charge clearing stage is greater than or equal to the time required for the first preset number of pixel rows that follow it in the quantization sequence to complete the quantization control.

4. The image sensor of claim 3, wherein, The control module includes a signal generation circuit, which includes a selector and a latch. The control module is also used to provide a second preset number of first address signals in an orderly manner, wherein the second preset number is greater than or equal to the number of pixel rows corresponding to the pixel array; The selector includes at least one input terminal and one output terminal. The selector is connected to the first signal interface of the latch through the output terminal. It is used to select a first address signal as the target control signal according to a preset selection rule, and output the signal through the output terminal to input the first signal interface of the latch. The preset selection rule is to use the first address signal corresponding to the first preset number of positions after pushing the first preset number of positions in a sequential or reverse manner as the target control signal. The target control signal output from the output terminal of the selector is used to cause the pixel row in the pixel array to enter the charge clearing stage according to the delay time when the quantization control is completed.

5. The image sensor of claim 4, wherein, The selector includes an enable terminal, a first input terminal, and a second input terminal; The selector, driven by an enable signal received at the enable terminal, outputs the target control signal, obtained by sequentially pushing back the first preset number of positions received at the first input terminal, through the output terminal; or... The selector is driven by the enable signal connected to the enable terminal to output the target control signal obtained by pushing the first preset number of positions forward in reverse order received at the second input terminal through the output terminal.

6. The image sensor according to claim 4, characterized in that, The control module includes a control circuit, which includes multiple control circuit units. The signal generation circuit is included in the control circuit unit, and the control circuit unit is connected to the pixel row of the pixel array. The control circuit unit is used to control the transmission transistor in the pixel circuit connected to the pixel row when the signal generation circuit outputs the target control signal, so that the pixel row connected to it enters the charge clearing stage with a delay.

7. The image sensor according to any one of claims 4-6, characterized in that, The second preset number of the first address signals is equal to the number of pixel rows corresponding to the pixel array; The signal generation circuit also includes the first preset number of Class D flip-flops; The first preset number of Class D flip-flops are connected in series to the input of the selector. When the first address signal cannot be selected as the target control signal according to the preset selection rule, at least one of the first preset number of Class D flip-flops generates and outputs the target control signal to the input of the selector.

8. The image sensor according to claim 7, characterized in that, The pixel array includes the tail-level pixel rows and the non-tail-level pixel rows, wherein the tail-level pixel rows represent any one of the first preset number of pixel rows adjacent to the first boundary unit or the second boundary unit. The target control signal output from the output terminal of the selector, determined according to the preset selection rule, is used to cause the signal generation circuit to control the non-tail-level pixel row to complete the quantization control and enter the charge clearing stage according to the delay time. The target control signal output by the first preset number of D-type flip-flops is used to cause the signal generation circuit to enter the charge clearing stage according to the delay time when the pixel row of the tail stage completes the quantization control.

9. The image sensor according to claim 1, characterized in that, The control module outputs the target control signal to control the pixel row to delay entering the charge clearing stage until at least one other pixel row whose quantization order follows it completes the quantization control.

10. The image sensor according to claim 3, characterized in that, The control module includes a signal generation circuit, which includes a latch, a first selector, and a signal generation unit. The first selector includes two input terminals, an output terminal, and an enable terminal. The input terminals of the first selector are connected to the signal generation unit, the output terminals of the first selector are connected to the first signal interface of the latch, and the enable terminal of the first selector receives a first enable signal. The first selector is driven by the first enable signal to select one of the two input terminals as the target control signal and transmit it to the first signal interface of the latch, wherein the target control signal is generated and output by the signal generation unit; The latch is used to control the pixel row in the pixel array to enter the charge clearing stage according to the received target control signal when the quantization control is completed.

11. The image sensor according to claim 10, characterized in that, The signal generation unit includes a second selector and multiple Class D flip-flops; The second selector includes multiple input terminals, an output terminal, and an enable terminal. The multiple input terminals of the second selector are respectively connected to the output terminals of the multiple Class D flip-flops. The output terminal of the second selector is connected to the input terminal of the first selector. The enable terminal of the second selector receives a second enable signal. The second selector is driven by the second enable signal to select one of the plurality of Class D flip-flops, and outputs the address signal output by the output terminal of the selected Class D flip-flop to the input terminal of the first selector; The input data terminal of the Class D flip-flop receives a start address signal, which is a preset address signal or another address signal output by the output terminal of the Class D flip-flop; the address signals output by the output terminals of the multiple Class D flip-flops are different from each other and / or can form an address signal sequence.

12. The image sensor according to claim 1, characterized in that, The first pixel circuit and the second pixel circuit belong to two pixel rows in the pixel array, respectively. The first pixel circuit includes a first optoelectronic device, a first transmission transistor, a first floating diffusion node, a first source follower transistor, and a first dual-conversion gain transistor; The control terminal of the first transmission transistor receives a control signal, and the two terminals of the first transmission transistor are respectively connected to the first optoelectronic device and the first floating diffusion node; The control terminal of the first source follower transistor is connected to the first floating diffusion node, the second path terminal of the first source follower transistor is connected to the data line through the two path terminals of the row select transistor, the first path terminal of the first source follower transistor receives a power signal, and the control terminal of the row select transistor receives a control signal. The control terminal of the first dual-conversion-gain transistor receives a control signal, and the first path terminal of the first dual-conversion-gain transistor is connected to the shared pixel unit or the first boundary unit through the second path terminal of a reset transistor. The second path terminal of the first dual-conversion-gain transistor is connected to the first floating diffusion node. The control terminal of the reset transistor receives a control signal, and the first path terminal of the reset transistor receives a charging signal. The second pixel circuit includes a second optoelectronic device, a second transmission transistor, a second floating diffusion node, a second source follower transistor, and a second dual-conversion gain transistor; The control terminal of the second transmission transistor receives a control signal, and the two terminals of the second transmission transistor are respectively connected to the second optoelectronic device and the second floating diffusion node; The control terminal of the second source follower transistor is connected to the second floating diffusion node, the second path terminal of the second source follower transistor is connected to the data line through the two path terminals of the row select transistor, and the first path terminal of the second source follower transistor receives the power signal. The control terminal of the second dual-conversion-gain transistor receives a control signal, the second path terminal of the second dual-conversion-gain transistor is connected to the second floating diffusion node, and the first path terminal of the second dual-conversion-gain transistor is connected to the shared pixel unit or second boundary unit through the second path terminal of another reset transistor; wherein, the control terminal of the other reset transistor receives a control signal, and the first path terminal of the other reset transistor receives a charging signal.

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