A switcher digital audio mixing control circuit and device

Abstract

This utility model relates to a digital audio mixing control circuit and device for a switcher, including a first SDI chip, a second SDI chip, a first HDMI chip, a second HDMI chip, and an FPGA chip, as well as an audio processing chip and a SOC chip. The SOC chip is connected to both the first and second HDMI chips, the FPGA chip is connected to the SOC chip, and the audio processing chip is connected to the SOC chip. It can configure different sampling rates of each input to a consistent sampling rate, and uses external mixing. No data loss or noise is caused during mixing. When the SDI signal is input to the FPGA, the I2S signal is separated and can be directly output to the audio processing chip for synchronization without internal delay processing. The SOC chip can be flexibly configured to various sampling rates, or to unify the on / off output and mixing of the four channels, without occupying other chip resources for processing, which is very convenient.

Description

Technical Field

[0001] This utility model relates to the field of digital audio mixing technology, and more specifically, to a digital audio mixing control circuit and device for a switcher. Background Technology

[0002] The I2S protocol is commonly used for data transmission between audio devices. It transmits audio data through digital audio signals and is widely used in various audio decoders, digital signal processors (DSPs), and other embedded audio systems to ensure that these devices can exchange data smoothly and accurately. I2S synchronization is a key technical aspect.

[0003] See Figure 1 and Figure 2 Currently, most devices on the market only have a Master outputting timing and data, while the Slave synchronously receives the clock and data. Under normal circumstances, audio data is generally not lost or delayed. However, if two or more I2S audio sources are mixed and interleaved, data bit loss or delay occurs. This problem is present in most switchers on the market, and it occurs at the very beginning of the mixing process. It is particularly noticeable when the output volume is high. The problem arises when the two I2S audio clocks are not synchronized, making it impossible to use one clock to align and sample the two data bits. Audio analysis tools on a PC can show the data loss at the start of the mixing process. Some switchers modify the software to delay the clock, but it is still difficult to align the frequency points for sampling and output at the beginning, and the bits of the previous audio source will be lost, resulting in incomplete playback. This detracts from a perfect audio source output and leads to poor listening quality. A digital audio mixing control circuit and device for switchers that can solve the above problems is needed. Utility Model Content

[0004] The technical problem to be solved by this utility model is to provide a digital audio mixing control circuit for a switcher, and also to provide a digital audio mixing control device for a switcher, in view of the above-mentioned defects of the prior art.

[0005] The technical solution adopted by this utility model to solve its technical problem is:

[0006] A digital audio mixing control circuit for a switcher is constructed, comprising a first SDI chip, a second SDI chip, a first HDMI chip, a second HDMI chip, and an FPGA chip. The first SDI chip, the second SDI chip, the first HDMI chip, and the second HDMI chip are all connected to the FPGA chip. The circuit also includes an audio processing chip and a SOC chip.

[0007] The SOC chip is connected to both the first HDMI chip and the second HDMI chip, and performs initialization communication with the first HDMI chip and the second HDMI chip.

[0008] After initial communication, the first HDMI chip and the second HDMI chip each output an I2S signal to the audio processing chip at a set sampling rate.

[0009] The FPGA chip is connected to the SOC chip, and according to the SPI configuration of the SOC chip, it separates the two SDI signals input from the first SDI chip and the second SDI chip and outputs two I2S signals to the audio processing chip.

[0010] The audio processing chip is connected to the SOC chip, and mixes the four I2S signals obtained in pairs according to the SPI configuration of the SOC chip and outputs them to the FPGA chip.

[0011] The digital audio mixing control circuit for the switcher described in this utility model further includes an active crystal oscillator and a clock drive distribution controller.

[0012] The active crystal oscillator is connected to the clock drive distribution controller, generates a set clock frequency, and sends it to the clock drive distribution controller.

[0013] The clock drive distribution controller is connected to both the FPGA chip and the audio processing chip. It splits the received clock frequency into two and sends them to the FPGA chip and the audio processing chip respectively for clock data synchronization.

[0014] The set clock frequency is 12.288MHz.

[0015] The digital audio mixing control circuit for the switcher described in this utility model further includes an LED driver chip and an LED display screen.

[0016] The LED driver chip is connected to both the SOC chip and the LED display screen, receives control commands from the SOC chip, and drives the LED display screen to operate.

[0017] The digital audio mixing control circuit for the switcher described in this utility model further includes control buttons.

[0018] The SOC chip is connected to and controlled by the control button.

[0019] The digital audio mixing control circuit for the switcher described in this utility model has a set sampling rate of 48kHz.

[0020] A digital audio mixing control device for a switcher, wherein the device is provided with a digital audio mixing control circuit for a switcher as described above.

[0021] The beneficial effects of this utility model are as follows: By applying the digital audio mixing control device of the switcher of this application, which relies on the audio processing chip, the different sampling rates of each input can be configured into a consistent sampling rate. At the same time, external mixing is used, which does not require the FPGA to use a single clock to synchronize the data of one of the four channels. No data is lost during mixing and no noise is caused. When the SDI signal is input to the FPGA, the I2S signal is separated and can be directly output to the audio processing chip for synchronization without internal delay processing. This reduces the impact of the FPGA on the I2S signal when processing video signals. In addition, the SOC chip can be flexibly configured to various sampling rates, or the four channels can be turned on and off for output and mixing can be unified without occupying other chip resources for processing, which is very convenient. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the present invention will be further described below in conjunction with the accompanying drawings and embodiments. The drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is an I2S timing diagram;

[0024] Figure 2 This is a schematic diagram of the existing digital audio mixing control circuit for a switcher;

[0025] Figure 3 This is a block diagram of the switching station digital audio mixing control circuit of a preferred embodiment of the present invention. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, a clear and complete description will be provided below in conjunction with the technical solutions in the embodiments of this utility model. Obviously, the described embodiments are some, but not all, of the embodiments of this utility model. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0027] The preferred embodiment of this utility model is a digital audio mixing control circuit for a switcher, such as... Figure 3As shown, it includes a first SDI chip 100, a second SDI chip 101, a first HDMI chip 102, a second HDMI chip 103, and an FPGA chip 104. The first SDI chip 100, the second SDI chip 101, the first HDMI chip 102, and the second HDMI chip 103 are all connected to the FPGA chip 104. It also includes an audio processing chip 2 and a SOC chip 3.

[0028] SOC chip 3 is connected to both the first HDMI chip 102 and the second HDMI chip 103, and performs initialization communication with the first HDMI chip 102 and the second HDMI chip 103.

[0029] After the first HDMI chip 102 and the second HDMI chip 103 initialize communication, each outputs an I2S signal to the audio processing chip 2 at a set sampling rate. The preferred sampling rate is 48kHz. Of course, other rates can be used as needed, and there is no limitation on this.

[0030] The FPGA chip 104 is connected to the SOC chip 3. According to the SPI configuration of the SOC chip 3, it separates the two SDI signals input from the first SDI chip 100 and the second SDI chip 101 and outputs two I2S signals to the audio processing chip 2.

[0031] Audio processing chip 2 is connected to SOC chip 3. According to the SPI configuration of SOC chip 3, it mixes the four I2S signals obtained in pairs and outputs them to FPGA chip 104.

[0032] like Figure 3 As shown, the SOC chip 3 configures the audio processing chip 2 via SPI. After fully synchronizing the four received I2S signals, the signals can be mixed in pairs and then output back to the FPGA chip 104 for processing. The output SCK, LRCK, D1, D2, D3, and D4 are the synchronized I2S signals, where D1 is the data of the first SDI input, D2 is the data of the second SDI input, D3 is the data of the first HDMI input, and D4 is the data of the second HDMI input.

[0033] The specific advantages of using the switcher digital audio mixing control device of this application are as follows:

[0034] 1. Audio processing chip 2 can synchronize asynchronous input clocks and configure different sampling rates of each input to a consistent sampling rate, such as 48kHz, 96kHz, or 192kHz.

[0035] 2. The audio processing chip 2 has a digital audio latency of up to 800 milliseconds at a sampling rate of 48kHz.

[0036] 3. Mixing is achieved through an external chip (audio processing chip 2), eliminating the need for a single clock inside the FPGA to synchronize data from one of the four channels. Data is not lost during mixing, and noise is not generated.

[0037] 4. When the SDI signal (originating from the first SDI chip 100 and the second SDI chip 101) is input to the FPGA chip 104, the I2S signal is separated and can be directly output to the audio processing chip 2 for synchronization without internal delay processing, thus reducing the impact of the FPGA chip 104 on the I2S signal when processing video signals.

[0038] 5. The SOC chip can be flexibly configured to various sampling rates, or to unify the four channels for output on / off and mixing, without occupying other chip resources for processing, which is very convenient.

[0039] It should be noted that the FPGA chip 104 can be of model XCAU10P-SBVB484, or other existing chip models that have the same functions required to implement this application, without limitation; the audio processing chip 2 can be of model ADAU1452, or other existing chip models that have the same functions required to implement this application, without limitation; the SOC chip 3 can be of model RV1109 or RV1126, or other existing chip models that have the same functions required to implement this application, without limitation.

[0040] Preferably, the digital audio mixing control circuit of the switcher also includes an active crystal oscillator 4 and a clock drive distribution controller 5;

[0041] An active crystal oscillator 4 is connected to a clock drive distribution controller 5 to generate a set clock frequency and send it to the clock drive distribution controller. The set clock frequency is preferably 12.288MHz. Of course, other frequencies can be used as needed, and there is no limitation on this.

[0042] The clock drive distribution controller 5 is connected to both the FPGA chip 104 and the audio processing chip 2. It divides the received clock frequency into two parts and sends them to the FPGA chip and the audio processing chip respectively for clock data synchronization.

[0043] This method ensures that the FPGA chip and the audio processing chip can maintain clock data synchronization at all times during operation;

[0044] The clock drive distribution controller 5 can be a CDCVF2505DR, or other existing chip models that have the same functions required for this application. There is no limitation on this.

[0045] Preferably, the digital audio mixing control circuit of the switcher also includes an LED driver chip 6 and an LED display screen 7;

[0046] LED driver chip 6 is connected to both SOC chip 3 and LED display screen 7, and receives control commands from SOC chip 3 to drive and control the operation of LED display screen 7.

[0047] This part can use a conventional LED driver chip 6 and an LED display screen 7, and there are no restrictions on which one is used.

[0048] Preferably, the digital audio mixing control circuit of the switcher also includes control buttons 8;

[0049] SOC chip 3 is connected to and controlled by control button 8;

[0050] This part can use the control buttons 8 of a standard SOC chip 3, and there are no restrictions on this.

[0051] A switcher digital audio mixing control device, wherein the device is provided with a switcher digital audio mixing control circuit according to the above description.

[0052] It should be understood that those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A digital audio mixing control circuit for a switcher, comprising a first SDI chip, a second SDI chip, a first HDMI chip, a second HDMI chip, and an FPGA chip, wherein the first SDI chip, the second SDI chip, the first HDMI chip, and the second HDMI chip are all connected to the FPGA chip, characterized in that, It also includes audio processing chips and SOC chips; The SOC chip is connected to both the first HDMI chip and the second HDMI chip, and performs initialization communication with the first HDMI chip and the second HDMI chip. After initial communication, the first HDMI chip and the second HDMI chip each output an I2S signal to the audio processing chip at a set sampling rate. The FPGA chip is connected to the SOC chip, and according to the SPI configuration of the SOC chip, it separates the two SDI signals input from the first SDI chip and the second SDI chip and outputs two I2S signals to the audio processing chip. The audio processing chip is connected to the SOC chip, and mixes the four I2S signals obtained in pairs according to the SPI configuration of the SOC chip and outputs them to the FPGA chip.

2. The digital audio mixing control circuit for a switcher according to claim 1, characterized in that, The switcher digital audio mixing control circuit also includes an active crystal oscillator and a clock drive distribution controller. The active crystal oscillator is connected to the clock drive distribution controller, generates a set clock frequency, and sends it to the clock drive distribution controller. The clock drive distribution controller is connected to both the FPGA chip and the audio processing chip. It splits the received clock frequency into two and sends them to the FPGA chip and the audio processing chip respectively for clock data synchronization.

3. The digital audio mixing control circuit for a switcher according to claim 2, characterized in that, The set clock frequency is 12.288MHz.

4. The digital audio mixing control circuit for a switcher according to claim 1, characterized in that, The digital audio mixing control circuit of the switcher also includes an LED driver chip and an LED display screen; The LED driver chip is connected to both the SOC chip and the LED display screen, receives control commands from the SOC chip, and drives the LED display screen to operate.

5. The digital audio mixing control circuit for a switcher according to claim 1, characterized in that, The switcher digital audio mixing control circuit also includes control buttons; The SOC chip is connected to and controlled by the control button.

6. The digital audio mixing control circuit for a switcher according to claim 1, characterized in that, The set sampling rate is 48kHz.

7. A digital audio mixing control device for a switcher, characterized in that, The device is equipped with a switcher digital audio mixing control circuit according to any one of claims 1-6.

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