Goa driving circuit and display device
By simplifying the GOA driver circuit structure and adopting the design of a reset module and an inverter module, the problems of complex GOA driver circuit structure and high cost are solved, achieving circuit simplification and cost reduction, while extending device life.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- ZHEJIANG LAIBAO DISPLAY TECHNOLOGY CO LTD
- Filing Date
- 2025-04-29
- Publication Date
- 2026-05-29
AI Technical Summary
Existing GOA driving circuits are complex, costly, and have large bezels on the display panel.
A novel GOA driver circuit structure is adopted, including a pull-up module, an input module, a pull-down module, a pull-down sustaining module, an inverter module, and a reset module. The reset module outputs a reset control signal to the pull-down control node, enabling the pull-down sustaining module to pull down the output of both the pull-up control node and the GOA driver circuit to a low level, thus simplifying the circuit structure and reducing the number of reset modules.
The circuit structure was simplified, the cost was reduced, the display panel bezel was reduced, and the design of the inverter module reduced the possibility of transistors being on for extended periods, thus extending the device lifespan.
Smart Images
Figure CN224304334U_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of display technology, and in particular relates to a GOA driving circuit and display device. Background Technology
[0002] Integrating a gate driver on array (GOA) circuitry onto a glass substrate creates a scanning drive for the display panel. Compared to traditional gate chip-based driving techniques, GOA technology significantly reduces manufacturing costs and allows for smaller left and right bezels on the display panel. Each GOA driving module outputs a scan signal for each row, driving the pixel units in that row. Multiple GOA driving modules are cascaded to form a GOA driving circuit, enabling line-by-line scanning of the display panel.
[0003] The relevant GOA driver circuit requires two reset modules to reset the output terminal and pull-up control node of the GOA driver circuit respectively, resulting in a complex circuit structure, high cost and a large display panel bezel.
[0004] Therefore, the related GOA driving circuit has a complex structure, high cost, and a large display panel bezel. Summary of the Invention
[0005] The purpose of this application is to provide a GOA driving circuit and display device, which aims to solve the problems of complex structure, high cost and large bezel of the related GOA driving circuit.
[0006] This application provides a GOA driving circuit, including a pull-up module, an input module, a pull-down module, a pull-down sustaining module, an inverter module, and a reset module;
[0007] The input module is connected to the first input signal terminal and the pull-up control node;
[0008] The reset module is connected to a high-voltage power supply, a pull-down control node, and a reset signal terminal. It is used to output a reset control signal to the pull-down control node according to the reset signal under the excitation of the power supply voltage output by the high-voltage power supply.
[0009] The pull-up module is connected to the first clock signal terminal, the pull-up control node, and the output terminal of the GOA driver circuit.
[0010] The inverter module is connected to the high-voltage power supply, the second clock signal terminal, the pull-up control node, and the pull-down control node;
[0011] The pull-down sustaining module is connected to the output terminal of the pull-down control node, the pull-up control node, and the GOA drive circuit, and is used to pull down the output terminals of the pull-up control node and the GOA drive circuit to a low level according to the reset control signal;
[0012] The pull-down module is connected to the pull-up control node and the second input signal terminal.
[0013] In one embodiment, the input module is used to receive a first input signal and transmit the first input signal to the pull-up control node;
[0014] The input module includes a first transistor;
[0015] The drain and gate of the first transistor are connected to the first input signal terminal;
[0016] The source of the first transistor is connected to the pull-up control node.
[0017] In one embodiment, the pull-up module is used to receive a first clock signal, and in response to the high-level first clock signal and the high-level pull-up control node signal, outputs a high-level output signal from the output terminal of the GOA driver circuit;
[0018] The pull-up module includes a second transistor and a bootstrap capacitor;
[0019] The gate of the second transistor and the first terminal of the bootstrap capacitor are both connected to the pull-up control node;
[0020] The source of the second transistor and the second terminal of the bootstrap capacitor are both connected to the output terminal of the GOA driving circuit;
[0021] The drain of the second transistor is connected to the first clock signal terminal to receive the first clock signal.
[0022] In one embodiment, the pull-down sustaining module is further configured to maintain the output of the GOA drive circuit and the pull-up control node at a low level in response to a signal from the intermediate-level pull-down control node; the pull-down sustaining module includes a third transistor and a fourth transistor;
[0023] The drain of the third transistor is connected to the output terminal of the GOA driving circuit, the drain of the fourth transistor is connected to the pull-up control node, the gates of the third transistor and the fourth transistor are connected to the pull-down control node, the source of the fourth transistor is connected to the first low voltage source, and the source of the third transistor is connected to the second low voltage source, wherein the output voltage of the first low voltage source is less than the output voltage of the second low voltage source.
[0024] In one embodiment, the inverter module is used to invert the signal of the pull-up control node according to the second clock signal input to the second clock signal terminal under the excitation of the supply voltage, and output the inverted signal of the pull-up control node to the pull-down control node;
[0025] The inverter module includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and an eleventh transistor;
[0026] The gate of the fifth transistor is connected to the second clock signal terminal, and the drain of the eleventh transistor, the drain of the fifth transistor, and the drain of the seventh transistor are all connected to a high voltage source.
[0027] The gate of the sixth transistor and the gate of the eighth transistor are both connected to the pull-up control node;
[0028] The gate of the sixth transistor and the gate of the eighth transistor are connected to the first low voltage source.
[0029] The source of the fifth transistor is connected to the source of the eleventh transistor, the drain of the sixth transistor, and the gate of the seventh transistor.
[0030] The source of the seventh transistor and the drain of the eighth transistor are both connected to the pull-down control node;
[0031] The gate of the eleventh transistor is connected to the reset signal terminal to receive the reset signal.
[0032] In one embodiment, the pull-down module is used to receive a second input signal, and in response to a high-level second input signal, pulls the pull-up control node down to a low level;
[0033] The pull-down module includes a ninth transistor;
[0034] The drain of the ninth transistor is connected to the pull-down control node;
[0035] The drain of the ninth transistor is connected to the first low-voltage source;
[0036] The gate of the ninth transistor is connected to the second input signal terminal to receive the second input signal.
[0037] In one embodiment, the reset module includes a tenth transistor;
[0038] The gate and drain of the tenth transistor are both connected to the reset signal terminal to receive the reset signal.
[0039] The source of the tenth transistor is connected to the pull-down control node.
[0040] In one embodiment, the first input signal is the output signal of the GOA driving circuit in the upper k rows; the second input signal is the output signal of the GOA driving circuit in the lower k rows, where k is a positive integer.
[0041] In one embodiment, the reset signal is located before the output signal of the GOA driver circuit in the upper k rows and after the output signal of the GOA driver circuit in the lower k rows.
[0042] This invention also provides a display device, which includes the GOA driving circuit described above.
[0043] The beneficial effects of this invention compared to the prior art are as follows: Since the reset module outputs a reset control signal to the pull-down control node based on the reset signal, the pull-down sustaining module pulls down the output terminals of both the pull-up control node and the GOA drive circuit to a low level based on the reset control signal. Therefore, only one reset module is needed to achieve the reset function, simplifying the circuit structure, saving costs, and reducing the display panel bezel. Simultaneously, the inverter module connects to the high-voltage power supply, the second clock signal terminal, the pull-up control node, and the pull-down control node. Thus, the inverter module can invert the signal of the pull-up control node based on the second clock signal input to the second clock signal terminal. The transistors in the inverter module can periodically turn on and off based on the second clock signal, reducing the possibility of the transistors in the inverter module being on for extended periods, preventing device degradation, and extending the device's lifespan. Attached Figure Description
[0044] To more clearly illustrate the technical inventions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0045] Figure 1 A schematic diagram of a GOA driving circuit provided in an embodiment of this application;
[0046] Figure 2 Waveform diagrams of various signals of a GOA driving circuit provided in an embodiment of this application;
[0047] Figure 3 This is a partial example circuit schematic diagram of a GOA driving circuit provided in an embodiment of this application. Detailed Implementation
[0048] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.
[0049] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.
[0050] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0051] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0052] Figure 1 A schematic diagram of the GOA driving circuit provided in a preferred embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are described in detail below:
[0053] The aforementioned GOA drive circuit includes a pull-up module 10, an input module 20, a pull-down module 30, a pull-down sustaining module 40, an inverter module 50, and a reset module 60.
[0054] Input module 20 is connected to the first input signal terminal and the pull-up control node Qn.
[0055] The reset module 60 is connected to the high-voltage power supply VGH, the pull-down control node Kn, and the reset signal terminal. It is used to output a reset control signal to the pull-down control node Kn according to the reset signal RESET under the excitation of the power supply voltage output by the high-voltage power supply VGH.
[0056] Pull-up module 10 is connected to the first clock signal terminal, the pull-up control node Qn, and the output terminal of the GOA drive circuit.
[0057] The inverter module 50 is connected to the high-voltage power supply VGH, the second clock signal terminal, the pull-up control node Qn, and the pull-down control node Kn.
[0058] The pull-down sustaining module 40 is connected to the pull-down control node Kn, the pull-up control node Qn, and the output of the GOA driver circuit. It is used to maintain the output of both the pull-up control node Qn and the GOA driver circuit at a low level according to the reset control signal.
[0059] The pull-down module 30 is connected to the pull-up control node Qn and the second input signal terminal.
[0060] In a specific implementation, the input module 20 is used to access the first input signal Gn-k and transmit the first input signal Gn-k to the pull-up control node Qn.
[0061] The pull-up module 10 is used to receive the first clock signal CLK, and in response to the high-level first clock signal CLK and the high-level pull-up control node Qn, it outputs a high-level output signal Gn from the output terminal of the GOA driver circuit.
[0062] The pull-down sustaining module 40 is also used to maintain the output of the GOA drive circuit and the pull-up control node Qn at a low level in response to the signal of the pull-down control node Kn at the intermediate level.
[0063] The inverter module 50, under the excitation of the supply voltage, inverts the signal of the pull-up control node Qn according to the second clock signal XCLK input to the second clock signal terminal, and outputs the inverted signal of the pull-up control node Qn to the pull-down control node Kn. It should be noted that the second clock signal is the inverted signal of the first clock signal.
[0064] The pull-down module 30 is used to receive the second input signal Gn+k, and in response to the high level of the second input signal Gn+k, it pulls down the pull-up control node Qn to a low level.
[0065] Figure 2 The waveforms of various signals in the GOA drive circuit are shown below. Figure 2 right Figure 1 The principle of the GOA driving circuit shown will be further explained:
[0066] Before stage A, the reset signal RESET, the first clock signal CLK, the first input signal Gn-k, and the second input signal Gn+k are all at low levels; the second clock signal XCLK is at a high level; the pull-down module 30 is turned off according to the low-level second input signal Gn+k, and the input module 20 transmits the low-level first input signal Gn-k to the pull-up control node Qn. The pull-up control node Qn is at a low level. Under the excitation of the power supply voltage, the inverter module 50 inverts the low-level signal of the pull-up control node Qn according to the second clock signal XCLK, and outputs the inverted signal (high level) to the pull-down control node Kn. At the same time, the reset module 60 stops outputting the high-level reset control signal to the pull-down control node Kn, and the pull-down control node Kn is at an intermediate level. Thus, the pull-down maintenance module 40 is in the open state, and maintains the output of the pull-up control node Qn and the GOA drive circuit at a low level according to the intermediate level signal. The output of the GOA drive circuit outputs a low-level output signal Gn.
[0067] During phase A to B, the second clock signal XCLK and the first input signal Gn-k are at high levels, while the reset signal RESET, the first clock signal CLK, and the second input signal Gn+k are all at low levels. The pull-down module 30 is turned off based on the low-level second input signal Gn+k. The input module 20 transmits the high-level first input signal Gn-k to the pull-up control node Qn, making the pull-up control node Qn high (first voltage). Under the excitation of the supply voltage, the inverter module 50 responds to the high-level signal of the pull-up control node Qn based on the second clock signal XCLK. The signal is inverted and the inverted signal (low level) is output to the pull-down control node Kn. At the same time, the reset module 60 stops outputting the high-level reset control signal to the pull-down control node Kn, and the pull-down control node Kn is low level, so the pull-down maintenance module 40 is in the off state. The pull-up module 10 receives the low-level first clock signal CLK and responds to the high-level pull-up control node Qn signal, transmitting the low-level first clock signal CLK to the output of the GOA driver circuit. The output of the GOA driver circuit outputs the low-level output signal Gn.
[0068] During phases B to C, the first clock signal CLK is high, while the second clock signal XCLK, the first input signal Gn-k, the reset signal RESET, and the second input signal Gn+k are all low. The pull-down module 30 shuts down based on the low-level second input signal Gn+k, the input module 20 shuts down based on the low-level first input signal Gn-k, the pull-up control node Qn remains high, and the inverter module 50, under the excitation of the supply voltage, inverts the high-level signal of the pull-up control node Qn according to the second clock signal XCLK, and outputs the inverted signal (low level) to the pull-down control node Kn. Simultaneously, the reset signal... Bit module 60 stops outputting a high-level reset control signal to the pull-down control node Kn, and the pull-down control node Kn is at a low level, thus the pull-down sustaining module 40 is in the off state. The pull-up module 10 receives a high-level first clock signal CLK and, in response to the high-level signal of the pull-up control node Qn, transmits the high-level first clock signal CLK to the output of the GOA driver circuit. It is worth noting that, due to the bootstrap effect of the capacitor in the pull-up module 10, the high level maintained by the pull-up control node Qn is the second voltage, where the second voltage is greater than the first voltage. The output of the GOA driver circuit outputs a high-level output signal Gn.
[0069] During stages C to D, the second input signal Gn+k, the reset signal RESET, the first clock signal CLK, and the first input signal Gn-k are all at low levels; the second clock signal XCLK is at a high level; the pull-down module 30 is turned off according to the low-level second input signal Gn+k, the input module 20 is turned off according to the low-level first input signal Gn-k, the pull-up control node Qn remains at a high level, and the inverter module 50, under the excitation of the supply voltage, inverts the high-level signal of the pull-up control node Qn according to the second clock signal XCLK, and outputs the inverted signal (low level) to the pull-down control node. Simultaneously, the reset module 60 stops outputting a high-level reset control signal to the pull-down control node Kn, and the pull-down control node Kn is at a low level, thus the pull-down maintenance module 40 is in a closed state. The pull-up module 10 receives a low-level first clock signal CLK and, in response to the high-level pull-up control node Qn, transmits the low-level first clock signal CLK to the output of the GOA driver circuit. It is worth noting that, since the capacitor in the pull-up module 10 is no longer self-bootstrapping, the high level maintained by the pull-up control node Qn is the first voltage, and the output of the GOA driver circuit outputs a low-level output signal Gn.
[0070] During stages D to E, the second clock signal XCLK and the second input signal Gn+k are at high levels, while the reset signal RESET, the first clock signal CLK, and the first input signal Gn-k are all at low levels. Input module 20 transmits the low-level first input signal Gn-k to the pull-up control node Qn, and pull-down module 30 connects to the high-level second input signal Gn+k. In response to the high-level second input signal Gn+k, it pulls up control node Qn down to a low level. Under the excitation of the power supply voltage, inverter module 50 inverts the low-level signal of pull-up control node Qn according to the second clock signal XCLK and outputs the inverted signal (high level) to pull-down control node Kn. At the same time, reset module 60 stops outputting the high-level reset control signal to pull-down control node Kn, and pull-down control node Kn is at an intermediate level. Thus, pull-down maintenance module 40 is in the enabled state, and according to the intermediate level signal, it maintains both pull-up control node Qn and the output of GOA drive circuit at a low level. The output of GOA drive circuit outputs a low-level output signal Gn.
[0071] In stages E to F, the working principle of the GOA drive circuit is the same as in the stages before A, and will not be repeated here.
[0072] During phases F to G, the second clock signal XCLK and the reset signal RESET are high, while the first clock signal CLK, the first input signal Gn-k, and the second input signal Gn+k are low. The pull-down module 30 is turned off based on the low-level second input signal Gn+k. The input module 20 transmits the low-level first input signal Gn-k to the pull-up control node Qn. Since the pull-up control node Qn is low, the inverter module 50, driven by the power supply voltage output from the high-voltage power supply VGH, inverts the low-level signal of the pull-up control node Qn according to the second clock signal XCLK, and then outputs the inverted signal (high level). The output is sent to the pull-down control node Kn. At the same time, under the excitation of the power supply voltage, the reset module 60 outputs a high-level reset control signal to the pull-down control node Kn according to the high-level reset signal RESET. The pull-down control node Kn is at a high level, so the pull-down sustaining module 40 is in a strongly enabled state. According to the high-level reset control signal, the output terminals of the pull-up control node Qn and the GOA drive circuit are both pulled down to a low level. Since the pull-down sustaining module 40 is in a strongly enabled state, the output terminals of the pull-up control node Qn and the GOA drive circuit are effectively reset, and the output terminal of the GOA drive circuit outputs a low-level output signal Gn.
[0073] It is worth emphasizing that the first input signal Gn-k is the output signal Gn of the GOA driving circuit in the kth row above; the second input signal Gn+k is the output signal Gn of the GOA driving circuit in the kth row below.
[0074] It is understandable that k is a positive integer.
[0075] It should be noted that the reset signal RESET is located before the output signal Gn of the GOA driver circuit in the upper k rows and after the output signal Gn of the GOA driver circuit in the lower k rows.
[0076] Setting the RESET signal between the output signals Gn of the upper k-line GOA drive circuit and the lower k-line GOA drive circuit allows the GOA drive circuit to be reset during the scanning interval, thereby releasing excess charge in the GOA drive circuit and enabling it to enter a stable operating state, thus improving the stability and reliability of the GOA drive circuit.
[0077] Figure 3 The diagram illustrates a partial example circuit structure of the GOA driving circuit provided in an embodiment of the present invention. For ease of explanation, only the parts relevant to the embodiment of the present invention are shown, and are described in detail below:
[0078] The input module 20 includes a first transistor T1; the drain and gate of the first transistor T1 are connected to the first input signal terminal; the source of the first transistor T1 is connected to the pull-up control node Qn.
[0079] The pull-up module 10 includes a second transistor T2 and a bootstrap capacitor C1.
[0080] The gate of the second transistor T2 and the first terminal of the bootstrap capacitor C1 are connected to the pull-up control node Qn; the source of the second transistor T2 and the second terminal of the bootstrap capacitor C1 are connected to the output terminal of the GOA driving circuit; the drain of the second transistor T2 is connected to the first clock signal terminal to receive the first clock signal CLK.
[0081] The pull-down sustaining module 40 includes a third transistor T3 and a fourth transistor T4.
[0082] The drain of the third transistor T3 is connected to the output of the GOA drive circuit, the drain of the fourth transistor T4 is connected to the pull-up control node Qn, the gates of the third transistor T3 and the fourth transistor T4 are connected to the pull-down control node Kn, the source of the fourth transistor is connected to the first low voltage source VSSQ, and the source of the third transistor is connected to the second low voltage source VSSG. The output voltage of the first low voltage source VSSQ is less than the output voltage of the second low voltage source VSSG.
[0083] It is understandable that the output voltage of the first low voltage source VSSQ is less than the output voltage of the second low voltage source VSSG. Therefore, when the pull-down sustaining module 40 maintains the output terminal of the GOA drive circuit and the pull-up control node Qn at a low level or pulls them down to a low level, the voltage at the output terminal of the GOA drive circuit is greater than the voltage at the pull-up control node. The gate-source voltage of the second transistor T2 in the pull-up circuit 10 is negative, and the second transistor T2 is completely cut off, reducing the possibility of leakage current.
[0084] The inverter module 50 includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and an eleventh transistor T11.
[0085] The gate of the fifth transistor is connected to the second clock signal terminal. The drain of the eleventh transistor T11, the drain of the fifth transistor T5, and the drain of the seventh transistor T7 are all connected to the high voltage source VGH. The gate of the sixth transistor T6 and the gate of the eighth transistor T8 are all connected to the pull-up control node Qn. The gate of the sixth transistor T6 and the gate of the eighth transistor T8 are all connected to the first low voltage source VSSQ. The source of the fifth transistor T5 is connected to the source of the eleventh transistor T11, the drain of the sixth transistor T6, and the gate of the seventh transistor T7. The source of the seventh transistor T7 and the drain of the eighth transistor T8 are all connected to the pull-down control node Kn. The gate of the eleventh transistor T11 is connected to the reset signal terminal to receive the reset signal RESET.
[0086] By setting the eleventh transistor T11, the gate of the seventh transistor T7 can jump to a high level when a reset signal is input, thereby turning on the seventh transistor T7 and transmitting the high-level signal of the high voltage source VGH to the pull-down control node Kn; thus improving the reset effect and the reliability of the reset function.
[0087] The fifth transistor T5 in the inverter module can be periodically turned on and off according to the second clock signal, which reduces the possibility of the fifth transistor T5 being turned on for a long time, prevents device degradation, and extends the device's lifespan.
[0088] The pull-down module 30 includes a ninth transistor T9.
[0089] The drain of the ninth transistor T9 is connected to the pull-down control node Kn; the drain of the ninth transistor T9 is connected to the first low voltage source VSSQ; the gate of the ninth transistor T9 is connected to the second input signal terminal to receive the second input signal Gn+k.
[0090] The reset module 60 includes the tenth transistor T10.
[0091] The gate and drain of the tenth transistor T10 are connected to the reset signal terminal to receive the reset signal RESET; the source of the tenth transistor T10 is connected to the pull-down control node Kn.
[0092] Understandably, the reset module 60 uses only one transistor to achieve the reset function, making the circuit simple, reliable, and low-cost.
[0093] It should be noted that the first transistor T1 to the tenth transistor T10 mentioned above can all be NMOS transistors.
[0094] The following combination Figure 2 right Figure 3 The working principle shown will be further explained as follows:
[0095] Before stage A, the second clock signal XCLK is high, while the reset signal RESET, the first clock signal CLK, the first input signal Gn-k, and the second input signal Gn+k are all low. The ninth transistor T9 is turned off based on the low-level second input signal Gn+k, the eleventh transistor T11 is turned off, the gate of the fifth transistor T5 is connected to the high-level second clock signal XCLK, and the drain of the fifth transistor T5 transmits the high-level signal output from the high-voltage source VGH to the source of the fifth transistor T5. The gate of the first transistor T1 is connected to the low-level first input signal Gn-k, the first transistor T1 is turned off, and the pull-up control node Qn is low. Therefore, the sixth transistor T6 and the eighth transistor T8 are turned off, the seventh transistor T7 is turned on, and the seventh transistor T7 outputs the high-level signal from the high-voltage source VGH to the pull-down control node Kn. At the same time, the gate of the tenth transistor T10 is connected to the low-level reset signal RESET, and the tenth transistor T10 is turned off, so that the pull-down control node Kn jumps from the high level to the intermediate level. Thus, the third transistor T3 and the fourth transistor T4 are turned on, so that the pull-up control node Qn is connected to the first low-voltage source VSSQ and the output terminal of the GOA drive circuit is connected to the second low-voltage source VSSG. The output terminal of the GOA drive circuit outputs a low-level output signal Gn.
[0096] During phases A to B, the second clock signal XCLK and the first input signal Gn-k are high, while the reset signal RESET, the first clock signal CLK, and the second input signal Gn+k are all low. The ninth transistor T9 turns off based on the low-level second input signal Gn+k, the eleventh transistor T11 turns off, the gate of the fifth transistor T5 is connected to the high-level second clock signal XCLK, and the drain of the fifth transistor T5 transmits the high-level signal output from the high-voltage source VGH to the source of the fifth transistor T5. The seventh transistor T7 turns on. The gate of the first transistor T1 is connected to the high-level first input signal Gn-k, and the drain of the first transistor T1 transmits the high-level first input signal Gn+k to the source of the first transistor T1. Signal Gn-k is transmitted to the source of the first transistor T1, the pull-up control node Qn is high (first voltage) and the bootstrap capacitor C1 is charged. Therefore, the sixth transistor T6 and the eighth transistor T8 are turned on and pull down the pull-down control node Kn to a low level. At the same time, the gate of the tenth transistor T10 is connected to the low-level reset signal RESET, and the tenth transistor T10 is turned off. Thus, the third transistor T3 and the fourth transistor T4 are in the off state. The second transistor T2 is turned on according to the high-level pull-up control node Qn and transmits the low-level first clock signal CLK to the output of the GOA driver circuit. The output of the GOA driver circuit outputs a low-level output signal Gn.
[0097] In stages B to C, the first clock signal CLK is high, while the second clock signal XCLK, the first input signal Gn-k, the reset signal RESET, and the second input signal Gn+k are all low. The ninth transistor T9 turns off due to the low-level second input signal Gn+k, the eleventh transistor T11 turns off, the gate of the fifth transistor T5 is low to the second clock signal XCLK, the drain of the fifth transistor T5 stops transmitting the high-level signal output from the high-voltage source VGH to the source of the fifth transistor T5, and the seventh transistor T7 turns off. The gate of the first transistor T1 is connected to the low-level first input signal Gn-k, and the first transistor T1 turns off. Because the bootstrap capacitor C1 was charged and stored energy in the previous stage, the... When the pull-up control node Qn is high, the sixth transistor T6 and the eighth transistor T8 turn on, pulling the pull-down control node Kn down to a low level. At the same time, the gate of the tenth transistor T10 is connected to a low-level reset signal RESET, and the tenth transistor T10 turns off. Thus, the third transistor T3 and the fourth transistor T4 are in the off state. The second transistor T2 turns on according to the high-level pull-up control node Qn signal and transmits the high-level first clock signal CLK to the output of the GOA driver circuit. Due to the bootstrap effect of the bootstrap capacitor C1, the pull-up control node Qn is raised to the high level of the second voltage, where the second voltage is greater than the first voltage. The output of the GOA driver circuit outputs a high-level output signal Gn.
[0098] During stages C to D, the first clock signal CLK, the first input signal Gn-k, the reset signal RESET, and the second input signal Gn+k are all at low levels, while the second clock signal XCLK is at a high level. The ninth transistor T9 is turned off due to the low-level second input signal Gn+k, the eleventh transistor T11 is turned off, the gate of the fifth transistor T5 is connected to the high-level second clock signal XCLK, and the drain of the fifth transistor T5 transmits the high-level signal output from the high-voltage source VGH to the source of the fifth transistor T5, turning on the seventh transistor T7. The gate of the first transistor T1 is connected to the low-level first input signal Gn-k, turning off the first transistor T1. Due to the energy stored in the bootstrap capacitor C1 in the previous stage, the pull-up control node Qn is at a high level, therefore the sixth transistor T6 and the eighth transistor... When transistor T8 is turned on, it pulls the pull-down control node Kn down to a low level. At the same time, the gate of the tenth transistor T10 is connected to a low-level reset signal RESET, and the tenth transistor T10 is turned off. As a result, the third transistor T3 and the fourth transistor T4 are turned on according to the high-level pull-up control node Qn signal, so that the pull-up control node Qn is connected to the first low voltage source VSSQ and the output of the GOA drive circuit is connected to the second low voltage source VSSG. The second transistor T2 is turned on according to the high-level pull-up control node Qn signal and transmits the low-level first clock signal CLK to the output of the GOA drive circuit. Since the bootstrap capacitor C1 is no longer bootstrapping at this time, the pull-up control node Qn is at the high level of the first voltage, and the output of the GOA drive circuit outputs a low-level output signal Gn.
[0099] During stages D to E, the second clock signal XCLK and the second input signal Gn+k are high, while the reset signal RESET, the first clock signal CLK, and the first input signal Gn-k are all low. The gate of the fifth transistor T5 is connected to the high-level second clock signal XCLK, the eleventh transistor T11 is turned off, the drain of the fifth transistor T5 transmits the high-level signal output from the high-voltage source VGH to the source of the fifth transistor T5, the gate of the first transistor T1 is connected to the low-level first input signal Gn-k, the first transistor T1 is turned off, and the ninth transistor T9 is turned on according to the high-level second input signal Gn+k, and pulls the pull-up control node Qn down to low. When the voltage level is low, transistors T6 and T8 are turned off, transistor T7 is turned on, and transistor T7 outputs a high-level signal from the high-voltage source VGH to the pull-down control node Kn. At the same time, the gate of transistor T10 is connected to a low-level reset signal RESET, and transistor T10 is turned off, causing the pull-down control node Kn to jump from a high level to an intermediate level. This causes transistors T3 and T4 to be turned on, so that the pull-up control node Qn is connected to the first low-voltage source VSSQ and the output of the GOA drive circuit is connected to the second low-voltage source VSSG. The output of the GOA drive circuit outputs a low-level output signal Gn.
[0100] In stages E to F, the working principle of the GOA drive circuit is the same as in the stages before A, and will not be repeated here.
[0101] During stages F to G, the second clock signal XCLK and the reset signal RESET are high, while the first clock signal CLK, the first input signal Gn-k, and the second input signal Gn+k are low. The ninth transistor T9 is turned off based on the low-level second input signal Gn+k. The gate of the fifth transistor T5 is connected to the high-level second clock signal XCLK, and the drain of the fifth transistor T5 transmits the high-level signal output from the high-voltage source VGH to the source of the fifth transistor T5. The eleventh transistor T11 is turned on based on the high-level reset signal STV and transmits the high-level signal output from the high-voltage source VGH to the source of the fifth transistor T5. The gate of the first transistor T1 is connected to the low-level first input signal Gn-k, and the first transistor T1 is turned off. The pull-up control node Qn is low, therefore the sixth transistor T6 and the eighth transistor T8 are turned off, and the seventh transistor T7... When the high-voltage source VGH is output by the seventh transistor T7, the high-level signal is output to the pull-down control node Kn. At the same time, the gate of the tenth transistor T10 is connected to the high-level reset signal RESET. The drain of the tenth transistor T10 transmits the supply voltage output by the high-voltage power supply VGH to the source of the tenth transistor T10 (pull-down control node Kn), causing the pull-down control node Kn to jump from the intermediate level to the high level. As a result, the third transistor T3 and the fourth transistor T4 are in a strongly enabled state, so that the pull-up control node Qn is connected to the first low-voltage source VSSQ and the output of the GOA drive circuit is connected to the second low-voltage source VSSG. Since the third transistor T3 and the fourth transistor T4 are in a strongly enabled state, the pull-up control node Qn and the output of the GOA drive circuit are effectively reset, and the output of the GOA drive circuit outputs a low-level output signal Gn.
[0102] This invention also provides a display device, which includes the GOA driving circuit described above.
[0103] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.
[0104] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.
Claims
1. A GOA driving circuit, characterized in that, It includes a pull-up module, an input module, a pull-down module, a pull-down holding module, an inverter module, and a reset module; The input module is connected to the first input signal terminal and the pull-up control node; The reset module is connected to a high-voltage power supply, a pull-down control node, and a reset signal terminal. It is used to output a reset control signal to the pull-down control node according to the reset signal under the excitation of the power supply voltage output by the high-voltage power supply. The pull-up module is connected to the first clock signal terminal, the pull-up control node, and the output terminal of the GOA driver circuit. The inverter module is connected to the high-voltage power supply, the second clock signal terminal, the pull-up control node, and the pull-down control node; The pull-down sustaining module is connected to the output terminal of the pull-down control node, the pull-up control node, and the GOA drive circuit, and is used to pull down the output terminals of the pull-up control node and the GOA drive circuit to a low level according to the reset control signal; The pull-down module is connected to the pull-up control node and the second input signal terminal.
2. The GOA driving circuit as described in claim 1, characterized in that, The input module is used to receive a first input signal and transmit the first input signal to the pull-up control node; The input module includes a first transistor; The drain and gate of the first transistor are connected to the first input signal terminal; The source of the first transistor is connected to the pull-up control node.
3. The GOA driving circuit as described in claim 1, characterized in that, The pull-up module is used to receive the first clock signal, and in response to the high-level first clock signal and the high-level pull-up control node signal, it outputs a high-level output signal from the output terminal of the GOA driver circuit. The pull-up module includes a second transistor and a bootstrap capacitor; The gate of the second transistor and the first terminal of the bootstrap capacitor are both connected to the pull-up control node; The source of the second transistor and the second terminal of the bootstrap capacitor are both connected to the output terminal of the GOA driving circuit; The drain of the second transistor is connected to the first clock signal terminal to receive the first clock signal.
4. The GOA driving circuit as described in claim 1, characterized in that, The pull-down sustaining module is also used to maintain the output of the GOA drive circuit and the pull-up control node at a low level in response to the signal of the intermediate-level pull-down control node; the pull-down sustaining module includes a third transistor and a fourth transistor; The drain of the third transistor is connected to the output terminal of the GOA driving circuit, the drain of the fourth transistor is connected to the pull-up control node, the gates of the third transistor and the fourth transistor are connected to the pull-down control node, the source of the fourth transistor is connected to the first low voltage source, and the source of the third transistor is connected to the second low voltage source, wherein the output voltage of the first low voltage source is less than the output voltage of the second low voltage source.
5. The GOA driving circuit as described in claim 1, characterized in that, The inverter module is used to invert the signal of the pull-up control node according to the second clock signal input to the second clock signal terminal under the excitation of the power supply voltage, and output the inverted signal of the pull-up control node to the pull-down control node. The inverter module includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and an eleventh transistor; The gate of the fifth transistor is connected to the second clock signal terminal, and the drain of the eleventh transistor, the drain of the fifth transistor, and the drain of the seventh transistor are all connected to a high voltage source. The gate of the sixth transistor and the gate of the eighth transistor are both connected to the pull-up control node; The gate of the sixth transistor and the gate of the eighth transistor are connected to the first low voltage source. The source of the fifth transistor is connected to the source of the eleventh transistor, the drain of the sixth transistor, and the gate of the seventh transistor. The source of the seventh transistor and the drain of the eighth transistor are both connected to the pull-down control node; The gate of the eleventh transistor is connected to the reset signal terminal to receive the reset signal.
6. The GOA driving circuit as described in claim 1, characterized in that, The pull-down module is used to receive a second input signal, and in response to a high-level second input signal, it pulls the pull-up control node down to a low level; The pull-down module includes a ninth transistor; The drain of the ninth transistor is connected to the pull-down control node; The drain of the ninth transistor is connected to the first low-voltage source; The gate of the ninth transistor is connected to the second input signal terminal to receive the second input signal.
7. The GOA driving circuit as described in claim 1, characterized in that, The reset module includes a tenth transistor; The gate and drain of the tenth transistor are both connected to the reset signal terminal to receive the reset signal. The source of the tenth transistor is connected to the pull-down control node.
8. The GOA driving circuit as described in any one of claims 1 to 7, characterized in that, The first input signal is the output signal of the GOA driving circuit in the upper k rows; the second input signal is the output signal of the GOA driving circuit in the lower k rows, where k is a positive integer.
9. The GOA driving circuit as described in claim 8, characterized in that, The reset signal is located before the output signal of the GOA driver circuit in the upper k rows and after the output signal of the GOA driver circuit in the lower k rows.
10. A display device, characterized in that, The display device includes the GOA driving circuit as described in any one of claims 1 to 9.