Gate drive circuit

Abstract

The application provides a gate drive circuit, belonging to the technical field of display. An inverter module obtains an n-level reverse signal according to a reference high potential signal and an n-level control signal. A drift mitigation module is connected with the inverter module and outputs an n-level switching signal according to the n-level reverse signal and a local clock signal. A pull-down maintenance module is connected with the drift mitigation module and a pull-up module, and is used for pulling down and maintaining the potential of the n-level control signal to a reference low potential and pulling down and maintaining the potential of an n-level gate drive signal to the reference low potential according to the n-level switching signal. According to the n-level reverse signal and the local clock signal, the drift mitigation module in the circuit can make the potential of the n-level switching signal switch with the high and low of the local clock signal, weaken the forward bias effect of the transistor in the pull-down maintenance module, and solve the problem of forward drift of threshold voltage (Vth) caused by the long-time opening of the transistor in the pull-down maintenance module.

Description

Technical Field

[0001] This application belongs to the field of display technology, and in particular relates to a gate driving circuit. Background Technology

[0002] The Gate Driver on Array (GOA) circuit integrates the gate driver circuit of the display panel onto the glass substrate, forming a scanning driver for the display panel. The GOA driving circuit significantly reduces manufacturing costs and allows for a reduction in the bezel size of the display panel.

[0003] In traditional circuits, the thin-film transistor (TFT) in the pull-down sustaining module is kept on for a long time, which causes the threshold voltage (Vth) of the TFT to drift forward quickly, which can easily lead to the failure of the pull-down sustaining function and cause abnormalities in the GOA driving circuit. Utility Model Content

[0004] The purpose of this application is to provide a gate drive circuit that aims to solve the problem of pull-down sustaining function failure caused by the rapid positive drift of the threshold voltage of the thin-film transistor in the pull-down sustaining module of a conventional circuit.

[0005] This application provides a gate driving circuit, including a multi-stage sub-driving circuit connected in cascades, wherein the nth stage sub-driving circuit includes:

[0006] The pull-up control module is used to output the nth-level control signal based on the (n-3)th-level gate drive signal of the (n-3)th-level sub-drive circuit; where n is an integer greater than 3.

[0007] A pull-up module, connected to the pull-up control module, is used to output the nth-stage gate drive signal according to the nth-stage control signal and the nth-stage clock signal;

[0008] An inverter module is used to obtain an nth-stage inverted signal based on a reference high-potential signal and the nth-stage control signal.

[0009] A drift mitigation module, connected to the inverter module, is used to output an nth-stage switching signal based on the nth-stage inverted signal and the local clock signal.

[0010] A pull-down sustaining module, connected to the drift mitigation module and the pull-up module, is used to pull down and maintain the potential of the nth stage control signal to a reference low potential according to the nth stage switching signal, and to pull down and maintain the potential of the nth stage gate drive signal to the reference low potential.

[0011] In one embodiment, the nth-level sub-driving circuit further includes:

[0012] A pull-down module, connected to the pull-up module, is used to pull down the potential of the nth stage control signal to the reference low potential according to the gate drive signal of the (n+4)th stage of the (n+4)th stage sub-drive circuit.

[0013] In one embodiment, the nth-level sub-driving circuit further includes:

[0014] A reset module, connected to the pull-up module, is used to reset the potentials of the nth stage control signal and the nth stage gate drive signal to the reference low potential according to the reset signal during the reset time.

[0015] In one embodiment, the inverter module includes:

[0016] A first transistor, wherein a first terminal and a second terminal of the first transistor are connected, is used to acquire the reference high potential signal;

[0017] The second transistor has a first terminal connected to the third terminal of the first transistor. The second terminal of the second transistor is used to acquire the reference high-potential signal, and the third terminal of the second transistor is used to output the nth-level inverted signal.

[0018] The third transistor has a first terminal for acquiring the nth stage control signal, a second terminal for being connected to the first terminal of the second transistor, and a third terminal for acquiring the reference low potential.

[0019] A fourth transistor, wherein the first terminal of the fourth transistor is used to acquire the nth stage control signal, the second terminal of the fourth transistor is connected to the third terminal of the second transistor, and the third terminal of the fourth transistor is used to acquire the reference low potential.

[0020] In one embodiment, the drift mitigation module includes:

[0021] The fifth transistor has a first terminal for acquiring the nth-stage inverted signal, a second terminal for acquiring the local clock signal, and a third terminal for outputting the nth-stage switching signal.

[0022] In one embodiment, the pull-down sustaining module includes:

[0023] A sixth transistor, wherein the first terminal of the sixth transistor is used to acquire the nth stage switching signal, the second terminal of the sixth transistor is used to acquire the nth stage control signal, and the third terminal of the sixth transistor is used to acquire the reference low potential;

[0024] A seventh transistor, wherein the first terminal of the seventh transistor is used to acquire the nth stage switching signal, the second terminal of the seventh transistor is used to acquire the nth stage gate drive signal, and the third terminal of the seventh transistor is used to acquire the reference low potential.

[0025] In one embodiment, the pull-up control module includes:

[0026] The eighth transistor has its first and second terminals connected to acquire the (n-3)th stage gate drive signal, and its third terminal is used to output the nth stage control signal.

[0027] In one embodiment, the pull-up module includes:

[0028] The ninth transistor has a first terminal for acquiring the nth-stage control signal, a second terminal for acquiring the nth-stage clock signal, and a third terminal for outputting the nth-stage gate drive signal.

[0029] A capacitor, one end of which is connected to the first terminal of the ninth transistor, and the other end of which is connected to the third terminal of the ninth transistor.

[0030] In one embodiment, the dropdown module includes:

[0031] The tenth transistor has a first terminal for acquiring the (n+4)th stage gate drive signal, a second terminal for acquiring the nth stage control signal, and a third terminal for acquiring the reference low potential.

[0032] In one embodiment, the reset module includes:

[0033] The eleventh transistor has a first terminal for acquiring the reset signal, a second terminal for acquiring the nth gate drive signal, and a third terminal for acquiring the reference low potential.

[0034] The twelfth transistor has a first terminal for acquiring the reset signal, a second terminal for acquiring the nth stage control signal, and a third terminal for acquiring the reference low potential.

[0035] The beneficial effects of this utility model embodiment compared with the prior art are:

[0036] The nth-level gate drive signal Gn output by the nth-level sub-driver circuit can drive the pixel units in one row. Multiple sub-driver circuits are cascaded to form a gate drive circuit. Furthermore, gate drive signals are passed between these multiple sub-driver circuits. The (n-3)th-level gate drive signal Gn-3 of the (n-3)th-level sub-driver circuit is input to the pull-up control module as the start signal for the current nth-level sub-driver circuit. The pull-up control module outputs the nth-level control signal Qn based on the (n-3)th-level gate drive signal Gn-3 to activate the pull-up module. Then, the pull-up module outputs the nth-level gate drive signal Gn based on the nth-level control signal Qn and the nth-level clock signal CLK. Both the nth-level control signal Qn and the nth-level gate drive signal Gn are signals from the current nth-level sub-driver circuit.

[0037] The nth-stage control signal Qn serves as the main input signal of the inverter module. The nth-stage inverted signal Kn serves as the output signal of the inverter module. The inverter module reverses the nth-stage control signal Qn and the nth-stage inverted signal Kn; that is, when the nth-stage control signal Qn is high, the nth-stage inverted signal Kn is low, and vice versa.

[0038] The inverter module charges the transistors in the inverter module according to the reference high-level signal VGH, causing the nth-stage inverting signal Kn to become high, thus controlling the drift mitigation module to start working. The drift mitigation module, based on the nth-stage inverting signal Kn and the local clock signal CLKm-1, causes the potential of the nth-stage switching signal Pn to switch high and low with the local clock signal CLKm-1, reducing the forward bias effect on the transistors in the pull-down sustaining module. This solves the problem of forward drift of the threshold voltage (Vth) caused by the transistors being in the on state for a long time in the pull-down sustaining module, extending the lifespan of each transistor. Furthermore, the pull-down sustaining module, based on the nth-stage switching signal Pn, can switch high and low with the local clock signal CLKm-1, pulling down and maintaining the potential of the nth-stage control signal Qn to the reference low-level VSS, and also pulling down and maintaining the potential of the nth-stage gate drive signal Gn to the reference low-level VSS, ensuring the gate drive circuit can guarantee the function of the pull-down sustaining module. Therefore, the gate drive circuit provided in this application can more stably and reliably turn the thin-film transistors of the display panel on or off normally, avoiding abnormalities in the gate drive circuit. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or exemplary technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 The circuit structure diagrams of the gate drive circuits in some embodiments provided in this application are shown.

[0041] Figure 2 The circuit connection diagram of the inverter module and the drift mitigation module in some embodiments provided in this application is shown.

[0042] Figure 3 The circuit connection structure diagram of the pull-down sustaining module is shown in some embodiments provided in this application.

[0043] Figure 4 The circuit connection structure diagram of the pull-up control module and the pull-up module in some embodiments provided in this application is shown.

[0044] Figure 5 The circuit connection structure diagram of the pull-down module and the reset module in some embodiments provided in this application is shown.

[0045] Figure 6 The following are schematic diagrams of signal input waveforms in some embodiments provided in this application. Detailed Implementation

[0046] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0047] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0048] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0049] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. Additionally, in the embodiments of this application, the terms "first" and "second" are used to distinguish identical or similar items that have substantially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or order of execution, and that "first" and "second" do not necessarily imply difference.

[0050] In the description of this application, unless otherwise stated, " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B can mean A or B. "And / or" in this application is merely a description of the relationship between the related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone, where A and B can be singular or plural. Furthermore, in the description of this application, unless otherwise stated, "multiple" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0051] Please see Figure 1 This application provides a gate driving circuit. The gate driving circuit includes cascaded multi-stage sub-driving circuits. The nth stage sub-driving circuit includes a pull-up control module 10, a pull-up module 20, an inverter module 30, a drift mitigation module 40, and a pull-down sustaining module 50. The pull-up control module 10 is used to output a nth stage control signal Qn according to the (n-3)th stage gate driving signal Gn-3 of the (n-3)th stage sub-driving circuit.

[0052] Pull-up module 20 is connected to pull-up control module 10 and is used to output the nth-stage gate drive signal Gn based on the nth-stage control signal Qn and the nth-stage clock signal CLK. Inverter module 30 is used to obtain the nth-stage inverted signal Kn based on the reference high-level signal VGH and the nth-stage control signal Qn. Drift mitigation module 40 is connected to inverter module 30 and is used to output the nth-stage switching signal Pn based on the nth-stage inverted signal Kn and the local clock signal CLKm-1.

[0053] The pull-down sustaining module 50 is connected to the drift mitigation module 40 and the pull-up module 20, and is used to pull down and maintain the potential of the nth stage control signal Qn to the reference low potential VSS according to the nth stage switching signal Pn, and to pull down and maintain the potential of the nth stage gate drive signal Gn to the reference low potential VSS. Here, n is an integer greater than 3.

[0054] In this embodiment, the nth-level gate drive signal Gn output by the nth-level sub-driving circuit can drive the pixel units of a row. Multiple sub-driving circuits are cascaded to form a gate drive circuit. Furthermore, gate drive signals are transmitted between the multiple sub-driving circuits. The (n-3)th-level gate drive signal Gn-3 of the (n-3)th-level sub-driving circuit is input to the pull-up control module 10 as the start signal of the current nth-level sub-driving circuit. The pull-up control module 10 outputs the nth-level control signal Qn based on the (n-3)th-level gate drive signal Gn-3 to activate the pull-up module 20. Then, the pull-up module 20 outputs the nth-level gate drive signal Gn based on the nth-level control signal Qn and the nth-level clock signal CLK. Both the nth-level control signal Qn and the nth-level gate drive signal Gn are signals from the current nth-level sub-driving circuit.

[0055] The nth-stage control signal Qn serves as the main input signal of the inverter module 30. The nth-stage inverted signal Kn serves as the output signal of the inverter module 30. The inverter module 30 reverses the nth-stage control signal Qn and the nth-stage inverted signal Kn; that is, when the nth-stage control signal Qn is at a high potential, the nth-stage inverted signal Kn is at a low potential, and vice versa.

[0056] The inverter module 30 charges the transistors in the inverter module 30 according to the reference high-level signal VGH, causing the nth-stage inverting signal Kn to become high, thus controlling the drift mitigation module 40 to start working. The drift mitigation module 40, based on the nth-stage inverting signal Kn and the local clock signal CLKm-1, causes the potential of the nth-stage switching signal Pn to switch high and low with the local clock signal CLKm-1, reducing the forward bias effect on the transistors in the pull-down sustaining module 50. This solves the problem of forward drift of the threshold voltage (Vth) caused by the transistors in the pull-down sustaining module 50 being in the on state for a long time, extending the lifespan of each transistor. Furthermore, the pull-down sustaining module 50, based on the nth-stage switching signal Pn, can switch high and low with the local clock signal CLKm-1, pulling down and maintaining the potential of the nth-stage control signal Qn to the reference low-level VSS, and also pulling down and maintaining the potential of the nth-stage gate drive signal Gn to the reference low-level VSS, ensuring the gate drive circuit can guarantee the function of the pull-down sustaining module 50. Therefore, the gate drive circuit provided in this application can more stably and reliably turn the thin-film transistors of the display panel on or off normally, avoiding abnormalities in the gate drive circuit.

[0057] In one embodiment, the nth-level sub-driving circuit further includes a pull-down module 60. The pull-down module 60 is connected to the pull-up module 20 and is used to pull down the potential of the nth-level control signal Qn to a reference low potential VSS according to the (n+4)th-level gate drive signal Gn+4 of the (n+4)th-level sub-driving circuit.

[0058] In this embodiment, the pull-down module 60 pulls down the nth-level control signal Qn, ensuring that when the nth-level control signal Qn needs to be at a low potential, it can be accurately set to a low potential, thus ensuring the stability of the nth-level control signal Qn and preventing pixel malfunctions or leakage. The pull-down maintenance module 50 and the pull-down module 60 complement each other functionally and coordinate in timing. After the pull-down module 60 pulls the potential down, it continuously maintains a low potential state, effectively suppressing various parasitic capacitances and external interference in the circuit, ensuring stability at a low potential during the required time period, and improving the stability and reliability of the gate drive circuit.

[0059] In one embodiment, the nth-stage sub-driving circuit further includes a reset module 70. The reset module 70 is connected to the pull-up module 20 and is used to reset the potentials of the nth-stage control signal Qn and the nth-stage gate drive signal Gn to a reference low potential VSS according to the reset signal Reset during the reset time.

[0060] In this embodiment, the input terminal of the reset module 70 is connected to the reset signal Reset. During the reset time, the reset module 70 resets the potentials of the nth stage control signal Qn and the nth stage gate drive signal Gn to the reference low potential VSS, achieving low-potential reset. The reset module 70 eliminates signal residue in the nth stage control signal Qn and the nth stage gate drive signal Gn of the gate drive circuit, effectively clearing residual charge on the nodes, enhancing the stability of the gate drive circuit, and ensuring that the gate drive circuit can start up normally and operate stably.

[0061] Please see Figure 2 In one embodiment, the inverter module 30 includes a first transistor 310, a second transistor 320, a third transistor 330, and a fourth transistor 340. The first and second terminals of the first transistor 310 are connected to acquire a reference high-level signal VGH. The first terminal of the second transistor 320 is connected to the third terminal of the first transistor 310, the second terminal of the second transistor 320 is used to acquire the reference high-level signal VGH, and the third terminal of the second transistor 320 is used to output the nth-stage inverted signal Kn.

[0062] The first terminal of the third transistor 330 is used to acquire the nth-stage control signal Qn. The second terminal of the third transistor 330 is connected to the first terminal of the second transistor 320. The third terminal of the third transistor 330 is used to acquire the reference low potential VSS. The first terminal of the fourth transistor 340 is used to acquire the nth-stage control signal Qn. The second terminal of the fourth transistor 340 is connected to the third terminal of the second transistor 320. The third terminal of the fourth transistor 340 is used to acquire the reference low potential VSS.

[0063] In this embodiment, the inverter module 30 receives a reference high-potential signal VGH and an nth-stage control signal Qn, and outputs an nth-stage inverted signal Kn with the opposite potential to the nth-stage control signal Qn. The reference high-potential signal VGH is introduced by connecting the first and second terminals of the first transistor 310 in a diode configuration. The reference high-potential signal VGH is also connected to the second terminal of the second transistor 320. The reference high-potential signal VGH charges the first transistor 310 and the second transistor 320, causing the nth-stage inverted signal Kn to become high, thus activating the drift mitigation module 40.

[0064] The nth-stage control signal Qn is introduced through the first terminal of the third transistor 330 and the first terminal of the fourth transistor 340. The second terminal of the fourth transistor 340 is connected to the third terminal of the second transistor 320, and the nth-stage inverted signal Kn is output to the drift mitigation module 40 to drive the fifth transistor 410 in the drift mitigation module 40 to work.

[0065] In one embodiment, when the nth-stage control signal Qn in the inverter module 30 is high, the nth-stage inverting signal Kn is low, and the third transistor 330 and the fourth transistor 340 are turned on. When the nth-stage control signal Qn is low, the third transistor 330 and the fourth transistor 340 are turned off and do not conduct, and the nth-stage inverting signal Kn is high. When the nth-stage inverting signal Kn is high, the potential of the nth-stage switching signal Pn switches between high and low with the local clock signal CLKm-1, reducing the forward bias effect on the transistors in the pull-down sustaining module 50, solving the problem of forward drift of the threshold voltage (Vth) caused by the transistors in the pull-down sustaining module 50 being in the on state for a long time, and extending the life of each transistor.

[0066] In one embodiment, the drift mitigation module 40 includes a fifth transistor 410. The first terminal of the fifth transistor 410 is used to acquire the nth-stage inverted signal Kn, the second terminal of the fifth transistor 410 is used to acquire the local clock signal CLKm-1, and the third terminal of the fifth transistor 410 is used to output the nth-stage switching signal Pn.

[0067] In this embodiment, the nth-stage inverted signal Kn is introduced through the first terminal of the fifth transistor 410. When the nth-stage inverted signal Kn is at a high potential, the fifth transistor 410 is turned on, introducing the local clock signal CLKm-1. Subsequently, the potential of the nth-stage switching signal Pn output from the third terminal of the fifth transistor 410 switches between high and low with the local clock signal CLKm-1, reducing the forward bias effect on the transistors in the pull-down sustaining module 50 and solving the problem of forward drift of the threshold voltage (Vth) caused by the transistors in the pull-down sustaining module 50 being in the on state for a long time. When the nth-stage inverted signal Kn is at a low potential, the fifth transistor 410 is turned off, does not conduct, and is not in operation.

[0068] Please see Figure 3 In one embodiment, the pull-down sustaining module 50 includes a sixth transistor 510 and a seventh transistor 520. A first terminal of the sixth transistor 510 is used to acquire an nth-level switching signal, a second terminal of the sixth transistor 510 is used to acquire an nth-level control signal, and a third terminal of the sixth transistor 510 is used to acquire a reference low potential.

[0069] The first terminal of the seventh transistor 520 is used to obtain the nth stage switching signal, the second terminal of the seventh transistor 520 is used to obtain the nth stage gate drive signal, and the third terminal of the seventh transistor 520 is used to obtain the reference low potential.

[0070] In this embodiment, the first terminals of the sixth transistor 510 and the seventh transistor 520 are respectively connected to the third terminal of the fifth transistor 410 to obtain the nth-stage switching signal Pn. The sixth transistor 510 and the seventh transistor 520 can be turned on or off simultaneously.

[0071] When the nth-stage switching signal Pn is high, the sixth transistor 510 and the seventh transistor 520 are simultaneously turned on, pulling down the potential of the nth-stage control signal Qn to maintain it at the reference low potential VSS, and also pulling down the potential of the nth-stage gate drive signal Gn to maintain it at the reference low potential VSS. When the nth-stage switching signal Pn is low, the sixth transistor 510 and the seventh transistor 520 are simultaneously turned off and not turned on.

[0072] By using the sixth transistor 510 and the seventh transistor 520 in the pull-down sustaining module 50, the nth-stage control signal Qn and the nth-stage gate drive signal Gn can be pulled down and maintained at the reference low potential VSS, respectively. Therefore, the gate drive circuit provided in this application can ensure the stability of the nth-stage control signal Qn and the nth-stage gate drive signal Gn.

[0073] Furthermore, the potential of the nth-stage switching signal Pn output from the third terminal of the fifth transistor 410 switches between high and low with the local clock signal CLKm-1, which reduces the positive bias effect on the sixth transistor 510 and the seventh transistor 520 and solves the problem of positive drift of the threshold voltage (Vth) caused by the sixth transistor 510 and the seventh transistor 520 being in the on state for a long time.

[0074] Please see Figure 4 In one embodiment, the pull-up control module 10 includes an eighth transistor 110. The first and second terminals of the eighth transistor 110 are connected to acquire the (n-3)th stage gate drive signal Gn-3, and the third terminal of the eighth transistor 110 is used to output the nth stage control signal Qn.

[0075] In this embodiment, the eighth transistor 110 is connected in a diode configuration. The eighth transistor 110 is turned on by the (n-3)th stage gate drive signal Gn-3, outputting the nth stage control signal Qn of the control node. The nth stage control signal Qn serves as the input signal to the ninth transistor 210 in the pull-up module 20 and as the input signal to the third transistor 330 in the inverter module 30.

[0076] In one embodiment, the first terminal of each transistor in the above embodiment is the gate terminal, the second terminal of each transistor is the drain terminal, and the third terminal of each transistor is the source terminal.

[0077] In one embodiment, the pull-up module 20 includes a ninth transistor 210 and a capacitor 220. The first terminal of the ninth transistor 210 is used to acquire the nth-stage control signal Qn, the second terminal of the ninth transistor 210 is used to acquire the nth-stage clock signal CLK, and the third terminal of the ninth transistor 210 is used to output the nth-stage gate drive signal Gn.

[0078] One end of capacitor 220 is connected to the first end of the ninth transistor 210, and the other end of capacitor 220 is connected to the third end of the ninth transistor 210.

[0079] In this embodiment, the input signals of the pull-up module 20 are the nth-stage control signal Qn and the nth-stage clock signal CLK, and the output signal is the nth-stage gate drive signal Gn. The sixth transistor 510 and the tenth transistor 610 pull down the potential of the nth-stage control signal Qn input to the first terminal of the ninth transistor 210 and maintain it at a reference low potential VSS. A capacitor 220 is connected between the first and third terminals of the ninth transistor 210, i.e., between the gate terminal and the source terminal, serving to store charge, stabilize voltage, and couple and transmit signals.

[0080] Please see Figure 5 In one embodiment, the pull-down module 60 includes a tenth transistor 610. A first terminal of the tenth transistor 610 is used to acquire the (n+4)th stage gate drive signal Gn+4, a second terminal of the tenth transistor 610 is used to acquire the nth stage control signal Qn, and a third terminal of the tenth transistor 610 is used to acquire a reference low potential VSS.

[0081] In this embodiment, when the (n+4)th stage gate drive signal Gn+4 is high, the tenth transistor 610 is turned on, pulling the potential of the nth stage control signal Qn down to the reference low potential VSS. When the (n+4)th stage gate drive signal Gn+4 is low, the tenth transistor 610 is turned off and not turned on. The (n+4)th stage gate drive signal Gn+4 enables the interaction of trigger signals in each cascaded circuit in the gate drive circuit, thereby achieving line-by-line scan drive, ensuring the accuracy of the timing of the cascaded circuits, and achieving synchronization between the cascaded circuits.

[0082] In one embodiment, the reset module 70 includes an eleventh transistor 710 and a twelfth transistor 720. The first terminal of the eleventh transistor 710 is used to acquire the reset signal Reset, the second terminal of the eleventh transistor 710 is used to acquire the nth gate drive signal Gn, and the third terminal of the eleventh transistor 710 is used to acquire the reference low potential VSS.

[0083] The first terminal of the twelfth transistor 720 is used to obtain the reset signal Reset, the second terminal of the twelfth transistor 720 is used to obtain the nth stage control signal Qn, and the third terminal of the twelfth transistor 720 is used to obtain the reference low potential VSS.

[0084] In this embodiment, when the reset signal Reset is high, the first terminal of the eleventh transistor 710 is turned on under the control of the reset signal Reset. During the reset time, the eleventh transistor 710 pulls the potential of the nth gate drive signal Gn down to the reference low potential VSS. When the reset signal Reset is low, the eleventh transistor 710 is turned off and does not conduct.

[0085] When the reset signal Reset is high, the first terminal of the twelfth transistor 720 is turned on under the control of the reset signal Reset. During the reset time, the twelfth transistor 720 pulls the potential of the nth stage control signal Qn down to the reference low potential VSS. When the reset signal Reset is low, the twelfth transistor 720 is turned off and does not conduct.

[0086] The eleventh transistor 710 and the twelfth transistor 720 respectively reset the nth-stage gate drive signal Gn and the nth-stage control signal Qn, which can more accurately and effectively clear the residual charge on the corresponding node, enhance the stability of the gate drive circuit, and ensure that the gate drive circuit can start up normally and work stably, thereby improving the display quality.

[0087] Please see Figure 6 In one embodiment, the input waveforms of the various signals of the gate drive circuit are as follows: Figure 6 As shown. The start signal STV is used to initialize the gate drive circuit and start the first-stage sub-drive circuit. Taking six CLKs as an example, such as CLK1, CLK2, CLK3, CLK4, CLK5, and CLK6. The reference low potential VSS remains low. During the reset time, the reset signal Reset is high. The nth-stage control signal Qn and the nth-stage inverting signal Kn are inversely related.

[0088] In one embodiment, the potential of the nth-level switching signal Pn switches between high and low according to the local clock signal CLK3.

[0089] The nth-level sub-driving circuit provided in this application can also be understood as each sub-driving circuit including 12 TFTs and 1 capacitor, which greatly reduces the number of TFTs, simplifies the GOA circuit, meets the requirements of narrow bezels of display panels, and reduces costs.

[0090] This application provides a display panel including the gate driving circuit of any of the above embodiments. This application can be widely applied to various display panels and devices having display panels, such as mobile phones, laptop computers, and LCD TVs.

[0091] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0092] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0093] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0094] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0095] If the integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0096] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A gate driving circuit, characterized in that, The circuit includes n cascaded sub-driver circuits, wherein the nth sub-driver circuit includes: Pull-up control module (10) is used to output the nth level control signal according to the n-3rd level gate drive signal of the n-3rd level sub-drive circuit; where n is an integer greater than 3; Pull-up module (20), connected to the pull-up control module (10), is used to output the nth gate drive signal according to the nth level control signal and the nth level clock signal; Inverter module (30) is used to obtain the nth stage inverted signal based on the reference high potential signal and the nth stage control signal; The drift mitigation module (40) is connected to the inverter module (30) and is used to output the nth-level switching signal according to the nth-level inverted signal and the local clock signal; The pull-down sustaining module (50), connected to the drift mitigation module (40) and the pull-up module (20), is used to pull down and maintain the potential of the nth level control signal to a reference low potential according to the nth level switching signal, and to pull down and maintain the potential of the nth level gate drive signal to the reference low potential.

2. The gate driving circuit as described in claim 1, characterized in that, The nth-level sub-driving circuit also includes: The pull-down module (60), connected to the pull-up module (20), is used to pull down the potential of the nth level control signal to the reference low potential according to the gate drive signal of the n+4th level sub-drive circuit.

3. The gate driving circuit as described in claim 1, characterized in that, The nth-level sub-driving circuit also includes: The reset module (70), connected to the pull-up module (20), is used to reset the potentials of the nth level control signal and the nth level gate drive signal to the reference low potential according to the reset signal during the reset time.

4. The gate driving circuit as described in any one of claims 1 to 3, characterized in that, The inverter module (30) includes: A first transistor (310) is connected at its first and second ends to acquire the reference high potential signal; The second transistor (320) has a first terminal connected to the third terminal of the first transistor (310), a second terminal of the second transistor (320) for acquiring the reference high potential signal, and a third terminal of the second transistor (320) for outputting the nth level inverted signal. A third transistor (330) is used to acquire the nth level control signal. The second terminal of the third transistor (330) is connected to the first terminal of the second transistor (320). The third terminal of the third transistor (330) is used to acquire the reference low potential. A fourth transistor (340) is provided, the first terminal of which is used to acquire the nth level control signal, the second terminal of which is connected to the third terminal of the second transistor (320), and the third terminal of which is used to acquire the reference low potential.

5. The gate driving circuit as described in any one of claims 1 to 3, characterized in that, The drift mitigation module (40) includes: The fifth transistor (410) has a first terminal for acquiring the nth-stage inverted signal, a second terminal for acquiring the local clock signal, and a third terminal for outputting the nth-stage switching signal.

6. The gate driving circuit as described in any one of claims 1 to 3, characterized in that, The pull-down sustaining module (50) includes: A sixth transistor (510), wherein the first terminal of the sixth transistor (510) is used to acquire the nth stage switching signal, the second terminal of the sixth transistor (510) is used to acquire the nth stage control signal, and the third terminal of the sixth transistor (510) is used to acquire the reference low potential; A seventh transistor (520) is provided, wherein a first terminal of the seventh transistor (520) is used to acquire the nth stage switching signal, a second terminal of the seventh transistor (520) is used to acquire the nth stage gate drive signal, and a third terminal of the seventh transistor (520) is used to acquire the reference low potential.

7. The gate driving circuit as described in any one of claims 1 to 3, characterized in that, The pull-up control module (10) includes: The eighth transistor (110) has its first and second terminals connected to obtain the (n-3)th stage gate drive signal, and its third terminal is used to output the nth stage control signal.

8. The gate driving circuit as described in any one of claims 1 to 3, characterized in that, The pull-up module (20) includes: The ninth transistor (210) has a first terminal for acquiring the nth stage control signal, a second terminal for acquiring the nth stage clock signal, and a third terminal for outputting the nth stage gate drive signal. A capacitor (220) is provided, one end of which is connected to the first end of the ninth transistor (210), and the other end of which is connected to the third end of the ninth transistor (210).

9. The gate driving circuit as described in claim 2, characterized in that, The drop-down module (60) includes: The tenth transistor (610) has a first terminal for acquiring the (n+4)th stage gate drive signal, a second terminal for acquiring the nth stage control signal, and a third terminal for acquiring the reference low potential.

10. The gate driving circuit as described in claim 3, characterized in that, The reset module (70) includes: The eleventh transistor (710) has a first terminal for acquiring the reset signal, a second terminal for acquiring the nth gate drive signal, and a third terminal for acquiring the reference low potential. The twelfth transistor (720) has a first terminal for acquiring the reset signal, a second terminal for acquiring the nth stage control signal, and a third terminal for acquiring the reference low potential.

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