Gate drive circuit

Abstract

The application provides a kind of gate drive circuit, belongs to display technical field.Circuit includes energy storage lock module and pull-up module.Energy storage lock module obtains the nth-4 level trigger signal, the nth-4 level trigger signal is converted into the nth level control signal, and the charge of the nth level control signal is locked.Pull-up module is connected with energy storage lock module, according to the nth level control signal and clock signal, the nth level gate drive signal and the nth level trigger signal are output.Through energy storage lock module, the charge of the nth level control signal is locked, the charge of the nth level control signal is cut off, to prevent leakage from occurring.The high potential of the nth level control signal cannot be reduced by leakage, ensure the high potential of the nth level control signal stable, so that pull-up module according to the nth level control signal and clock signal, the nth level gate drive signal and the nth level trigger signal more stable are output, ensure the normal operation of circuit, to normally open or close the thin film transistor of display panel.

Description

Technical Field

[0001] This application belongs to the field of display technology, and in particular relates to a gate driving circuit. Background Technology

[0002] The Gate Driver on Array (GOA) circuit integrates the gate driver circuit of the display panel onto the glass substrate, forming a scanning driver for the display panel. The GOA driving circuit significantly reduces manufacturing costs and allows for a reduction in the bezel size of the display panel.

[0003] However, in traditional circuit pull-up control modules, the thin-film transistor (TFT) directly outputs the control signal Qn of the internal control node that stores and transmits the level state. When process variations can cause the threshold voltage (Vth) of the TFT in the pull-up control module to be lower than the gate-source voltage Vgs (Vgs is approximately 0V), the TFT will be in a slightly on state. Consequently, when the control signal Qn is at a high potential, the TFT will leak current, causing the high potential of the control signal Qn to decrease, leading to abnormalities in the GOA drive circuit and preventing the TFT of the display panel from being turned on or off normally. Utility Model Content

[0004] The purpose of this application is to provide a gate drive circuit that aims to solve the leakage problem of thin-film transistors in the pull-up control module of traditional circuits caused by process fluctuations.

[0005] This application provides a gate driving circuit, including a multi-stage sub-driving circuit connected in cascades, wherein the nth stage sub-driving circuit includes:

[0006] The energy storage and charge locking module is used to acquire the (n-4)th stage trigger signal of the (n-4)th stage sub-drive circuit, convert the (n-4)th stage trigger signal into the nth stage control signal, and lock the charge of the nth stage control signal; where n is an integer greater than 4.

[0007] The pull-up module, connected to the energy storage and load-locking module, is used to output the nth-stage gate drive signal and the nth-stage trigger signal according to the nth-stage control signal and the clock signal.

[0008] In one embodiment, the energy storage and load-locking module includes:

[0009] A first capacitor is used to acquire the (n-4)th level trigger signal at one end and output the nth level control signal at the other end.

[0010] In one embodiment, the nth-level sub-driving circuit further includes:

[0011] A reset module, connected to the other end of the first capacitor, is used to pull down and reset the potential of the nth level control signal to the first reference low potential according to the reset signal.

[0012] In one embodiment, the nth-level sub-driving circuit further includes:

[0013] A pull-down module, connected to the other end of the first capacitor, is used to pull down the potential of the nth level control signal to the first reference low potential according to the n+5th level trigger signal of the n+5th level sub-drive circuit.

[0014] The pull-down module is connected to the pull-up module and is used to pull down the potential of the nth stage gate drive signal to the second reference low potential according to the n+4th stage gate drive signal of the n+4th stage sub-drive circuit.

[0015] In one embodiment, the nth-level sub-driving circuit further includes:

[0016] A pull-down sustaining module, connected to the other end of the first capacitor, is used to pull down and maintain the potential of the nth level control signal to the first reference low potential according to the first reverse signal or the second reverse signal.

[0017] The pull-down sustaining module is connected to the pull-up module and is used to pull down and maintain the potential of the nth stage gate drive signal to the second reference low potential according to the first reverse signal or the second reverse signal, and to pull down and maintain the potential of the nth stage trigger signal to the first reference low potential.

[0018] In one embodiment, the nth-level sub-driving circuit further includes:

[0019] The first inverter module is connected to the other end of the first capacitor and the pull-down sustaining module, and is used to output a first inverted signal to the pull-down sustaining module according to the first local clock signal, the nth level control signal and the n-4th level trigger signal;

[0020] The second inverter module is connected to the other end of the first capacitor and the pull-down sustaining module, and is used to output a second inverted signal to the pull-down sustaining module according to the second local clock signal, the nth level control signal and the (n-4)th level trigger signal; wherein the first local clock signal is opposite to the second local clock signal.

[0021] In one embodiment, the pull-up module includes:

[0022] The first transistor has a first terminal connected to the other terminal of the first capacitor for acquiring the nth level control signal, a second terminal for acquiring the clock signal, and a third terminal for outputting the nth level trigger signal.

[0023] The second transistor has a first terminal connected to the other terminal of the first capacitor for acquiring the nth stage control signal, a second terminal for acquiring the clock signal, and a third terminal for outputting the nth stage gate drive signal.

[0024] The second capacitor has one end connected to the first terminal of the second transistor and the other end connected to the third terminal of the second transistor.

[0025] In one embodiment, the reset module includes:

[0026] The third transistor has a first terminal for acquiring the reset signal, a second terminal connected to the other terminal of the first capacitor for acquiring the nth stage control signal, and a third terminal for acquiring the first reference low potential.

[0027] In one embodiment, the dropdown module includes:

[0028] The fourth transistor has a first terminal for acquiring the (n+5)th stage trigger signal of the (n+5)th stage sub-driving circuit, a second terminal for being connected to the other end of the first capacitor for acquiring the nth stage control signal, and a third terminal for acquiring the first reference low potential.

[0029] The fifth transistor has a first terminal for acquiring the (n+4)th stage gate drive signal of the (n+4)th stage sub-drive circuit, a second terminal for being connected to the pull-up module for acquiring the nth stage gate drive signal, and a third terminal for acquiring the second reference low potential.

[0030] In one embodiment, the pull-down sustaining module includes:

[0031] The sixth transistor has a first terminal for acquiring the first inverted signal, a second terminal for being connected to the other end of the first capacitor for acquiring the nth level control signal, and a third terminal for acquiring the first reference low potential.

[0032] The seventh transistor has a first terminal for acquiring the first inverted signal, a second terminal for being connected to the pull-up module for acquiring the nth trigger signal, and a third terminal for acquiring the first reference low potential.

[0033] The eighth transistor has a first terminal for acquiring the first inverted signal, a second terminal connected to the pull-up module for acquiring the nth gate drive signal, and a third terminal for acquiring the second reference low potential.

[0034] The beneficial effects of this utility model embodiment compared with the prior art are:

[0035] Multi-level sub-driving circuits are cascaded to form a gate driving circuit. Trigger signals and gate driving signals are transmitted between the multi-level sub-driving circuits, enabling line-by-line scanning of the display panel. The (n-4)th stage trigger signal STn-4 serves as the start signal for the nth stage sub-driving circuit and is input to one end of the energy storage and charging module. When the (n-4)th stage trigger signal STn-4 changes from a low potential to a high potential, the energy storage and charging module is charged. Subsequently, under the action of the energy storage and charging module, the potential at the other end of the energy storage and charging module is pulled high, causing the potential of the nth stage control signal Qn output by the conversion to be synchronously pulled high, completing the charging process.

[0036] The other end of the energy storage and charging module outputs the nth-level control signal Qn, which can control the output of the nth-level gate drive signal Gn to drive the pixel units of a row. Through the energy storage and charging module, the pull-up control module can function as a pull-up control module, outputting the nth-level control signal Qn of the internal control node to store and transmit the level state, ensuring the normal operation of the nth-level sub-drive circuit and the gate drive circuit. The energy storage and charging module locks the charge of the nth-level control signal Qn, cutting off its charge and preventing leakage. This prevents the high potential of the nth-level control signal Qn from decreasing due to leakage, ensuring the stability of its high potential. Therefore, the gate drive circuit provided in this application ensures the stability of the high potential of the nth-level control signal Qn, allowing the pull-up module to output a more stable nth-level gate drive signal Gn and nth-level trigger signal STn based on the stable nth-level control signal Qn and the clock signal CLK, ensuring the normal operation of the GOA drive circuit and properly turning the thin-film transistors of the display panel on or off. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or exemplary technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 The circuit structure diagrams of the gate drive circuits in some embodiments provided in this application are shown.

[0039] Figure 2 A schematic diagram of the transistor connection structure of the pull-up module and the reset module in some embodiments provided in this application.

[0040] Figure 3 A schematic diagram of the transistor connection structure of the pull-down module and the pull-down sustaining module in some embodiments provided in this application.

[0041] Figure 4 A schematic diagram of the transistor connection structure of the first inverter module and the second inverter module in some embodiments provided in this application. Detailed Implementation

[0042] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0043] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0044] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0045] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. Additionally, in the embodiments of this application, the terms "first" and "second" are used to distinguish identical or similar items that have substantially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or order of execution, and that "first" and "second" do not necessarily imply difference.

[0046] In the description of this application, unless otherwise stated, " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B can mean A or B. "And / or" in this application is merely a description of the relationship between the related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone, where A and B can be singular or plural. Furthermore, in the description of this application, unless otherwise stated, "multiple" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0047] Please see Figure 1 This application provides a gate driving circuit. The gate driving circuit includes cascaded multi-stage sub-driving circuits. The nth stage sub-driving circuit includes an energy storage and charging module 10 and a pull-up module 20. The energy storage and charging module 10 is used to acquire the (n-4)th stage trigger signal STn-4 of the (n-4)th stage sub-driving circuit, convert the (n-4)th stage trigger signal STn-4 into the nth stage control signal Qn, and lock the charge of the nth stage control signal Qn. Here, n is an integer greater than 4. The pull-up module 20 is connected to the energy storage and charging module 10 and is used to output the nth stage gate driving signal Gn and the nth stage trigger signal STn according to the nth stage control signal Qn and the clock signal CLK.

[0048] In this embodiment, multi-level sub-driving circuits are cascaded to form a gate driving circuit. The transmission of trigger signals and gate driving signals between the multi-level sub-driving circuits enables line-by-line scanning of the display panel. The (n-4)th stage trigger signal STn-4 is input to one end of the energy storage and charging module 10 as the start signal of the nth stage sub-driving circuit. When the (n-4)th stage trigger signal STn-4 changes from a low potential to a high potential, the energy storage and charging module 10 is charged. Furthermore, under the action of the energy storage and charging module 10, the potential at the other end of the energy storage and charging module 10 is pulled high, causing the potential of the nth stage control signal Qn output by the conversion to be synchronously pulled high, completing the charging process.

[0049] The other end of the energy storage and locking module 10 outputs the nth-level control signal Qn, which can control the output of the nth-level gate drive signal Gn in the pull-up module 20 to drive the pixel units of a row. Through the energy storage and locking module 10, the function of the pull-up control module can be realized, outputting the nth-level control signal Qn of the internal control node that stores and transmits the level state, ensuring the normal operation of the nth-level sub-drive circuit and the gate drive circuit. Through the energy storage and locking module 10, the charge of the nth-level control signal Qn is locked, cutting off the charge of the nth-level control signal Qn to prevent leakage, ensuring that the high potential of the nth-level control signal Qn cannot be reduced by leakage, thus ensuring the stability of the high potential of the nth-level control signal Qn. Therefore, through the gate drive circuit provided in this application, the high potential of the nth-level control signal Qn can be ensured to be stable, allowing the pull-up module 20 to output a more stable nth-level gate drive signal Gn and nth-level trigger signal STn based on the stable nth-level control signal Qn and the clock signal CLK, ensuring the normal operation of the GOA drive circuit to properly turn the thin-film transistors of the display panel on or off.

[0050] In one embodiment, the energy storage and load locking module 10 includes at least one first capacitor 110. The first capacitor 110 is a coupling capacitor. The number of first capacitors 110 in the energy storage and load locking module 10 can be set according to the actual application scenario. The capacitance and other parameters of the first capacitors 110 can be set according to the actual application scenario.

[0051] In one embodiment, the energy storage and load locking module 10 includes a plurality of first capacitors 110 connected in series. One end of the plurality of first capacitors 110 connected in series receives the (n-4)th level trigger signal STn-4, and the other end of the plurality of first capacitors 110 connected in series outputs the nth level control signal Qn.

[0052] In one embodiment, the energy storage and load locking module 10 includes a first capacitor 110. One end of the first capacitor 110 receives the (n-4)th level trigger signal STn-4, and the other end of the first capacitor 110 outputs the nth level control signal Qn.

[0053] In this embodiment, the (n-4)th stage trigger signal STn-4 is input to one end of the first capacitor 110 as the start signal of the nth stage sub-drive circuit. When the (n-4)th stage trigger signal STn-4 changes from a low potential to a high potential, the first capacitor 110 is charged. Subsequently, under the action of the first capacitor 110, the potential at the other end of the first capacitor 110 is pulled high, causing the potential of the nth stage control signal Qn to be pulled high synchronously, completing the charging process.

[0054] The other end of the first capacitor 110 outputs the nth-level control signal Qn, which can control the output of the nth-level gate drive signal Gn to drive the pixel units of a row. Through the first capacitor 110, the pull-up control module can function, outputting the nth-level control signal Qn of the internal control node to store and transmit the level state, ensuring the normal operation of the nth-level sub-drive circuit and the gate drive circuit. Through the first capacitor 110, the charge of the nth-level control signal Qn is locked, cutting off the charge of the nth-level control signal Qn to prevent leakage, ensuring that the high potential of the nth-level control signal Qn cannot be reduced by leakage, thus ensuring the stability of the high potential of the nth-level control signal Qn. Therefore, through the gate drive circuit provided in this application, the high potential of the nth-level control signal Qn can be ensured to be stable, allowing the pull-up module 20 to output a more stable nth-level gate drive signal Gn and nth-level trigger signal STn according to the nth-level control signal Qn and the clock signal CLK, ensuring the normal operation of the GOA drive circuit to properly turn the thin-film transistors of the display panel on or off.

[0055] In one embodiment, the nth-stage sub-driving circuit further includes a reset module 30. The reset module 30 is connected to the other end of the first capacitor 110 and is used to pull down and reset the potential of the nth-stage control signal Qn to the first reference low potential VSSQ according to the reset signal Reset.

[0056] In this embodiment, the reset module 30 is connected to the other end of the first capacitor 110 to obtain the nth-level control signal Qn. The input terminal of the reset module 30 is connected to the reset signal Reset. During the reset time, the reset module 30 pulls the potential of the nth-level control signal Qn down to the first reference low potential VSSQ to achieve low-level reset, ensuring the low-level stability of the nth-level control signal Qn, preventing pixel malfunctions or leakage, and enhancing the stability of the gate drive circuit.

[0057] In one embodiment, the nth-level sub-driving circuit further includes a pull-down module 40. The pull-down module 40 is connected to the other end of the first capacitor 110 and is used to pull down the potential of the nth-level control signal Qn to the first reference low potential VSSQ according to the n+5th-level trigger signal STn+5 of the n+5th-level sub-driving circuit.

[0058] The pull-down module 40 is connected to the pull-up module 20 and is used to pull down the potential of the nth stage gate drive signal Gn to the second reference low potential VSSG according to the n+4th stage gate drive signal Gn+4 of the n+4th stage sub-drive circuit.

[0059] In this embodiment, the pull-down module 40 is connected to the other end of the first capacitor 110 to obtain the nth level control signal Qn. Under the control of the (n+5)th level trigger signal STn+5, the pull-down module 40 pulls the potential of the nth level control signal Qn down to the first reference low potential VSSQ. This ensures that when the potential of the nth level control signal Qn needs to be low, it can be accurately set to a low potential, ensuring the stability of the low potential of the nth level control signal Qn and preventing pixel malfunctions or leakage.

[0060] The pull-down module 40 is connected to the pull-up module 20 to obtain the nth-level gate drive signal Gn. Under the control of the (n+4)th-level gate drive signal Gn+4, the pull-down module 40 pulls the potential of the nth-level gate drive signal Gn down to the second reference low potential VSSG. This ensures that when the potential of the nth-level gate drive signal Gn needs to be low, it can be accurately set to a low potential, ensuring the stability of the low potential of the nth-level gate drive signal Gn and preventing pixel malfunctions or leakage.

[0061] In one embodiment, the nth-stage sub-driving circuit further includes a pull-down sustaining module 50. The pull-down sustaining module 50 is connected to the other end of the first capacitor 110 and is used to pull down and maintain the potential of the nth-stage control signal Qn to the first reference low potential VSSQ according to the first inverted signal Kn or the second inverted signal Pn.

[0062] The pull-down sustaining module 50 is connected to the pull-up module 20 and is used to pull down and maintain the potential of the nth stage gate drive signal Gn to the second reference low potential VSSG according to the first reverse signal Kn or the second reverse signal Pn, and to pull down and maintain the potential of the nth stage trigger signal STn to the first reference low potential VSSQ.

[0063] In this embodiment, the pull-down sustaining module 50 is connected to the other end of the first capacitor 110 to obtain the nth-level control signal Qn. By pulling down and maintaining the potential of the nth-level control signal Qn to the first reference low potential VSSQ through the pull-down sustaining module 50, it can be ensured that when the potential of the nth-level control signal Qn needs to be low, the potential of the nth-level control signal Qn can be accurately set to a low potential, ensuring the stability of the low potential of the nth-level control signal Qn, preventing pixel malfunctions or leakage, and enhancing the stability of the gate drive circuit.

[0064] The pull-down sustaining module 50 is connected to the pull-up module 20 to acquire the nth-stage trigger signal STn and the nth-stage gate drive signal Gn. By using the pull-down sustaining module 50 to pull down and maintain the potential of the nth-stage trigger signal STn to the first reference low potential VSSQ, it ensures that when the potential of the nth-stage trigger signal STn needs to be low, the potential of STn can be accurately set to low, ensuring the stability of the low potential of STn and preventing pixel malfunctions or leakage, thus enhancing the stability of the gate drive circuit.

[0065] By using the pull-down sustaining module 50 to pull down and maintain the potential of the nth-level gate drive signal Gn to the second reference low potential VSSG, it can be ensured that when the potential of the nth-level gate drive signal Gn needs to be low, the potential of the nth-level gate drive signal Gn can be accurately set to low, thus ensuring the stability of the low potential of the nth-level gate drive signal Gn, preventing pixel malfunctions or leakage, and enhancing the stability of the gate drive circuit.

[0066] Furthermore, under the control of the first inverted signal Kn or the second inverted signal Pn, the transistors within the pull-down sustaining module 50 can be alternately turned on to achieve the pull-down sustaining function. This avoids the forward bias drift problem caused by some transistors being constantly turned on, ensuring the stability of the pull-down sustaining module 50. The pull-down sustaining module 50 and the pull-down module 40 complement each other in function and cooperate in timing. After the pull-down module 40 pulls the potential down, it can continuously maintain a low potential state, effectively suppressing various parasitic capacitances and external interference in the circuit, ensuring that the low potential is maintained stably during the required period, and improving the stability and reliability of the gate drive circuit.

[0067] In one embodiment, the nth-stage sub-driving circuit further includes a first inverter module 610 and a second inverter module 620. The first inverter module 610 is connected to the other end of the first capacitor 110 and the pull-down sustaining module 50, and is used to output a first inverted signal Kn to the pull-down sustaining module 50 according to the first local clock signal LC1, the nth-stage control signal Qn and the (n-4)th-stage trigger signal STn-4.

[0068] The second inverter module 620 is connected to the other end of the first capacitor 110 and the pull-down sustaining module 50, and is used to output a second inverted signal Pn to the pull-down sustaining module 50 according to the second local clock signal LC2, the nth level control signal Qn, and the (n-4)th level trigger signal STn-4. The first local clock signal LC1 is opposite to the second local clock signal LC2.

[0069] In this embodiment, the nth-stage control signal Qn serves as the main input signal of the first inverter module 610. The first inverted signal Kn serves as the output signal of the first inverter module 610. The first inverter module 610 inverts the nth-stage control signal Qn and the first inverted signal Kn. Similarly, the nth-stage control signal Qn serves as the main input signal of the second inverter module 620. The second inverted signal Pn serves as the output signal of the second inverter module 620. The second inverter module 620 inverts the nth-stage control signal Qn and the second inverted signal Pn.

[0070] The first local clock signal LC1 and the second local clock signal LC2 are two opposite clock signals. When the first local clock signal LC1 is high, the second local clock signal LC2 is low. When the first local clock signal LC1 is low, the second local clock signal LC2 is high. By making the first local clock signal LC1 and the second local clock signal LC2 opposite, the pull-down sustaining module 50 can control the transistors within it to alternately conduct under the control of either the first inverted signal Kn or the second inverted signal Pn, thus avoiding the forward bias drift problem caused by some transistors always being in the on state.

[0071] Furthermore, the first inverter module 610 incorporates the control of the (n-4)th stage trigger signal STn-4 when outputting the first inverted signal Kn. This allows it to quickly pull the first inverted signal Kn low when the nth stage control signal Qn begins to go high, solving the problem that the nth stage control signal Qn cannot rise and avoiding the pull problem between the first inverted signal Kn and the nth stage control signal Qn. Similarly, the second inverter module 620 incorporates the control of the (n-4)th stage trigger signal STn-4 when outputting the second inverted signal Pn. This allows it to quickly pull the second inverted signal Pn low when the nth stage control signal Qn begins to go high, solving the problem that the nth stage control signal Qn cannot rise and avoiding the pull problem between the second inverted signal Pn and the control signal Qn.

[0072] Furthermore, the pull-down sustaining module 50 maintains the nth-stage control signal Qn, the nth-stage trigger signal STn, and the nth-stage gate drive signal Gn by pulling down the first inverted signal Kn or the second inverted signal Pn. This prevents low-potential fluctuations in the nth-stage control signal Qn, the nth-stage trigger signal STn, and the nth-stage gate drive signal Gn, improving their low-potential stability and reliability. This ensures that the thin-film transistors of the display panel can be turned on or off normally, guaranteeing the normal display of the display panel and extending its lifespan.

[0073] Please see Figure 2 In one embodiment, the pull-up module 20 includes a first transistor 210, a second transistor 220, and a second capacitor 230. The first terminal of the first transistor 210 is connected to the other terminal of the first capacitor 110 and is used to acquire the nth level control signal Qn. The second terminal of the first transistor 210 is used to acquire the clock signal CLK. The third terminal of the first transistor 210 is used to output the nth level trigger signal STn.

[0074] The first terminal of the second transistor 220 is connected to the other terminal of the first capacitor 110 to obtain the nth stage control signal Qn. The second terminal of the second transistor 220 is used to obtain the clock signal CLK. The third terminal of the second transistor 220 is used to output the nth stage gate drive signal Gn.

[0075] One end of the second capacitor 230 is connected to the first end of the second transistor 220, and the other end of the second capacitor 230 is connected to the third end of the second transistor 220.

[0076] In this embodiment, the input signals of the pull-up module 20 are the nth-stage control signal Qn and the clock signal CLK, and the output signals are the nth-stage gate drive signal Gn and the nth-stage trigger signal STn. The second capacitor 230 is connected between the first and third terminals of the second transistor 220, that is, between the gate terminal and the source terminal, serving to store charge, stabilize voltage, and couple and transmit signals.

[0077] In one embodiment, the second capacitor 230 is a coupling capacitor.

[0078] In one embodiment, the nth-stage control signal Qn input to the first terminal of the second transistor 220 is pulled down to the first reference low potential VSSQ, and the nth-stage gate drive signal Gn output from the third terminal of the second transistor 220 is pulled down to the second reference low potential VSSG. The first reference low potential VSSQ is less than the second reference low potential VSSG, and the Vgs of the second transistor 220 = VSSQ - VSSG, which is less than zero. This makes the second transistor 220 less prone to forward bias under negative stress. Therefore, the second transistor 220 is less prone to forward bias under negative stress, ensuring that the nth-stage gate drive signal Gn can be stably maintained when a high potential is required. This ensures that the thin-film transistors of the display panel can be normally turned on or off, guaranteeing normal display operation and extending the lifespan of the display panel.

[0079] In one embodiment, the reset module 30 includes a third transistor 310. A first terminal of the third transistor 310 is used to acquire a reset signal Reset, a second terminal of the third transistor 310 is connected to the other terminal of the first capacitor 110 and is used to acquire an nth-level control signal Qn, and a third terminal of the third transistor 310 is used to acquire a first reference low potential VSSQ.

[0080] In this embodiment, a reset signal Reset is connected to the first terminal of the third transistor 310. Under the control of the reset signal Reset, the nth-stage control signal Qn output from the other terminal of the first capacitor 110 is pulled down to the first reference low potential VSSQ, thereby realizing the reset function. In one embodiment, when the reset signal Reset is high, the third transistor 310 is turned on, pulling the nth-stage control signal Qn down to the first reference low potential VSSQ. This ensures that when the potential of the nth-stage control signal Qn needs to be low, the potential of the nth-stage control signal Qn can be accurately reset to a low potential, ensuring the stability of the low potential of the nth-stage control signal Qn and preventing pixel malfunction or leakage. When the reset signal Reset is low, the third transistor 310 is turned off and not turned on, preventing the potential of the nth-stage control signal Qn from being set to a low potential. This ensures the stability of the high potential of the nth-stage control signal Qn, preventing pixel malfunction or leakage and improving the stability and reliability of the gate drive circuit.

[0081] Please see Figure 3 In one embodiment, the pull-down module 40 includes a fourth transistor 410 and a fifth transistor 420. The first terminal of the fourth transistor 410 is used to acquire the (n+5)th stage trigger signal STn+5 of the (n+5)th stage sub-drive circuit, the second terminal of the fourth transistor 410 is connected to the other end of the first capacitor 110 and is used to acquire the nth stage control signal Qn, and the third terminal of the fourth transistor 410 is used to acquire the first reference low potential VSSQ.

[0082] The first terminal of the fifth transistor 420 is used to obtain the gate drive signal Gn+4 of the (n+4)th stage of the sub-drive circuit. The second terminal of the fifth transistor 420 is connected to the pull-up module 20 and is used to obtain the gate drive signal Gn of the nth stage. The third terminal of the fifth transistor 420 is used to obtain the second reference low potential VSSG.

[0083] In this embodiment, when the (n+5)th stage trigger signal STn+5 is at a high potential, the fourth transistor 410 is turned on, pulling down the potential of the nth stage control signal Qn to the first reference low potential VSSQ. This ensures that when the potential of the nth stage control signal Qn needs to be low, it can be accurately set to a low potential, ensuring the stability of the low potential of the nth stage control signal Qn and preventing pixel malfunctions or leakage. When the (n+5)th stage trigger signal STn+5 is at a low potential, the fourth transistor 410 is turned off and not turned on, preventing the potential of the nth stage control signal Qn from being set to a low potential. This ensures the stability of the high potential of the nth stage control signal Qn, preventing pixel malfunctions or leakage, and improving the stability and reliability of the gate drive circuit.

[0084] When the (n+4)th stage gate drive signal Gn+4 is high, the fifth transistor 420 is turned on, pulling the potential of the nth stage gate drive signal Gn down to the second reference low potential VSSG. This ensures that when the potential of the nth stage gate drive signal Gn needs to be low, it can be accurately set to a low potential, ensuring the stability of the low potential of the nth stage gate drive signal Gn and preventing pixel malfunctions or leakage. When the (n+4)th stage gate drive signal Gn+4 is low, the fifth transistor 420 is turned off and does not conduct, preventing the potential of the nth stage gate drive signal Gn from being set to a low potential. This ensures the stability of the high potential of the nth stage gate drive signal Gn, preventing pixel malfunctions or leakage and improving the stability and reliability of the gate drive circuit.

[0085] Furthermore, the gate drive signal Gn+4 of the (n+4)th stage and the trigger signal STn+5 of the (n+5)th stage are used to realize the interaction between the gate drive signals and the trigger signals in each cascaded circuit in the gate drive circuit, so as to realize line-by-line scanning drive, ensure the accuracy of the timing of the cascaded circuit, and realize the synchronization between the cascaded circuits.

[0086] In one embodiment, the pull-down sustaining module 50 includes a sixth transistor 510, a seventh transistor 520, and an eighth transistor 530. The first terminal of the sixth transistor 510 is used to acquire a first inverted signal Kn, the second terminal of the sixth transistor 510 is connected to the other end of the first capacitor 110 and is used to acquire an nth-level control signal Qn, and the third terminal of the sixth transistor 510 is used to acquire a first reference low potential VSSQ.

[0087] The first terminal of the seventh transistor 520 is used to obtain the first inverted signal Kn, the second terminal of the seventh transistor 520 is connected to the pull-up module 20 and is used to obtain the nth stage trigger signal STn, and the third terminal of the seventh transistor 520 is used to obtain the first reference low potential VSSQ.

[0088] The first terminal of the eighth transistor 530 is used to obtain the first inverted signal Kn, the second terminal of the eighth transistor 530 is connected to the pull-up module 20 and is used to obtain the nth gate drive signal Gn, and the third terminal of the eighth transistor 530 is used to obtain the second reference low potential VSSG.

[0089] In this embodiment, the sixth transistor 510, the seventh transistor 520, and the eighth transistor 530 are simultaneously turned on or simultaneously turned off. The sixth transistor 510, the seventh transistor 520, and the eighth transistor 530 form part of the pull-down sustaining module 50. When the first inverting signal Kn is high, the sixth transistor 510, the seventh transistor 520, and the eighth transistor 530 are simultaneously turned on. When the first inverting signal Kn is low, the sixth transistor 510, the seventh transistor 520, and the eighth transistor 530 are simultaneously turned off and not turned on.

[0090] When the first inverse signal Kn is at a high potential, the sixth transistor 510 is turned on, pulling down the nth-stage control signal Qn to maintain it at the first reference low potential VSSQ. This ensures the stability of the low potential of the nth-stage control signal Qn, preventing pixel malfunctions or leakage.

[0091] When the first inverse signal Kn is at a high potential, the seventh transistor 520 is turned on, pulling down the nth stage trigger signal STn to maintain it at the first reference low potential VSSQ. This ensures the stability of the low potential of the nth stage trigger signal STn, preventing pixel malfunctions or leakage.

[0092] When the first inverse signal Kn is high, the eighth transistor 530 is turned on, pulling down the nth-stage gate drive signal Gn to maintain it at the second reference low potential VSSG. This ensures the low-potential stability of the nth-stage gate drive signal Gn, preventing pixel malfunctions or leakage. Therefore, the gate drive circuit provided in this application can ensure the low-potential stability of the nth-stage control signal Qn, the nth-stage trigger signal STn, and the nth-stage gate drive signal Gn.

[0093] In one embodiment, the pull-down sustaining module 50 further includes a twelfth transistor 540, a thirteenth transistor 550, and a fourteenth transistor 560. The first terminal of the twelfth transistor 540 is used to acquire a second inverted signal Pn, the second terminal of the twelfth transistor 540 is connected to the other end of the first capacitor 110 and is used to acquire an nth-level control signal Qn, and the third terminal of the twelfth transistor 540 is used to acquire a first reference low potential VSSQ.

[0094] The first terminal of the thirteenth transistor 550 is used to obtain the second inverted signal Pn. The second terminal of the thirteenth transistor 550 is connected to the pull-up module 20 and is used to obtain the nth stage trigger signal STn. The third terminal of the thirteenth transistor 550 is used to obtain the first reference low potential VSSQ.

[0095] The first terminal of the fourteenth transistor 560 is used to obtain the second inverted signal Pn. The second terminal of the fourteenth transistor 560 is connected to the pull-up module 20 and is used to obtain the nth gate drive signal Gn. The third terminal of the fourteenth transistor 560 is used to obtain the second reference low potential VSSG.

[0096] In this embodiment, the twelfth transistor 540, the thirteenth transistor 550, and the fourteenth transistor 560 are simultaneously turned on or simultaneously turned off. The twelfth transistor 540, the thirteenth transistor 550, and the fourteenth transistor 560 form another part of the pull-down sustaining module 50.

[0097] When the second inverse signal Pn is at a high potential, the twelfth transistor 540 is turned on, pulling down the nth stage control signal Qn to maintain it at the first reference low potential VSSQ. This ensures the low potential stability of the nth stage control signal Qn, preventing pixel malfunctions or leakage.

[0098] When the second inverse signal Pn is at a high potential, the thirteenth transistor 550 is turned on, pulling down the nth stage trigger signal STn to maintain it at the first reference low potential VSSQ. This ensures the stability of the low potential of the nth stage trigger signal STn, preventing pixel malfunctions or leakage.

[0099] When the second inverse signal Pn is at a high potential, the fourteenth transistor 560 is turned on, pulling down the nth-stage gate drive signal Gn to maintain it at the second reference low potential VSSG. This ensures the stability of the low potential of the nth-stage gate drive signal Gn, preventing pixel malfunctions or leakage.

[0100] The twelfth transistor 540, the thirteenth transistor 550, and the fourteenth transistor 560 can respectively pull down the nth stage control signal Qn, the nth stage trigger signal STn, and the nth stage gate drive signal Gn to maintain them at the first reference low potential VSSQ and the second reference low potential VSSG, thus ensuring the low potential stability of the nth stage control signal Qn, the nth stage trigger signal STn, and the nth stage gate drive signal Gn.

[0101] Therefore, under the control of the second reverse signal Pn or the first reverse signal Kn, the sixth transistor 510 and the twelfth transistor 540 can be turned on alternately, the seventh transistor 520 and the thirteenth transistor 550 can be turned on alternately, and the eighth transistor 530 and the fourteenth transistor 560 can be turned on alternately to realize the pull-down function and prevent the device characteristics from drifting.

[0102] Please see Figure 4In one embodiment, the first inverter module 610 includes a ninth transistor 611, a tenth transistor 612, and an eleventh transistor 613. The first and second terminals of the ninth transistor 611 are connected to acquire a first local clock signal LC1.

[0103] The first terminal of the tenth transistor 612 is used to obtain the (n-4)th stage trigger signal STn-4. The second terminal of the tenth transistor 612 is connected to the third terminal of the ninth transistor 611. The third terminal of the tenth transistor 612 is used to obtain the first reference low potential VSSQ.

[0104] The first terminal of the eleventh transistor 613 is used to acquire the nth level control signal Qn. The second terminal of the eleventh transistor 613 is connected to the third terminal of the ninth transistor 611 and is used to output the first inverted signal Kn. The third terminal of the eleventh transistor 613 is used to acquire the first reference low potential VSSQ.

[0105] In this embodiment, the first and second terminals of the ninth transistor 611 are connected in a diode configuration to introduce the first local clock signal LC1. The alternation of the first local clock signal LC1 and the second local clock signal LC2 causes the first inverter module 610 and the second inverter module 620 to alternately control the operation of the pull-down sustaining module 50.

[0106] The (n-4)th stage trigger signal STn-4 is introduced through the first terminal of the tenth transistor 612. The nth stage control signal Qn is introduced through the first terminal of the eleventh transistor 613. The common connection point between the ninth transistor 611, the tenth transistor 612, and the eleventh transistor 613 serves as the output terminal of the first inverter module 610, outputting the first inverted signal Kn to the pull-down sustaining module 50.

[0107] Because the first inverting signal Kn and the nth-stage control signal Qn have opposite potentials, there is a pull between them. By using the tenth transistor 612, under the control of the (n-4)th-stage trigger signal STn-4, the first inverting signal Kn can be quickly pulled low when the nth-stage control signal Qn begins to go high, thus avoiding the pull problem between them.

[0108] In one embodiment, when the nth-stage control signal Qn in the first inverter module 610 is at a high potential, the eleventh transistor 613 is turned on, causing the first inverted signal Kn to be at a low potential. When the nth-stage control signal Qn is at a low potential, the eleventh transistor 613 is turned off and not turned on, causing the first inverted signal Kn to be at a high potential, thus turning on the pull-down sustaining module 50 to achieve the pull-down sustaining function. The first inverter module 610 includes a ninth transistor 611, a tenth transistor 612, and an eleventh transistor 613, forming a 3T structure. This simplifies the inverter structure while preventing the pulling problem between the first inverted signal Kn and the nth-stage control signal Qn, meeting the requirements of narrow bezels in the display panel and reducing costs.

[0109] In one embodiment, the second inverter module 620 includes a fifteenth transistor 621, a sixteenth transistor 622, and a seventeenth transistor 623. The connection structure of the transistors in the second inverter module 620 is the same as the connection structure of the transistors in the first inverter module 610.

[0110] The first and second terminals of the fifteenth transistor 621 are connected to obtain the second local clock signal LC2. The first terminal of the sixteenth transistor 622 is used to obtain the (n-4)th stage trigger signal STn-4. The second terminal of the sixteenth transistor 622 is connected to the third terminal of the fifteenth transistor 621. The third terminal of the sixteenth transistor 622 is used to obtain the first reference low potential VSSQ.

[0111] The first terminal of the seventeenth transistor 623 is used to acquire the nth stage control signal Qn. The second terminal of the seventeenth transistor 623 is connected to the third terminal of the fifteenth transistor 621 and is used to output the second inverted signal Pn. The third terminal of the seventeenth transistor 623 is used to acquire the first reference low potential VSSQ.

[0112] In this embodiment, the second local clock signal LC2 is introduced by connecting the first and second terminals of the fifteenth transistor 621 in a diode configuration. The (n-4)th stage trigger signal STn-4 is introduced through the first terminal of the sixteenth transistor 622. The nth stage control signal Qn is introduced through the first terminal of the seventeenth transistor 623. The common connection point between the fifteenth transistor 621, the sixteenth transistor 622, and the seventeenth transistor 623 serves as the output terminal of the second inverter module 620, outputting the second inverted signal Pn to the pull-down sustaining module 50.

[0113] Because the second inverse signal Pn has an opposite potential to the nth-stage control signal Qn, there is a pull between them. By using the sixteenth transistor 622, under the control of the (n-4)th-stage trigger signal STn-4, the second inverse signal Pn can be quickly pulled low when the nth-stage control signal Qn begins to go high, thus avoiding the pull problem between them.

[0114] In one embodiment, when the nth-stage control signal Qn in the second inverter module 620 is at a high potential, the seventeenth transistor 623 is turned on, causing the second inverted signal Pn to be at a low potential. When the nth-stage control signal Qn is at a low potential, the seventeenth transistor 623 is turned off and not turned on, causing the second inverted signal Pn to be at a high potential, thus turning on the pull-down sustaining module 50 to achieve the pull-down sustaining function. The second inverter module 620 includes a fifteenth transistor 621, a sixteenth transistor 622, and a seventeenth transistor 623, forming a 3T structure. This simplifies the inverter structure while preventing the pull problem between the second inverted signal Pn and the nth-stage control signal Qn, meeting the requirements of narrow bezels in the display panel and reducing costs.

[0115] In one embodiment, the first terminal of each transistor in the above embodiment is the gate terminal, the second terminal of each transistor is the drain terminal, and the third terminal of each transistor is the source terminal.

[0116] This application provides a display panel including the gate driving circuit of any of the above embodiments. This application can be widely applied to various display panels and devices having display panels, such as mobile phones, laptop computers, and LCD TVs.

[0117] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0118] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0119] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0120] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0121] If the integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0122] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A gate driving circuit, characterized in that, The nth-level sub-drive circuit includes cascaded sub-drive circuits. The energy storage and charge locking module (10) is used to acquire the (n-4)th stage trigger signal of the (n-4)th stage sub-drive circuit, convert the (n-4)th stage trigger signal into the nth stage control signal, and lock the charge of the nth stage control signal; where n is an integer greater than 4. The pull-up module (20) is connected to the energy storage and load-locking module (10) and is used to output the nth-level gate drive signal and the nth-level trigger signal according to the nth-level control signal and the clock signal.

2. The gate driving circuit as described in claim 1, characterized in that, The energy storage and load-locking module (10) includes: A first capacitor (110) is used, one end of which receives the (n-4)th level trigger signal, and the other end of the first capacitor (110) outputs the nth level control signal.

3. The gate driving circuit as described in claim 2, characterized in that, The nth-level sub-driving circuit also includes: The reset module (30) is connected to the other end of the first capacitor (110) and is used to pull down and reset the potential of the nth level control signal to the first reference low potential according to the reset signal.

4. The gate driving circuit as described in claim 2, characterized in that, The nth-level sub-driving circuit also includes: The pull-down module (40) is connected to the other end of the first capacitor (110) and is used to pull down the potential of the nth level control signal to the first reference low potential according to the n+5th level trigger signal of the n+5th level sub-drive circuit. The pull-down module (40) is connected to the pull-up module (20) and is used to pull down the potential of the nth level gate drive signal to the second reference low potential according to the n+4th level gate drive signal of the n+4th level sub-drive circuit.

5. The gate driving circuit as described in claim 2, characterized in that, The nth-level sub-driving circuit also includes: The pull-down sustaining module (50) is connected to the other end of the first capacitor (110) and is used to pull down and maintain the potential of the nth level control signal to the first reference low potential according to the first reverse signal or the second reverse signal. The pull-down sustaining module (50) is connected to the pull-up module (20) and is used to pull down and maintain the potential of the nth gate drive signal to the second reference low potential according to the first reverse signal or the second reverse signal, and to pull down and maintain the potential of the nth trigger signal to the first reference low potential.

6. The gate driving circuit as described in claim 5, characterized in that, The nth-level sub-driving circuit also includes: The first inverter module (610) is connected to the other end of the first capacitor (110) and the pull-down sustaining module (50), and is used to output a first inverted signal to the pull-down sustaining module (50) according to the first local clock signal, the nth level control signal and the n-4th level trigger signal. The second inverter module (620) is connected to the other end of the first capacitor (110) and the pull-down sustaining module (50), and is used to output a second inverted signal to the pull-down sustaining module (50) according to the second local clock signal, the nth level control signal and the n-4th level trigger signal; wherein the first local clock signal is opposite to the second local clock signal.

7. The gate driving circuit as described in any one of claims 2 to 6, characterized in that, The pull-up module (20) includes: The first transistor (210) has a first terminal connected to the other terminal of the first capacitor (110) for acquiring the nth level control signal, a second terminal for acquiring the clock signal, and a third terminal for outputting the nth level trigger signal. The second transistor (220) has its first terminal connected to the other terminal of the first capacitor (110) for acquiring the nth level control signal, its second terminal for acquiring the clock signal, and its third terminal for outputting the nth level gate drive signal. A second capacitor (230) is connected at one end to the first end of the second transistor (220) and at the other end to the third end of the second transistor (220).

8. The gate driving circuit as described in claim 3, characterized in that, The reset module (30) includes: The third transistor (310) has a first terminal for acquiring the reset signal, a second terminal for being connected to the other terminal of the first capacitor (110) for acquiring the nth level control signal, and a third terminal for acquiring the first reference low potential.

9. The gate driving circuit as described in claim 4, characterized in that, The drop-down module (40) includes: The fourth transistor (410) has a first terminal for acquiring the (n+5)th stage trigger signal of the (n+5)th stage sub-driving circuit, a second terminal for connecting to the other terminal of the first capacitor (110) for acquiring the nth stage control signal, and a third terminal for acquiring the first reference low potential. The fifth transistor (420) has a first terminal for acquiring the gate drive signal of the (n+4)th stage of the (n+4)th stage sub-driving circuit, a second terminal for being connected to the pull-up module (20) for acquiring the gate drive signal of the nth stage, and a third terminal for acquiring the second reference low potential.

10. The gate driving circuit as described in claim 5, characterized in that, The pull-down sustaining module (50) includes: The sixth transistor (510) has a first terminal for acquiring the first inverted signal, a second terminal for connecting to the other terminal of the first capacitor (110) for acquiring the nth level control signal, and a third terminal for acquiring the first reference low potential. The seventh transistor (520) has a first terminal for acquiring the first inverted signal, a second terminal for being connected to the pull-up module (20) for acquiring the nth trigger signal, and a third terminal for acquiring the first reference low potential. The eighth transistor (530) has a first terminal for acquiring the first inverted signal, a second terminal for being connected to the pull-up module (20) for acquiring the nth gate drive signal, and a third terminal for acquiring the second reference low potential.

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