Goa driving circuit and display device
By simplifying the pull-down sustaining control module of the GOA driving circuit and using the fifth transistor to implement the pull-down sustaining function, the problems of complex GOA driving circuit structure and high cost are solved, and the display panel bezel is reduced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- ZHEJIANG LAIBAO DISPLAY TECHNOLOGY CO LTD
- Filing Date
- 2025-05-30
- Publication Date
- 2026-05-29
AI Technical Summary
The existing GOA driving circuit has a complex structure, high cost and large display panel bezel, mainly because the traditional inverting module requires at least 4 TFTs.
A GOA driving circuit is adopted, including a pull-up module, an input module, a pull-down module, a pull-down sustaining module, a pull-down sustaining control module, and a reset module. The pull-down sustaining control function is realized through a fifth transistor, simplifying the circuit structure.
Pull-down sustain control can be achieved with only one transistor, simplifying the circuit structure, saving costs, and reducing the bezel of the display panel.
Smart Images
Figure CN224304345U_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of display technology, and in particular relates to a GOA driving circuit and display device. Background Technology
[0002] Integrating a gate driver on array (GOA) circuitry onto a glass substrate creates a scanning drive for the display panel. Compared to traditional gate chip-based driving techniques, GOA technology significantly reduces manufacturing costs and allows for smaller left and right bezels on the display panel. Each GOA driving module outputs a scan signal for each row, driving the pixel units in that row. Multiple GOA driving modules are cascaded to form a GOA driving circuit, enabling line-by-line scanning of the display panel.
[0003] The pull-down sustaining circuit of the related GOA driving circuit is controlled by the inverted signal of the pull-down control node, which requires the setting of an inverting module. Traditional inverting modules require at least 4 TFTs, resulting in a complex circuit structure, high cost, and a large display panel bezel.
[0004] Therefore, the related GOA driving circuit has a complex structure, high cost, and a large display panel bezel. Utility Model Content
[0005] The purpose of this application is to provide a GOA driving circuit and display device, which aims to solve the problems of complex structure, high cost and large bezel of the related GOA driving circuit.
[0006] This application provides a GOA driving circuit, including a pull-up module, an input module, a pull-down module, a pull-down sustaining module, a pull-down sustaining control module, and a reset module;
[0007] The input module is connected to the first input signal terminal and the pull-up control node;
[0008] The reset module is connected to the pull-up control node and the reset signal terminal;
[0009] The pull-up module is connected to the clock signal terminal, the pull-up control node, and the output terminal of the GOA driver circuit.
[0010] The pull-down sustain control module includes a fifth transistor, which is connected to the pull-down control node, sustain signal terminal and sustain adjustment signal terminal, and is used to output a sustain control signal to the pull-down control node according to the sustain signal and sustain adjustment signal;
[0011] The pull-down sustaining module is connected to the output terminal of the pull-down control node, the pull-up control node, and the GOA driver circuit, and is used to pull down the output terminals of the pull-up control node and the GOA driver circuit to a low level according to the sustaining control signal;
[0012] The pull-down module is connected to the pull-up control node and the second input signal terminal;
[0013] The sustain signal is located after the falling edge of the signal of the pull-up control node.
[0014] In one embodiment, the input module is used to receive a first input signal and transmit the first input signal to the pull-up control node;
[0015] The input module includes a first transistor;
[0016] The drain and gate of the first transistor are connected to the first input signal terminal;
[0017] The source of the first transistor is connected to the pull-up control node.
[0018] In one embodiment, the pull-up module is used to receive a clock signal and, in response to a high-level clock signal and a high-level pull-up control node signal, outputs a high-level output signal from the output terminal of the GOA driver circuit.
[0019] The pull-up module includes a second transistor and a bootstrap capacitor;
[0020] The gate of the second transistor and the first terminal of the bootstrap capacitor are both connected to the pull-up control node;
[0021] The source of the second transistor and the second terminal of the bootstrap capacitor are both connected to the output terminal of the GOA driving circuit;
[0022] The drain of the second transistor is connected to the clock signal terminal to receive the clock signal.
[0023] In one embodiment, the pull-down sustaining module is specifically used to maintain the output of the GOA driving circuit and the pull-up control node at a low level in response to the signal of the square wave sustaining control node; the pull-down sustaining module includes a third transistor and a fourth transistor;
[0024] The drain of the third transistor is connected to the output terminal of the GOA driving circuit, the drain of the fourth transistor is connected to the pull-up control node, the gates of the third transistor and the fourth transistor are connected to the pull-down control node, and the sources of the third transistor and the fourth transistor are connected to a low voltage source.
[0025] In one embodiment, the pull-down sustaining control module includes a fifth transistor;
[0026] The drain of the fifth transistor is connected to the sustain signal terminal to receive the sustain signal;
[0027] The gate of the fifth transistor is connected to the sustain adjustment signal terminal to receive the sustain adjustment signal;
[0028] The source of the fifth transistor is connected to the pull-down control node to output the sustain control signal.
[0029] The reset module is also connected to the output terminal of the GOA drive circuit.
[0030] In one embodiment, the pull-down module is used to receive a second input signal, and in response to a high-level second input signal, pulls the pull-up control node down to a low level;
[0031] The pull-down module includes an eighth transistor;
[0032] The drain of the eighth transistor is connected to the pull-up control node;
[0033] The source of the eighth transistor is connected to a low-voltage source;
[0034] The gate of the eighth transistor is connected to the second input signal terminal to receive the second input signal.
[0035] In one embodiment, the first input signal is the output signal of the GOA driving circuit in the upper k rows; the second input signal is the output signal of the GOA driving circuit in the lower k rows; the reset signal is located before the output signal of the GOA driving circuit in the upper k rows and after the output signal of the GOA driving circuit in the lower k rows; where k is a positive integer;
[0036] The sustaining adjustment signal is the clock signal of the GOA driving circuit of the j-th row; j is a positive integer.
[0037] This utility model embodiment also provides a display device, which includes the above-described GOA driving circuit.
[0038] In one embodiment, the display device includes a display units, each display unit including b rows of the GOA driving circuit described above;
[0039] Wherein, the sustain signal of the (c+1)th display unit has the same waveform as the sustain signal of the cth display unit, and the phase of the sustain signal of the (c+1)th display unit is delayed by 180 degrees from the phase of the sustain signal of the cth display unit; a and b are positive integers, b is an even number, and c is a positive integer less than a.
[0040] j is half of b.
[0041] The beneficial effects of this utility model embodiment compared with the prior art are as follows: Since the pull-down sustaining control module includes a fifth transistor, it outputs a sustaining control signal to the pull-down control node according to the sustaining signal and the sustaining adjustment signal; so that the pull-down sustaining module pulls down the output terminals of the pull-up control node and the GOA driving circuit to a low level according to the sustaining control signal; therefore, only one transistor is needed to realize the pull-down sustaining control function, which simplifies the circuit structure, saves costs, and reduces the bezel of the display panel. Attached Figure Description
[0042] To more clearly illustrate the technical utility model in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0043] Figure 1 A schematic diagram of a GOA driving circuit provided in an embodiment of this application;
[0044] Figure 2 Waveform diagrams of various signals of a GOA driving circuit provided in an embodiment of this application;
[0045] Figure 3 This is a partial example circuit schematic diagram of a GOA driving circuit provided in an embodiment of this application. Detailed Implementation
[0046] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.
[0047] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.
[0048] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0049] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0050] Figure 1 A schematic diagram of the GOA driving circuit provided in a preferred embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are described in detail below:
[0051] The aforementioned GOA driving circuit includes a pull-up module 10, an input module 20, a pull-down module 30, a pull-down sustaining module 40, a pull-down sustaining control module 50, and a reset module 60.
[0052] Input module 20 is connected to the first input signal terminal and the pull-up control node Qn.
[0053] The reset module 60 is connected to the pull-up control node Qn and the reset signal terminal.
[0054] Pull-up module 10 connects to the clock signal terminal, the pull-up control node Qn, and the output terminal of the GOA driver circuit.
[0055] The pull-down sustaining control module 50 includes a fifth transistor, which is connected to the pull-down control node, the sustaining signal terminal and the sustaining adjustment signal terminal, and is used to output a sustaining control signal to the pull-down control node according to the sustaining signal CLKmn and the sustaining adjustment signal CLKm-j.
[0056] The pull-down sustaining module 40 is connected to the pull-down control node Kn, the pull-up control node Qn, and the output of the GOA driver circuit. It is used to maintain the output of both the pull-up control node Qn and the GOA driver circuit at a low level according to the sustaining control signal.
[0057] The pull-down module 30 is connected to the pull-up control node Qn and the second input signal terminal;
[0058] The sustain signal CLKmn is located after the falling edge of the signal of the pull-up control node.
[0059] In a specific implementation, the input module 20 is used to access the first input signal Gn-k and transmit the first input signal Gn-k to the pull-up control node Qn.
[0060] The pull-up module 10 is used to receive the clock signal CLKm, and in response to the high-level clock signal CLKm and the high-level pull-up control node Qn, it outputs a high-level output signal Gn from the output terminal of the GOA driver circuit.
[0061] The pull-down sustaining module 40 is specifically used to maintain the output of the GOA drive circuit and the pull-up control node Qn at a low level in response to the signal of the square wave pull-down control node Kn.
[0062] The pull-down module 30 is used to receive the second input signal Gn+k, and in response to the high level of the second input signal Gn+k, it pulls down the pull-up control node Qn to a low level.
[0063] In one embodiment, the reset module 60 is also connected to the output terminal of the GOA driving circuit.
[0064] Figure 2 The waveforms of various signals in the GOA drive circuit are shown below. Figure 2 right Figure 1 The principle of the GOA driving circuit shown will be further explained:
[0065] During phase A to B, the reset signal RESET is high, while the sustain signal CLKmn, the first input signal Gn-k, and the second input signal Gn+k are low. The pull-down module 30 is turned off based on the low-level second input signal Gn+k. The input module 20 transmits the low-level first input signal Gn-k to the pull-up control node Qn, making the pull-up control node Qn low. The pull-down sustain control module 50 outputs a low-level sustain control signal to the pull-down control node Kn based on the low-level sustain signal CLKmn and the sustain adjustment signal. Simultaneously, the reset module 60 receives the high-level reset signal RESET to pull the pull-up control node Qn low. Since the pull-down sustain module 40 is in the off state, the pull-up control node Qn and the output of the GOA driver circuit are effectively reset, and the output of the GOA driver circuit outputs a low-level output signal Gn.
[0066] During phases B to C, the reset signal RESET, the sustain signal CLKmn, the first input signal Gn-k, and the second input signal Gn+k are all at low levels. The pull-down module 30 is turned off based on the low-level second input signal Gn+k. The input module 20 transmits the low-level first input signal Gn-k to the pull-up control node Qn, making the pull-up control node Qn low. The pull-down sustain control module 50 outputs a low-level sustain control signal to the pull-down control node Kn based on the low-level sustain signal CLKmn and the sustain adjustment signal. Simultaneously, the reset module 60 stops resetting the pull-up control node Qn, making the pull-down control node Kn low. Thus, the pull-down sustain module 40 is in the off state, and the output terminals of the pull-up control node Qn and the GOA drive circuit are maintained at low levels. The output terminal of the GOA drive circuit outputs a low-level output signal Gn.
[0067] During the C to D phase, the first input signal Gn-k is high, while the clock signal CLKm, reset signal RESET, sustain signal CLKmn, and second input signal Gn+k are all low. The pull-down module 30 is turned off based on the low-level second input signal Gn+k. The input module 20 transmits the high-level first input signal Gn-k to the pull-up control node Qn, which is high (first voltage). The pull-down sustain control module 50 outputs a low-level sustain control signal to the pull-down control node Kn based on the low-level sustain signal CLKmn and sustain adjustment signal. Simultaneously, the reset module 60 stops resetting the pull-up control node Qn, and the pull-down control node Kn is low, thus the pull-down sustain module 40 is in the off state. The pull-up module 10 receives the low-level clock signal CLKm and, in response to the high-level pull-up control node Qn, transmits the low-level clock signal CLK to the output of the GOA driver circuit. The output of the GOA driver circuit outputs a low-level output signal Gn.
[0068] During stages D to E, the clock signal CLKm is high, while the sustain signal CLKmn, the first input signal Gn-k, the reset signal RESET, and the second input signal Gn+k are all low. The pull-down module 30 shuts down based on the low-level second input signal Gn+k, the input module 20 shuts down based on the low-level first input signal Gn-k, the pull-up control node Qn remains high, and the pull-down sustain control module 50 outputs a low-level sustain control signal to the pull-down control node Kn based on the low-level sustain signal CLKmn and the sustain adjustment signal. Simultaneously, the reset module 60 stops. The pull-up control node Qn is reset, and the pull-down control node Kn is at a low level, thus the pull-down maintenance module 40 is in the off state. The pull-up module 10 is connected to a high-level clock signal CLKm, and in response to the high-level signal of the pull-up control node Qn, it transmits the high-level clock signal CLKm to the output of the GOA driver circuit. It is worth noting that due to the bootstrap effect of the capacitor in the pull-up module 10, the high level maintained by the pull-up control node Qn is the second voltage, which is greater than the first voltage. The output of the GOA driver circuit outputs a high-level output signal Gn.
[0069] During stages E to F, the sustain signal CLKmn, the second input signal Gn+k, the reset signal RESET, the clock signal CLK, and the first input signal Gn-k are all at low levels. The pull-down module 30 is turned off based on the low-level second input signal Gn+k, the input module 20 is turned off based on the low-level first input signal Gn-k, the pull-up control node Qn remains high, and the pull-down sustain control module 50 outputs a low-level sustain control signal to the pull-down control node Kn based on the low-level sustain signal CLKmn and the sustain adjustment signal. Simultaneously, the reset signal... Module 60 stops resetting the pull-up control node Qn, and the pull-down control node Kn is at a low level, thus the pull-down maintenance module 40 is in the off state. The pull-up module 10 receives a low-level clock signal CLKm and, in response to the high-level signal of the pull-up control node Qn, transmits the low-level clock signal CLKm to the output of the GOA driver circuit. It is worth noting that, since the capacitor in the pull-up module 10 is no longer bootstrapping, the high level maintained by the pull-up control node Qn is the first voltage, and the output of the GOA driver circuit outputs a low-level output signal Gn.
[0070] During stages F to G, the second input signal Gn+k is high, while the reset signal RESET, the sustain signal CLKmn, and the first input signal Gn-k are all low. Input module 20 transmits the low-level first input signal Gn-k to the pull-up control node Qn, and pull-down module 30 receives the high-level second input signal Gn+k. In response to the high-level second input signal Gn+k, it pulls the pull-up control node Qn down to a low level. Pull-down sustain control module 50 outputs a low-level sustain control signal to the pull-down control node Kn based on the low-level sustain signal CLKmn and sustain adjustment signal. Simultaneously, reset module 60 stops resetting the pull-up control node Qn, and the pull-down control node Kn is low. Thus, pull-down sustain module 40 is in a closed state, and both the pull-up control node Qn and the output of the GOA driver circuit remain at a low level. The output of the GOA driver circuit outputs a low-level output signal Gn.
[0071] The principle is the same as that of the G to H stage, so it will not be repeated here.
[0072] In the subsequent stage (H), the sustain signal CLKmn is a square wave, and the reset signal RESET, the first input signal Gn-k, and the second input signal Gn+k are all at low levels. The pull-down module 30 is turned off according to the low-level second input signal Gn+k. The input module 20 transmits the low-level first input signal Gn-k to the pull-up control node Qn, and the pull-up control node Qn is at a low level. The pull-down sustain control module 50 outputs a square wave sustain control signal to the pull-down control node Kn according to the square wave sustain signal CLKmn and the sustain adjustment signal. At the same time, the reset module 60 stops resetting the pull-up control node Qn, and the pull-down control node Kn is a square wave. Thus, the pull-down sustain module 40 is in a state of switching between off and on, so that the output of the pull-up control node Qn and the GOA drive circuit is maintained at a low level. The output of the GOA drive circuit outputs a low-level output signal Gn.
[0073] It is worth emphasizing that the first input signal Gn-k is the output signal Gn of the GOA driving circuit in the kth row above; the second input signal Gn+k is the output signal Gn of the GOA driving circuit in the kth row below.
[0074] It is understandable that k is a positive integer.
[0075] It should be noted that the reset signal RESET is located before the output signal Gn of the GOA driver circuit in the upper k rows and after the output signal Gn of the GOA driver circuit in the lower k rows.
[0076] Setting the RESET signal between the output signals Gn of the upper k-line GOA drive circuit and the lower k-line GOA drive circuit allows the GOA drive circuit to be reset during the scanning interval, thereby releasing excess charge in the GOA drive circuit and enabling it to enter a stable operating state, thus improving the stability and reliability of the GOA drive circuit.
[0077] The adjustment signal is maintained as the clock signal of the GOA drive circuit of the j-th row; j is a positive integer.
[0078] Figure 3 The illustration shows a partial example circuit structure of the GOA driving circuit provided in an embodiment of the present invention. For ease of explanation, only the parts related to the embodiment of the present invention are shown, and are described in detail below:
[0079] The input module 20 includes a first transistor T1; the drain and gate of the first transistor T1 are connected to the first input signal terminal; the source of the first transistor T1 is connected to the pull-up control node Qn.
[0080] The pull-up module 10 includes a second transistor T2 and a bootstrap capacitor C1.
[0081] The gate of the second transistor T2 and the first terminal of the bootstrap capacitor C1 are connected to the pull-up control node Qn; the source of the second transistor T2 and the second terminal of the bootstrap capacitor C1 are connected to the output terminal of the GOA driving circuit; the drain of the second transistor T2 is connected to the clock signal terminal to receive the clock signal CLK.
[0082] The pull-down sustaining module 40 includes a third transistor T3 and a fourth transistor T4.
[0083] The drain of the third transistor T3 is connected to the output of the GOA drive circuit, the drain of the fourth transistor T4 is connected to the pull-up control node Qn, the gates of the third transistor T3 and the fourth transistor T4 are connected to the pull-down control node Kn, and the sources of the third transistor T3 and the fourth transistor T4 are connected to the low voltage source VSS.
[0084] The pull-down sustaining control module 50 includes a fifth transistor T5;
[0085] The drain of the fifth transistor T5 is connected to the sustain signal terminal to receive the sustain signal CLKmn; the gate of the fifth transistor T5 is connected to the sustain adjustment signal terminal to receive the sustain adjustment signal CLKm-j; the source of the fifth transistor T5 is connected to the pull-down control node Kn to output the sustain control signal.
[0086] The reset module 60 includes a sixth transistor T6 and a seventh transistor T7;
[0087] The gate of the sixth transistor T6 and the gate of the seventh transistor T7 are both connected to the reset signal terminal to receive the reset signal RESET; the source of the sixth transistor T6 and the source of the seventh transistor T7 are both connected to the pull-down control node Kn; the drain of the sixth transistor T6 is connected to the pull-up control node Qn; and the drain of the seventh transistor T7 is connected to the output terminal of the GOA driving circuit.
[0088] The pull-down module 30 includes an eighth transistor T8.
[0089] The drain of the eighth transistor T8 is connected to the pull-up control node Qn; the source of the eighth transistor T8 is connected to the low voltage source VSS; the gate of the eighth transistor T8 is connected to the second input signal terminal to receive the second input signal Gn+k.
[0090] It should be noted that the first transistor T1 to the eighth transistor T10 mentioned above can all be NMOS transistors.
[0091] The following combination Figure 2 right Figure 3 The working principle shown will be further explained as follows:
[0092] During phase A to B, the reset signal RESET is high, while the sustain signal CLKmn, the first input signal Gn-k, and the second input signal Gn+k are low. The eighth transistor T8 is turned off based on the low-level second input signal Gn+k. The gate of the first transistor T1 is connected to the low-level first input signal Gn-k, turning off the first transistor T1. The pull-up control node Qn is low, and the drain of the fifth transistor T5 is connected to the low-level sustain signal CLKmn. Therefore, the fifth transistor T5 outputs a low-level sustain control signal to the pull-down control node Kn, thus turning off the third transistor T3 and the fourth transistor T4. Simultaneously, the gates of the sixth transistor T6 and the seventh transistor T7 are connected to the high-level reset signal RESET, connecting the pull-up control node Qn and the output of the GOA drive circuit to the low-voltage source VSS. Since the third transistor T3 and the fourth transistor T4 are off, the pull-up control node Qn and the output of the GOA drive circuit are effectively reset, and the output of the GOA drive circuit outputs a low-level output signal Gn.
[0093] During phases B to C, the reset signal RESET, the sustain signal CLKmn, the clock signal CLK, the first input signal Gn-k, and the second input signal Gn+k are all at low levels. The eighth transistor T8 is turned off based on the low-level second input signal Gn+k. The gate of the first transistor T1 is connected to the low-level first input signal Gn-k, so the first transistor T1 is turned off, the pull-up control node Qn is at a low level, and the drain of the fifth transistor T5 is connected to the low-level sustain signal CLKmn. Therefore, the fifth transistor T5 outputs a low-level sustain control signal to the pull-down control node Kn, thereby turning off the third transistor T3 and the fourth transistor T4. At the same time, the gates of the sixth transistor T6 and the seventh transistor T7 are connected to the low-level reset signal RESET, so that the pull-up control node Qn and the output of the GOA drive circuit are disconnected from the low voltage source VSS. The output of the GOA drive circuit maintains the output of the low-level output signal Gn.
[0094] During stages C to D, the first input signal Gn-k is high, while the sustain signal CLKmn, reset signal RESET, clock signal CLKm, and second input signal Gn+k are all low. The eighth transistor T8 is turned off based on the low-level second input signal Gn+k. The gate of the first transistor T1 is connected to the high-level first input signal Gn-k, and the drain of the first transistor T1 transmits the high-level first input signal Gn-k to the source of the first transistor T1. The pull-up control node Qn is high (first voltage) and charges the bootstrap capacitor C1. The drain of the fifth transistor T5 is connected to the low-level sustain signal CLKmn, so the fifth transistor T5 outputs a low-level sustain control signal to the pull-down control node Kn, thereby turning off the third transistor T3 and the fourth transistor T4. Simultaneously, the gates of the sixth transistor T6 and the seventh transistor T7 are connected to the low-level reset signal RESET to turn off the sixth transistor T6 and the seventh transistor T7. The second transistor T2 is turned off based on the high-level pull-up control node Qn. The signal is turned on, and the low-level clock signal CLK is transmitted to the output of the GOA driver circuit. The output of the GOA driver circuit outputs a low-level output signal Gn.
[0095] During stages D to E, the clock signal CLKm is high, while the sustain signal CLKmn, the first input signal Gn-k, the reset signal RESET, and the second input signal Gn+k are all low. The eighth transistor T8 is turned off based on the low-level second input signal Gn+k. The gate of the first transistor T1 is connected to the low-level first input signal Gn-k, turning off the first transistor T1. Since the bootstrap capacitor C1 was charged and stored energy in the previous stage, the pull-up control node Qn is high. The drain of the fifth transistor T5 is connected to the low-level sustain signal CLKmn, so the fifth transistor T5 outputs a low-level sustain control signal to the pull-down control node Kn, thus turning off the third transistor T3 and the fourth transistor T4. Simultaneously, the gates of the sixth transistor T6 and the seventh transistor T7 are connected to the low-level reset signal RESET, causing the sixth transistor T6 and the seventh transistor T7 to turn off. The second transistor T2 is turned off based on the high-level pull-up control node Qn. The signal is turned on, and the high-level clock signal CLKm is transmitted to the output of the GOA driver circuit. Due to the bootstrap effect of the bootstrap capacitor C1, the pull-up control node Qn is raised to the high level of the second voltage, where the second voltage is greater than the first voltage. The output of the GOA driver circuit outputs a high-level output signal Gn.
[0096] During stages E to F, the sustain signal CLKmn, clock signal CLK, first input signal Gn-k, reset signal RESET, and second input signal Gn+k are all low. The eighth transistor T8 is turned off based on the low-level second input signal Gn+k. The gate of the first transistor T1 is connected to the low-level first input signal Gn-k, turning off the first transistor T1. Due to the energy stored in the bootstrap capacitor C1 in the previous stage, the pull-up control node Qn is high. The drain of the fifth transistor T5 is connected to the low-level sustain signal CLKmn, so the fifth transistor T5 outputs a low-level sustain control signal to the pull-down control node Kn, thus turning off the third transistor T3 and the fourth transistor T4. Simultaneously, the gates of the sixth transistor T6 and the seventh transistor T7 are connected to the low-level reset signal RESET, turning off the sixth transistor T6 and the seventh transistor T7. The second transistor T2 is turned on based on the high-level pull-up control node Qn and transmits the low-level clock signal CLKm to the output of the GOA driver circuit. Since the bootstrap capacitor C1 is no longer bootstrapping at this time, the pull-up control node Qn... When the first voltage is high, the output terminal of the GOA driver circuit outputs a low-level output signal Gn.
[0097] During stages F to G, the second input signal Gn+k is high, while the reset signal RESET, the sustain signal CLKmn, and the first input signal Gn-k are all low. The gate of the first transistor T1 is connected to the low-level first input signal Gn-k, turning off the first transistor T1. The eighth transistor T8 is turned on according to the high-level second input signal Gn+k and pulls the pull-up control node Qn down to a low level. The drain of the fifth transistor T5 is connected to the low-level sustain signal CLKmn, so the fifth transistor T5 outputs a low-level sustain control signal to the pull-down control node Kn, thereby turning off the third transistor T3 and the fourth transistor T4. At the same time, the gates of the sixth transistor T6 and the seventh transistor T7 are connected to the low-level reset signal RESET to turn off the sixth transistor T6 and the seventh transistor T7, so that the pull-up control node Qn and the output of the GOA drive circuit are both maintained at a low level. The output of the GOA drive circuit outputs a low-level output signal Gn.
[0098] The principle is the same as that of the G to H stage, so it will not be repeated here.
[0099] In the phase after H, the maintenance signal CLKmn is a square wave, and the reset signal RESET, the first input signal Gn-k, and the second input signal Gn+k are all at low level;
[0100] The eighth transistor T8 is turned off according to the low-level second input signal Gn+k. The gate of the first transistor T1 is connected to the low-level first input signal Gn-k, and the first transistor T1 is turned off. The pull-up control node Qn is at a low level. The drain of the fifth transistor T5 is connected to the square wave sustain signal CLKmn. Therefore, the fifth transistor T5 outputs a square wave sustain control signal to the pull-down control node Kn. The pull-down control node Kn is a square wave, so the third transistor T3 and the fourth transistor T4 are in a switching state between off and on, so that the output of the pull-up control node Qn and the GOA drive circuit is maintained at a low level. At the same time, the gate of the sixth transistor T6 and the gate of the seventh transistor T7 are connected to the low-level reset signal RESET, so that the pull-up control node Qn and the output of the GOA drive circuit are disconnected from the low voltage source VSS. The output of the GOA drive circuit maintains the output signal Gn at a low level.
[0101] This utility model embodiment also provides a display device, which includes the above-described GOA driving circuit.
[0102] In one embodiment, the display device includes a display units, each display unit including b rows of GOA driving circuits as described above; wherein the sustain signal of the (c+1)th display unit has the same waveform as the sustain signal of the cth display unit, and the phase of the sustain signal of the (c+1)th display unit is delayed by 180 degrees from the phase of the sustain signal of the cth display unit; a and b are positive integers, b is an even number, c is a positive integer less than a; j is half of b.
[0103] It is understandable that, since each display unit displays sequentially, the phase of the sustain signal of the (c+1)th display unit is delayed by 180 degrees from the phase of the sustain signal of the cth display unit, thereby ensuring the accuracy of the triggering timing of the pull-down sustain function.
[0104] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.
[0105] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.
Claims
1. A GOA driving circuit, characterized in that, It includes a pull-up module, an input module, a pull-down module, a pull-down sustain module, a pull-down sustain control module, and a reset module; The input module is connected to the first input signal terminal and the pull-up control node; The reset module is connected to the pull-up control node and the reset signal terminal; The pull-up module is connected to the clock signal terminal, the pull-up control node, and the output terminal of the GOA driver circuit. The pull-down sustain control module includes a fifth transistor, which is connected to the pull-down control node, sustain signal terminal and sustain adjustment signal terminal, and is used to output a sustain control signal to the pull-down control node according to the sustain signal and sustain adjustment signal; The pull-down sustaining module is connected to the output terminal of the pull-down control node, the pull-up control node, and the GOA driver circuit, and is used to pull down the output terminals of the pull-up control node and the GOA driver circuit to a low level according to the sustaining control signal; The pull-down module is connected to the pull-up control node and the second input signal terminal; The sustain signal is located after the falling edge of the signal of the pull-up control node.
2. The GOA driving circuit as described in claim 1, characterized in that, The input module is used to receive a first input signal and transmit the first input signal to the pull-up control node; The input module includes a first transistor; The drain and gate of the first transistor are connected to the first input signal terminal; The source of the first transistor is connected to the pull-up control node.
3. The GOA driving circuit as described in claim 1, characterized in that, The pull-up module is used to receive a clock signal, and in response to a high-level clock signal and a high-level pull-up control node signal, it outputs a high-level output signal from the output terminal of the GOA driver circuit. The pull-up module includes a second transistor and a bootstrap capacitor; The gate of the second transistor and the first terminal of the bootstrap capacitor are both connected to the pull-up control node; The source of the second transistor and the second terminal of the bootstrap capacitor are both connected to the output terminal of the GOA driving circuit; The drain of the second transistor is connected to the clock signal terminal to receive the clock signal.
4. The GOA driving circuit as described in claim 1, characterized in that, The pull-down sustaining module is specifically used to maintain the output of the GOA driving circuit and the pull-up control node at a low level in response to the signal of the square wave sustaining control node; the pull-down sustaining module includes a third transistor and a fourth transistor; The drain of the third transistor is connected to the output terminal of the GOA driving circuit, the drain of the fourth transistor is connected to the pull-up control node, the gates of the third transistor and the fourth transistor are connected to the pull-down control node, and the sources of the third transistor and the fourth transistor are connected to a low voltage source.
5. The GOA driving circuit as described in claim 1, characterized in that, The pull-down sustaining control module includes a fifth transistor; The drain of the fifth transistor is connected to the sustain signal terminal to receive the sustain signal; The gate of the fifth transistor is connected to the sustain adjustment signal terminal to receive the sustain adjustment signal; The source of the fifth transistor is connected to the pull-down control node to output the sustain control signal.
6. The GOA driving circuit as described in claim 1, characterized in that, The reset module is also connected to the output terminal of the GOA drive circuit.
7. The GOA driving circuit as described in claim 1, characterized in that, The pull-down module is used to receive a second input signal, and in response to a high-level second input signal, it pulls the pull-up control node down to a low level; The pull-down module includes an eighth transistor; The drain of the eighth transistor is connected to the pull-up control node; The source of the eighth transistor is connected to a low-voltage source; The gate of the eighth transistor is connected to the second input signal terminal to receive the second input signal.
8. The GOA driving circuit as described in any one of claims 1 to 7, characterized in that, The first input signal is the output signal of the GOA driving circuit in the upper k rows; the second input signal is the output signal of the GOA driving circuit in the lower k rows; the reset signal is located before the output signal of the GOA driving circuit in the upper k rows and after the output signal of the GOA driving circuit in the lower k rows; where k is a positive integer. The sustaining adjustment signal is the clock signal of the GOA driving circuit of the j-th row; j is a positive integer.
9. A display device, characterized in that, The display device includes the GOA driving circuit as described in any one of claims 1 to 8.
10. The display device as claimed in claim 9, characterized in that, The display device includes a display units, each display unit including b rows of GOA driving circuits as described in any one of claims 1 to 9; Wherein, the sustain signal of the (c+1)th display unit has the same waveform as the sustain signal of the cth display unit, and the phase of the sustain signal of the (c+1)th display unit is delayed by 180 degrees from the phase of the sustain signal of the cth display unit; a and b are positive integers, b is an even number, and c is a positive integer less than a. j is half of b.