Conventional battery charge and discharge protection circuitry

Abstract

The utility model discloses a routine battery pack charge -discharge protection circuit system, it includes model number is the battery collection chip of BF8915A and model number is GD32A503RC control chip, voltage acquisition terminal of battery collection chip is through passive equalization channel module respectively corresponding the positive pole connection of single monomer electric core of battery pack realizes voltage acquisition and passive equalization, control chip is through voltage detection module to battery pack's end voltage and battery pack charge -discharge terminal voltage carries out the detection, control chip still is connected with bootstrap voltage module, bootstrap voltage module connects battery pack's end voltage and battery pack charge -discharge terminal voltage output charge, discharge voltage limit, battery pack's end voltage and battery pack charge -discharge terminal are connected with MOS array module. The utility model discloses through monitoring, equalization, charge -discharge protection design, provides the hardware realization foundation for preventing the overcharge, overdischarge and overtemperature of battery etc. problem, has applicability to reduce the occurrence of battery use accident.

Description

Technical Field

[0001] This utility model relates to the field of power management technology, specifically to a conventional battery pack charge and discharge protection circuit system. Background Technology

[0002] As the application scope of lithium batteries continues to expand, the safety and stability of lithium battery pack charging and discharging have gained increasing attention. Lithium battery packs typically consist of multiple battery cells connected in series. Due to differences in manufacturing processes and various factors during use, the capacity, internal resistance, and charge / discharge characteristics of each battery cell will vary. This can lead to voltage deviations in individual cells within the battery pack over long-term use. If these voltage deviations are not corrected, some cells may be overcharged or over-discharged, damaging the entire battery pack and affecting its safety and stability.

[0003] Therefore, Battery Management Systems (BMS) have emerged and are increasingly used in aerospace, rail transportation, military equipment, and communication equipment. With the rapid development of electric vehicles, BMS, as the core of vehicle battery pack monitoring and management, is an indispensable component of the entire vehicle. The main functions of a BMS include detecting battery parameters such as voltage, current, and temperature; using appropriate algorithms to estimate and monitor battery capacity and SOC; receiving vehicle commands; controlling contactors during power-on, power-off, and charging processes; and performing battery equalization.

[0004] For example, patent document CN 118921244 A discloses a CAN communication circuit and a battery management system for a battery management system. The CAN communication circuit of the battery management system includes a connector, a terminating resistor circuit, a CAN transceiver, and a controller connected in sequence. The terminating resistor circuit includes a CAN_H line, a CAN_L line, a first resistor, a second resistor, and a first capacitor. The CAN_H line, the first resistor, the first capacitor, and a ground terminal are connected in sequence, and the second resistor is connected to the CAN_L line. The connector includes a first port and a second port. The first port is connected to the first resistor and the first capacitor, and the second port is connected to the second resistor. When the battery management system is located at the end of a CAN bus system, the first port and the second port are connected. This provides a CAN communication scheme that can be adapted to multiple BMS systems simultaneously, providing the conditions for the management system to estimate, monitor, and balance battery capacity and SOC.

[0005] Nevertheless, the quality of battery pack charge / discharge protection boards on the market varies greatly, especially for multi-cell battery packs. These boards need to ensure that the voltage of each battery cell remains within a reasonable range to prevent overcharging or over-discharging, thereby extending the battery pack's lifespan and improving safety. Therefore, it is essential to provide an effective, safe, and economical hardware solution for the charge / discharge protection of multi-cell batteries. Summary of the Invention

[0006] This invention provides a conventional battery pack charge and discharge protection circuit system to improve the effectiveness, safety, and economy of charge and discharge protection for multi-string battery packs.

[0007] To solve the above-mentioned technical problems, the technical solution of this utility model is as follows:

[0008] A conventional battery pack charge / discharge protection circuit system includes a battery acquisition chip (model BF8915A) and a control chip (model GD32A503RC). The voltage acquisition terminal of the battery acquisition chip is connected to the positive terminal of each individual cell in the battery pack via a passive balancing channel module to achieve voltage acquisition and passive balancing. Each individual cell and the passive balancing channel module are equipped with a temperature detection module. The detection signal from the temperature detection module corresponding to each individual cell is connected to the analog input terminal of the battery acquisition chip via an analog switch chip. The detection signal from the temperature detection module of the passive balancing channel module is also connected to the analog input terminal of the battery acquisition chip.

[0009] The SPI communication port of the control chip is connected to the communication interface of the battery acquisition chip through a digital isolation module. The control chip detects the terminal voltage of the battery pack and the charging and discharging terminal voltage of the battery pack through a voltage detection module. The control chip is also connected to a bootstrap voltage module, which outputs charging and discharging voltage limits based on the terminal voltage of the battery pack and the charging and discharging terminal voltage. A MOS array module is connected between the terminal voltage of the battery pack and the charging and discharging terminals, and the charging and discharging voltage limits are connected to the MOS array module to achieve voltage balancing.

[0010] Furthermore, one battery acquisition chip corresponds to the voltage acquisition and passive balancing of sixteen individual battery cells. The passive balancing channel module has sixteen voltage acquisition channels and sixteen passive balancing lines. Each voltage acquisition channel includes two resistors connected in series. One resistor is connected to the positive terminal of the individual battery cell, and the other resistor is connected to a voltage acquisition terminal of the battery acquisition chip and grounded through a capacitor. Each passive balancing line also includes two resistors connected in series. One end of the series connection is between the two resistors in the voltage acquisition channel, and the other end is connected to a balancing switch terminal of the battery acquisition chip. A protection diode and a capacitor are connected between adjacent passive balancing lines. The positive terminal of each individual battery cell is grounded by a capacitor.

[0011] The analog switch chip is model RS2252XTSS16. The temperature signal output terminal of the temperature detection module corresponding to the eight individual battery cells is connected to one of the analog switch chips. The ninth and tenth pins of the analog switch chip are each connected to an analog input terminal of the battery acquisition chip. The temperature signal output terminal of the temperature detection module of the passive equalization channel module is also connected to an analog input terminal of the battery acquisition chip.

[0012] Furthermore, the positive terminal of the battery pack charging / discharging terminal is connected to the first pin of the battery acquisition chip via a resistor and a first discharge tube. The output of the first discharge tube is also connected to a silicon transistor via a resistor. The emitter of the silicon transistor is connected to the sixty-second pin of the battery acquisition chip via a second discharge tube. The base of the silicon transistor is connected to the sixty-third pin of the battery acquisition chip via a resistor. The negative terminal of the battery pack charging / discharging terminal is grounded via a resistor.

[0013] Furthermore, the digital isolation module includes an isolator of model SCM3728ASA, the sixth and seventh pins of the isolator are connected to the fifty-fourth and fifty-third pins of the battery acquisition chip, and the second and third pins of the isolator are connected to the thirty-fourth and thirty-second pins of the control chip.

[0014] Furthermore, the MOS array module includes multiple sets of parallel charge / discharge switch lines. Each set of charge / discharge switch lines includes two NMOS transistors. The drains of the two NMOS transistors are connected, and a voltage detection point is set at the connection point. The source of one NMOS transistor is connected to the positive terminal of the battery pack, and the gate resistor of the NMOS transistor is connected to the charging limit voltage. The source of the other NMOS transistor is connected to the positive terminal of the charge / discharge terminal of the battery pack, and the gate resistor of the NMOS transistor is connected to the discharge limit voltage.

[0015] Furthermore, the voltage detection module includes an operational amplifier chip of model RS624XQ. The twelfth pin of the operational amplifier chip is connected to the positive terminal of the battery pack, the thirteenth pin is connected to the negative terminal of the battery pack, and the fourteenth pin is connected to the forty-fourth pin of the control chip. The fifth pin of the operational amplifier chip is connected to the first pin and the negative terminal of the charging / discharging terminal of the battery pack, the sixth pin is connected to the negative terminal of the battery pack, the sixth pin is connected to the tenth pin, and the eighth pin is connected to the forty-third pin of the control chip.

[0016] The bootstrap voltage module includes two JMS2127STR driver chips. The second and third pins of one driver chip are connected to the forty-sixth and forty-fifth pins of the control chip. The fifth and sixth pins of the driver chip are connected by a resistor, and the fifth pin is connected to the voltage detection point. The sixth pin of the driver chip is also connected to the positive terminal of the battery pack through a resistor and a Zener diode in sequence. The positive terminal of the Zener diode is connected to the seventh pin of the driver chip by a resistor. The seventh pin of the driver chip outputs the charging limit voltage.

[0017] The second and third pins of another driver chip of the bootstrap voltage module are connected to the fifty-fourth and fifty-third pins of the control chip, respectively. The fifth and sixth pins of the driver chip are connected by a resistor, and the fifth pin is connected to the voltage detection point. The sixth pin of the driver chip is also connected to the positive terminal of the charging and discharging terminal of the battery pack in sequence through a resistor and a Zener diode. The positive terminal of the Zener diode is connected to the seventh pin of the driver chip, and the seventh pin of the driver chip outputs the discharge limit voltage.

[0018] The circuit system of this invention is the core hardware component of a Battery Management System (BMS). It realizes the acquisition and processing of voltage and temperature data. Especially for multi-string battery packs, the use of a multi-channel battery acquisition chip greatly reduces the circuit size and complexity, which helps to reduce hardware costs. At the battery acquisition chip level, it implements voltage balancing and abnormal temperature safety functions between individual cells. At the MCU on-chip system level, it implements charge and discharge voltage limiting control for the entire battery pack, effectively protecting the battery pack and ensuring battery safety. Both the battery acquisition chip and the on-chip system are automotive-grade, with mature technology, ensuring their reliability and safety. The overall solution adopts a modular design, which facilitates the addition or removal of detection modules, enabling reusability and scalability of functions, and ensuring that the system has good scalability and maintainability. This invention provides a hardware implementation foundation for preventing battery overcharging, over-discharging, and over-temperature problems, and is applicable to reducing the occurrence of battery usage accidents. Attached Figure Description

[0019] Figure 1 This is a circuit diagram of the battery acquisition chip in a specific embodiment of the present invention.

[0020] Figure 2 This is a schematic diagram of the temperature detection circuit for a single battery cell in a specific embodiment of this utility model.

[0021] Figure 3 This is a schematic diagram of the temperature detection circuit of the passive equalization channel module in a specific embodiment of this utility model.

[0022] Figure 4 This is a circuit diagram of an analog switch chip in a specific embodiment of the present invention.

[0023] Figure 5 This is a schematic diagram of an isolated circuit in a specific embodiment of the present invention.

[0024] Figure 6 This is a circuit diagram of the charging voltage limit in the bootstrap voltage module in a specific embodiment of the present invention.

[0025] Figure 7 This is a circuit diagram of the discharge limit voltage in the bootstrap voltage module in a specific embodiment of the present invention.

[0026] Figure 8 This is a schematic diagram of the battery pack terminal voltage detection circuit in a specific embodiment of the present invention.

[0027] Figure 9 This is a schematic diagram of the detection circuit for the charging and discharging terminal voltage in a specific embodiment of this utility model.

[0028] Figure 10 This is a circuit diagram of a MOS array module in a specific embodiment of the present invention.

[0029] Figure 11 This is a circuit connection diagram of the negative terminal of the battery pack and the negative terminal for charging and discharging in a specific embodiment of this utility model.

[0030] Figure 12 This is a peripheral circuit diagram of the control chip in a specific embodiment of the present invention. Detailed Implementation

[0031] The specific embodiments of this utility model will be further described below with reference to the accompanying drawings. It should be noted that these descriptions are for the purpose of aiding understanding of this utility model, but do not constitute a limitation thereof. Furthermore, the technical features involved in the various embodiments of this utility model described below can be combined with each other as long as they do not conflict with each other.

[0032] In the description of this utility model, it should be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model. Furthermore, in the description of this utility model, "a plurality of" means two or more, unless otherwise explicitly specified.

[0033] After several years of development, Battery Management System (BMS) systems have achieved relatively mature battery charge and discharge management methods in the industry. These methods utilize software management logic implemented through a System-on-a-Chip (MCU) or a central system. BMS software primarily includes data analysis algorithms and safety control strategies. Data analysis algorithms process and analyze the collected data, while safety control strategies prevent safety issues such as overcharging, over-discharging, and over-temperature. Examples include the method for estimating battery state of charge, the battery management system and its driving method disclosed in patent publication CN100547849C; a battery management method and device disclosed in patent publication CN103762624B; and a method for assessing the health status of lithium-ion battery packs disclosed in patent publication CN103823188B. These management algorithms are also widely applied in the engineering of battery management, implemented through software deployment on an MCU or central system to achieve various battery management algorithms and controls. However, the quality of battery pack charge and discharge protection boards in current BMS systems varies greatly. In particular, the circuit boards for multi-string battery packs are complex and have high hardware costs. Therefore, the purpose of this patent is to provide an effective, safe, and economical hardware circuit design scheme for charge and discharge protection of multi-string battery packs.

[0034] This solution provides a conventional battery pack charge / discharge protection circuit system. The core chips used are a BF8915A battery acquisition chip and a GD32A503RC control chip. The battery acquisition chip is used to acquire the voltage of multiple individual cells, avoiding the need for power management chips which have fewer acquisition ports and thus more circuit components. The battery acquisition chip provides terminals capable of acquiring the voltage of 16 series-connected batteries with high synchronization, minimizing the number of chips and reducing hardware costs. The GD32A503RC control chip is an automotive-grade chip with two SPI communication channels for communication with the battery acquisition chip, eight I / O terminals, and two sets of charge / discharge control ports capable of controlling the charge / discharge of the battery pack under two battery acquisition chips. It also has temperature and voltage acquisition expansion ports and supports CAN and RS232 / 485 communication. Therefore, one control chip and two battery acquisition chips can achieve charge / discharge protection control for 32 series-connected batteries, resulting in high hardware integration, a simplified circuit board, clear control logic, effective and accurate charge / discharge control, and guaranteed safety.

[0035] Specifically, the circuit design of the battery acquisition chip is as follows: Figure 1 As shown, the voltage acquisition terminals C0 to C16 of the battery acquisition chip U6_2 are connected to the positive terminals of individual cells in the battery pack via the passive balancing channel module to achieve voltage acquisition and passive balancing. Each individual cell and the passive balancing channel module are equipped with a temperature detection module. The detection signal of the temperature detection module corresponding to the individual cell is connected to the analog input terminal of the battery acquisition chip U6_2 via an analog switch chip. The detection signal of the temperature detection module of the passive balancing channel module is connected to the analog input terminal of the battery acquisition chip U6_2. The number of passive balancing pins of the battery acquisition chip U6_2 is equal to the number of individual battery cells. The passive balancing pins are connected to the positive terminal of the individual battery cells via the passive balancing channel.

[0036] The BF8915A has an internal battery voltage equalization switch, and still... Figure 1For example, taking a battery acquisition chip U6_2 corresponding to 16 series-connected batteries as an example, one battery acquisition chip U6_2 corresponds to the voltage acquisition and passive balancing of sixteen individual battery cells. The passive balancing channel module has sixteen voltage acquisition channels and sixteen passive balancing lines. Taking one voltage acquisition channel as an example, this voltage acquisition channel includes two resistors R12 and R27 connected in series. Resistor R12 is connected to the positive terminal B16 of one individual battery cell, and the other resistor R27 is connected to a voltage acquisition terminal C16 of the battery acquisition chip U6_2 and is also grounded to AGND through a capacitor C10_2. Taking one of the passive balancing lines as an example, this passive balancing line also includes two resistors R29 and R150 connected in series. One end of the series connection of these two resistors is connected between two resistors R12 and R27 connected in series in the voltage acquisition channel. The other end of the series connection of these two resistors R29 and R150 is connected to a balancing switch terminal S16 of the battery acquisition chip U6_2. A protection diode TD1_2 and a capacitor C8_2 are connected between the passive balancing line and the adjacent dynamic balancing line. The positive terminals B16 to B1 of the 16 individual cells are grounded to AGND through capacitors C9_2 to C105_2.

[0037] The analog switch chip in the above embodiment is model RS2252XTSS16. Figure 4 The illustrated embodiment shows that the temperature signal output terminals RT1, RT2, RT5, RT6, RT9, RT10, RT13, and RT14 of the temperature detection module corresponding to the eight individual battery cells are connected to the analog switch chip U3_2. The circuit connection implementation of the analog switch chip U3_2 is as follows: Figure 4 As shown, pins 9 and 10 of the analog switch chip U3_2 are connected to the analog input terminals GPIO0 and GPIO1 (pins 37 and 38) of the battery acquisition chip U6_2, respectively. The temperature signal output terminal of the temperature detection module of the passive equalization channel module is also connected to one of the analog input terminals GPIO2 of the battery acquisition chip U6_2.

[0038] The temperature detection module for each individual battery cell is as follows: Figure 2 As shown, the detection signal from the temperature sensor NTC1 is generated and then connected to the analog switch chip U3_2 via resistor R56_2. The temperature detection module of the passive equalization channel module is as follows... Figure 3As shown, this includes a thermistor R89_2, whose resistance value varies with temperature, resulting in different voltages at the TB_1 terminal. The output signal is connected to the analog input GPIO2 of the battery acquisition chip U6_2 via resistor R44_2. The battery acquisition chip U6_2 has built-in safety functions. In addition to uploading the temperature signal to the MCU, it can also perform response control in case of abnormal temperature to ensure the safety of the battery cell's operating status and equalization process.

[0039] In one specific embodiment, the battery acquisition chip U6_2 also acquires the voltage of the battery pack's charging and discharging terminals, such as... Figure 1 As shown, the positive terminal P+ of the battery pack charging / discharging terminal is connected to the first pin of the battery acquisition chip U6_2 through resistor R24, the first discharge transistor B2_2, and resistor R2_2. The output of the first discharge transistor B2_2 is also connected to a silicon transistor Q1_2 through resistor R1_2. The emitter of the silicon transistor Q1_2 is connected to the sixty-second pin of the battery acquisition chip U6_2 through the second discharge transistor B1_2. The base of the silicon transistor Q1_2 is connected to the sixty-third pin of the battery acquisition chip U6_2 through resistor R8_2. The negative terminal P- of the battery pack charging / discharging terminal is grounded through resistor F1_2.

[0040] The SPI communication port of the control chip is connected to the communication interface of the battery acquisition chip U6_2 through a digital isolation module. The control chip detects the terminal voltage of the battery pack and the charging and discharging terminal voltage of the battery pack through a voltage detection module. The control chip is also connected to a bootstrap voltage module, which outputs charging and discharging voltage limits based on the terminal voltage of the battery pack and the charging and discharging terminal voltage. A MOS array module is connected between the terminal voltage of the battery pack and the charging and discharging terminals, and the charging and discharging voltage limits are connected to the MOS array module to achieve voltage balancing.

[0041] In one specific embodiment, such as Figure 5 As shown, the digital isolation module includes an isolator U1_2 of model SCM3728ASA. The sixth and seventh pins of the isolator U1_2 are connected to the fifty-fourth and fifty-third pins of the battery acquisition chip U6_2, respectively. The second and third pins of the isolator U1_2 are connected to the thirty-fourth and thirty-second pins of the control chip, respectively.

[0042] In one specific embodiment, such as Figure 10As shown, the MOS array module includes multiple sets of parallel charge / discharge switch lines. Each set of charge / discharge switch lines includes two NMOS transistors. The drains of the two NMOS transistors are connected, and a voltage detection point VS is set at the connection point. Taking one set of charge / discharge switch lines as an example, the source of one NMOS transistor Q6 is connected to the positive terminal BAT+ of the battery pack, and the gate of the NMOS transistor Q6 is connected to the charging limit voltage CHARG_HO through resistor R99; the source of the other NMOS transistor Q7 is connected to the positive terminal P+ of the charge / discharge terminal of the battery pack, and the gate of the NMOS transistor Q7 is connected to the discharge limit voltage DISCHARG_HO through resistor R101. When the battery pack is charging, if the voltage difference between the charging limit voltage CHARG_HO and the positive terminal of the battery causes NMOS transistor Q6 to conduct, it indicates that the battery pack voltage is insufficient and charging needs to continue. The discharge limit voltage DISCHARG_HO is lower than that of the charging terminal P+, so NMOS transistor Q7 is turned off, generating a voltage drop. The charging terminal P+ charges the positive terminal BAT+ of the battery pack through NMOS transistors Q7 and Q6. When the battery pack is sufficiently charged, the voltage at the positive terminal BAT+ rises until the voltage difference with the charging limit voltage CHARG_HO causes NMOS transistor Q6 to turn off. The current flowing from the charging terminal P+ to NMOS transistor Q6 is cut off, and charging stops. When the battery pack is discharging, the charging terminal P+ is the discharging terminal. When the battery pack voltage is sufficient, the voltage difference between the discharge limit voltage DISCHARG_HO and the discharging terminal P+ is sufficient to turn on the NMOS transistor Q7. The positive terminal BAT+ of the battery pack then connects to the discharging terminal P+ through the voltage drop of the NMOS transistor Q6, discharging. When the battery pack voltage is insufficient, the voltage at the discharging terminal P+ decreases until the voltage difference between the discharge limit voltage DISCHARG_HO and the discharging terminal P+ is insufficient to turn on the NMOS transistor Q7. The NMOS transistor Q7 then turns off, and the flow from the positive terminal BAT+ to the discharging terminal P+ is cut off by the NMOS transistor Q7, stopping the discharge. This achieves protection during charging and discharging. The circuit between the negative terminal BAT- and the charging / discharging terminal P- of the battery pack is as follows: Figure 11 As shown, no further details will be provided.

[0043] In one specific embodiment, such as Figure 12 As shown, the peripheral circuit and port design of the control chip U7 are illustrated. Besides communicating with the battery acquisition chip U6_2 to obtain battery charging and discharging voltage, circuit temperature, and cell temperature, the control chip U7 also uses a voltage detection module to detect the voltage at the positive terminal BAT+ and negative terminal BAT- of the battery pack, in order to further monitor and manage the battery status. Figure 8 , 9As shown, the voltage detection module includes an operational amplifier chip of model RS624XQ. The RS624XQ has four built-in operational amplifiers U5A, U5B, U5C, and U5D, which can be used independently. The twelfth pin of the operational amplifier chip is connected to the positive terminal BAT+ of the battery pack via resistors R165, R212, and R213; the thirteenth pin is connected to the negative terminal BAT- of the battery pack via resistor R218; and the fourteenth pin is connected to the forty-fourth pin of the control chip U7 via resistor R215. The fifth pin of the operational amplifier chip is connected to the first pin and the negative terminal P- of the battery pack's charge / discharge terminal via resistor R163. The sixth pin of the operational amplifier chip is connected to the negative terminal BAT- of the battery pack via resistor R171; the sixth pin is connected to the tenth pin via resistors R170 and R225; and the eighth pin is connected to the forty-third pin of the control chip U7 via resistor R227.

[0044] The charging limit voltage CHARG_HO and the discharging limit voltage DISCHARG_HO come from the bootstrap voltage module, such as Figure 6 , 7 As shown, the bootstrap voltage module includes two driver chips, U14 and U15, model JMS2127STR. Figure 6 As shown, the second and third pins of one of the driver chips U14 are connected to the forty-sixth and forty-fifth pins of the control chip U7. The fifth and sixth pins of the driver chip U14 are connected via resistor R98, and the fifth pin is connected to the voltage detection point VS. The sixth pin of the driver chip U14 is also connected to the positive terminal BAT+ of the battery pack via a resistor R96 and a Zener diode SD9. The positive terminal of the Zener diode SD9 is connected to the seventh pin of the driver chip U14 via resistor R93. The seventh pin of the driver chip U14 outputs the charging limit voltage CHARG_HO.

[0045] like Figure 7 As shown, the second and third pins of another driver chip U15 are connected to the fifty-fourth and fifty-third pins of the control chip U7. The fifth and sixth pins of the driver chip U15 are connected via resistor R154, and the fifth pin is connected to the voltage detection point VS. The sixth pin of the driver chip U15 is also connected to the positive terminal P+ of the charging and discharging terminal of the battery pack via a resistor R153 and a Zener diode SD12. The positive terminal of the Zener diode SD12 is connected to the seventh pin of the driver chip U15 via resistor R149. The seventh pin of the driver chip U15 outputs the discharge limit voltage DISCHARG_HO.

[0046] This patent addresses the use of 3.6V-3.7V battery cells (with a configurable charging limit of 4.25V and a discharging limit of 2.75V) connected in series to form a rechargeable battery pack. This specification of battery cell and its composition are relatively common and widely used. Furthermore, due to the modular design of this patent, the circuit parameters can be adjusted to accommodate different battery specifications when battery specifications change. Therefore, this patent has good practicality and wide applicability.

[0047] Of course, the MCU chip of this patent supports multiple communication methods and can interact with other devices. Its communication interface can be implemented through serial port, CAN bus, Ethernet and other means, and further transmit and control data with the electric vehicle's electronic control system.

[0048] The embodiments of this utility model have been described in detail above with reference to the accompanying drawings, but this utility model is not limited to the described embodiments. For those skilled in the art, various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of this utility model, and these variations still fall within the protection scope of this utility model.

Claims

1. A conventional battery pack charge / discharge protection circuit system, characterized in that: This includes a battery acquisition chip of model BF8915A and a control chip of model GD32A503RC; The voltage acquisition terminal of the battery acquisition chip is connected to the positive terminal of each individual cell of the battery pack through the passive equalization channel module to achieve voltage acquisition and passive equalization. Each individual cell and the passive equalization channel module are equipped with a temperature detection module. The detection signal of the temperature detection module corresponding to the individual cell is connected to the analog input terminal of the battery acquisition chip through an analog switch chip. The detection signal of the temperature detection module of the passive equalization channel module is connected to the analog input terminal of the battery acquisition chip. The SPI communication port of the control chip is connected to the communication interface of the battery acquisition chip through a digital isolation module. The control chip detects the terminal voltage of the battery pack and the charging and discharging terminal voltage of the battery pack through a voltage detection module. The control chip is also connected to a bootstrap voltage module, which outputs charging and discharging voltage limits based on the terminal voltage of the battery pack and the charging and discharging terminal voltage. A MOS array module is connected between the terminal voltage of the battery pack and the charging and discharging terminals, and the charging and discharging voltage limits are connected to the MOS array module to achieve voltage balancing.

2. The conventional battery pack charge / discharge protection circuit system according to claim 1, characterized in that: One battery acquisition chip corresponds to the voltage acquisition and passive balancing of sixteen individual battery cells. The passive balancing channel module has sixteen voltage acquisition channels and sixteen passive balancing lines. Each voltage acquisition channel includes two resistors connected in series. One resistor is connected to the positive terminal of the individual battery cell, and the other resistor is connected to a voltage acquisition terminal of the battery acquisition chip and grounded through a capacitor. Each passive balancing line also includes two resistors connected in series. One end of the series connection is between the two resistors in the voltage acquisition channel, and the other end is connected to a balancing switch terminal of the battery acquisition chip. A protection diode and a capacitor are connected between adjacent passive balancing lines. The positive terminal of each individual battery cell is grounded by a capacitor. The analog switch chip is model RS2252XTSS16. The temperature signal output terminal of the temperature detection module corresponding to the eight individual battery cells is connected to one of the analog switch chips. The ninth and tenth pins of the analog switch chip are each connected to an analog input terminal of the battery acquisition chip. The temperature signal output terminal of the temperature detection module of the passive equalization channel module is also connected to an analog input terminal of the battery acquisition chip.

3. The conventional battery pack charge / discharge protection circuit system according to claim 2, characterized in that: The positive terminal of the battery pack charging / discharging terminal is connected to the first pin of the battery acquisition chip via a resistor and a first discharge tube. The output of the first discharge tube is also connected to a silicon transistor via a resistor. The emitter of the silicon transistor is connected to the sixty-second pin of the battery acquisition chip via a second discharge tube. The base of the silicon transistor is connected to the sixty-third pin of the battery acquisition chip via a resistor. The negative terminal of the battery pack charging / discharging terminal is grounded via a resistor.

4. The conventional battery pack charge / discharge protection circuit system according to any one of claims 1 to 3, characterized in that: The digital isolation module includes an isolator of model SCM3728ASA. The sixth and seventh pins of the isolator are connected to the fifty-fourth and fifty-third pins of the battery acquisition chip, respectively, and the second and third pins of the isolator are connected to the thirty-fourth and thirty-second pins of the control chip, respectively.

5. The conventional battery pack charge / discharge protection circuit system according to claim 4, characterized in that: The MOS array module includes multiple sets of parallel charge / discharge switch lines. Each set of charge / discharge switch lines includes two NMOS transistors. The drains of the two NMOS transistors are connected, and a voltage detection point is set at the connection point. The source of one NMOS transistor is connected to the positive terminal of the battery pack, and the gate resistor of the NMOS transistor is connected to the charging limit voltage. The source of the other NMOS transistor is connected to the positive terminal of the charge / discharge terminal of the battery pack, and the gate resistor of the NMOS transistor is connected to the discharge limit voltage.

6. The conventional battery pack charge / discharge protection circuit system according to claim 5, characterized in that: The voltage detection module includes an operational amplifier chip of model RS624XQ. The twelfth pin of the operational amplifier chip is connected to the positive terminal of the battery pack, the thirteenth pin is connected to the negative terminal of the battery pack, and the fourteenth pin is connected to the forty-fourth pin of the control chip. The fifth pin of the operational amplifier chip is connected to the first pin and the negative terminal of the charging / discharging terminal of the battery pack, the sixth pin is connected to the negative terminal of the battery pack, the sixth pin is connected to the tenth pin, and the eighth pin is connected to the forty-third pin of the control chip. The bootstrap voltage module includes two JMS2127STR driver chips. The second and third pins of one driver chip are connected to the forty-sixth and forty-fifth pins of the control chip. The fifth and sixth pins of the driver chip are connected by a resistor, and the fifth pin is connected to the voltage detection point. The sixth pin of the driver chip is also connected to the positive terminal of the battery pack through a resistor and a Zener diode in sequence. The positive terminal of the Zener diode is connected to the seventh pin of the driver chip by a resistor. The seventh pin of the driver chip outputs the charging limit voltage. The second and third pins of another driver chip of the bootstrap voltage module are connected to the fifty-fourth and fifty-third pins of the control chip, respectively. The fifth and sixth pins of the driver chip are connected by a resistor, and the fifth pin is connected to the voltage detection point. The sixth pin of the driver chip is also connected to the positive terminal of the charging and discharging terminal of the battery pack in sequence through a resistor and a Zener diode. The positive terminal of the Zener diode is connected to the seventh pin of the driver chip, and the seventh pin of the driver chip outputs the discharge limit voltage.

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