A phase-locked loop capture device
By designing a phase-locked loop (PLL) capture device consisting of a temperature-compensated crystal oscillator and a frequency and phase detector, and adopting a phase-detection conversion method, the problem of long capture time of digital PLLs is solved, achieving fast locking and low-cost PLL capture, and simplifying the circuit structure.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- CHENGDU YAGUANG ELECTRONICS
- Filing Date
- 2025-05-19
- Publication Date
- 2026-05-29
AI Technical Summary
Existing digital phase-locked loops have long acquisition times, which leads to longer frequency transition times. Furthermore, existing methods suffer from high costs, large size, and low sensitivity when trying to shorten the acquisition time.
A phase-locked loop (PLL) acquisition device, composed of a temperature-compensated crystal oscillator, a frequency and phase detector, a loop filter, an adder, a voltage-controlled oscillator, a power divider, a delay line, a phase detector, and an operational amplifier, achieves initial locking through phase detection conversion, shortens the acquisition time, and optimizes the circuit structure.
It achieves fast voltage locking conversion, reduces cost and circuit complexity, simplifies circuit structure, shortens the phase-locked loop acquisition time, and keeps phase noise and other indicators unaffected, making it easy to expand and apply.
Smart Images
Figure CN224305760U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of phase-locked loop (PLL) capture technology, and more specifically, relates to a PLL capture device. Background Technology
[0002] With the development of wireless communication technology, much information needs to be transmitted using electromagnetic waves. Therefore, the performance of the frequency synthesizer, which serves as the local oscillator signal source, has become crucial, directly impacting the performance of communication, radar, navigation, and instrumentation equipment. Phase noise and frequency hopping time are key technical indicators. Especially in military electronic countermeasures systems, the synthesized frequency source is required to achieve frequency agility over a wide bandwidth. With the development of frequency synthesis technology, the requirement for shorter hopping times has become increasingly stringent. Different requirements for frequency hopping time determine the system architecture of the synthesized frequency source. Shorter hopping times typically require direct analog frequency synthesis technology, but products using this technology are costly and bulky, failing to meet user requirements. Digital phase-locked loop (PLL) technology offers advantages such as low cost, small size, and low power consumption. However, the longer acquisition time of PLL results in a longer final hopping time. Therefore, shortening the acquisition time of the PLL is particularly important. Various methods have been proposed to improve the acquisition performance of PLLs, such as tuning voltage methods, scanning methods, and changing loop parameters, but these methods still have some shortcomings. Utility Model Content
[0003] In view of this, the present invention provides a phase-locked loop capturing device to solve the above problems.
[0004] To solve the above technical problems, this utility model provides a phase-locked loop (PLL) capture device, comprising:
[0005] Temperature-compensated crystal oscillators, frequency and phase detectors, loop filters, adders, voltage-controlled oscillators, power dividers, phase detectors, operational amplifiers, amplifiers and frequency dividers;
[0006] The temperature-compensated crystal oscillator is connected to the frequency and phase detector. The frequency and phase detector is connected to the adder through a loop filter. The adder is connected to the voltage-controlled oscillator. The voltage-controlled oscillator is connected to the delay line through a power divider, and the other end is connected to the phase detector. The phase detector is connected to the adder through an operational amplifier.
[0007] As an alternative, the voltage-controlled oscillator is connected to the amplifier via a power divider, and then connected to the frequency and phase detector via a frequency divider.
[0008] As an alternative, after passing through a power divider, one path of the voltage-controlled oscillator (VCO) is connected to the frequency discriminator via a delay line and the other path is connected to the in-phase path via a delay line.
[0009] As an alternative, the error voltage of the frequency and phase detector is fed into an adder via an operational amplifier and then into a voltage-controlled oscillator.
[0010] The beneficial effects of this utility model are as follows:
[0011] (1) Since the initial locking voltage of this utility model adopts the phase detection conversion method, it has the advantages of fast conversion speed and high preset voltage accuracy. (2) This utility model shortens the phase-locked loop acquisition time without affecting phase noise and other indicators, and simplifies the circuit structure and spatial layout, making the application simpler and more convenient, and reducing costs. It is more flexible in circuit design and structural form, and easy to expand. Attached Figure Description
[0012] Figure 1 This is a schematic diagram illustrating the working principle of an existing digital frequency discriminator.
[0013] Figure 2 A schematic diagram of the phase-locked loop capturing device provided in an embodiment of this utility model. Detailed Implementation
[0014] To enable those skilled in the art to better understand the technical solution of this utility model, the present utility model will be further described in detail below with reference to specific embodiments.
[0015] Please see Figure 1 , Figure 1 The working principle of existing digital frequency discriminators is as follows: a signal with frequency f passing through a cable of length L will generate a phase shift of Ф, where Ф = 2πτf, and τ is the delay time of the cable of length L. When L is a fixed length, τ is a constant. When the frequency f is different, the phase shift Ф is also different. Thus, by measuring the phase shift Ф, the frequency f can be calculated.
[0016] Depend on Figure 1The signal f enters the power divider, splitting it into two paths. One path goes to a sinusoidal phase detector, which requires the highest possible phase detection sensitivity. Higher sensitivity leads to higher overall system sensitivity and frequency discrimination accuracy. In engineering, double-balanced mixers are commonly used as phase detectors for convenience. The other path goes through a phase-shifting cable, which is a low-loss, phase-stable cable. Because broadband double-balanced mixers generally have low phase detection sensitivity, an operational amplifier is added to amplify the phase detection voltage to improve frequency discrimination sensitivity. This amplifier should be selected for its good temperature stability, high speed, and low noise. The operational amplifier output is sent to an A / D converter. The A / D converter uses an appropriate number of bits to ensure that the converted value is consistent with the voltage-controlled sensitivity of the VCO and the D / A conversion, allowing direct calculation in the digital arithmetic unit to accurately preset the VCO's frequency hopping voltage. This device features a simple circuit design, stable performance, and low cost. Therefore, considering the shortcomings of existing phase-locked frequency synthesis technology and the need to improve the frequency hopping time of the phase-locked frequency synthesizer, this embodiment is implemented as follows:
[0017] Please see Figure 2 The objective of this embodiment is achieved through the following technical solution: a phase-locked loop capture device, mainly composed of a temperature-compensated crystal oscillator, a frequency and phase detector, a loop filter, an adder, a voltage-controlled oscillator, a frequency divider, an amplifier, a power divider, a delay line, a phase detector, and an operational amplifier.
[0018] The temperature-compensated crystal oscillator is connected to a frequency and phase detector. The frequency and phase detector is connected to an adder via a loop filter. The adder is connected to a voltage-controlled oscillator (VCO). The VCO is connected to a delay line via a power divider, and another path goes to the phase detector. The phase detector is then connected to the adder via an operational amplifier.
[0019] One signal is fed into the phase detector, and the other enters the phase detector via a phase-shifting cable. The frequency is calculated based on the phase shift of the cable. An operational amplifier is used to amplify the phase detector voltage appropriately, and the op-amp output is sent to an A / D converter. The A / D converter selects an appropriate number of bits according to the accuracy requirements to ensure that the A / D conversion value is consistent with the voltage-controlled sensitivity of the VCO and the D / A conversion. This allows for direct calculation in the digital arithmetic unit, achieving precise preset of the VCO's frequency hopping voltage. This ensures that the starting frequency error is preset within the fast capture band, thus significantly shortening the phase-locked loop (PLL) acquisition time.
[0020] This utility model discloses a phase-locked loop (PLL) capture device, mainly composed of a temperature-compensated crystal oscillator, a phase-frequency detector, a loop filter, an adder, a voltage-controlled oscillator, a power divider, a delay line, a phase detector, an operational amplifier, an amplifier, and a frequency divider. Compared with the prior art, this utility model has the following advantages and beneficial effects: (1) Since the initial locking voltage of this utility model adopts a phase-detection conversion method, it has the advantages of fast conversion speed and high preset voltage accuracy. (2) This utility model shortens the PLL capture time without affecting phase noise and other indicators, and simplifies the circuit structure and spatial layout, making the application simpler and more convenient, and reducing costs. It is more flexible in circuit design and structural form, and easy to expand.
[0021] The above are merely preferred embodiments of this utility model. It should be noted that the above preferred embodiments should not be considered as limitations on this utility model, and the scope of protection of this utility model should be determined by the scope defined in the claims. For those skilled in the art, several improvements and modifications can be made without departing from the spirit and scope of this utility model, and these improvements and modifications should also be considered within the scope of protection of this utility model.
Claims
1. A phase-locked loop (PLL) capturing device, characterized in that, include: Temperature-compensated crystal oscillators, frequency and phase detectors, loop filters, adders, voltage-controlled oscillators, power dividers, phase detectors, operational amplifiers, amplifiers and frequency dividers; The temperature-compensated crystal oscillator is connected to the frequency and phase detector. The frequency and phase detector is connected to the adder through a loop filter. The adder is connected to the voltage-controlled oscillator. The voltage-controlled oscillator is connected to the delay line through a power divider, and the other end is connected to the phase detector. The phase detector is connected to the adder through an operational amplifier.
2. The phase-locked loop capturing device according to claim 1, characterized in that, The voltage-controlled oscillator is connected to the amplifier via a power divider, and then connected to the frequency and phase detector via a frequency divider.
3. The phase-locked loop capturing device according to claim 1, characterized in that, The voltage-controlled oscillator, after passing through a power divider, enters the frequency discriminator via a delay line and another in-phase line.
4. The phase-locked loop capturing device according to claim 1, characterized in that, The error voltage of the frequency and phase detector is fed into the adder via an operational amplifier and then into the voltage-controlled oscillator.