Chip package structure
By designing bridging chips in the chip package structure and using a delay wiring layer to adjust the signal transmission time, the problem of asynchronous interconnect signals in the 2.5D package structure is solved, and the transmission efficiency is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- FOREHOPE SEMICONDUCTOR (NINGBO) CO LTD
- Filing Date
- 2025-05-29
- Publication Date
- 2026-05-29
AI Technical Summary
In 2.5D packaging structures, the transmission efficiency is low due to the asynchronous interconnection signals between adjacent chip modules.
By designing a bridge chip in the chip package structure and setting a delay wiring layer on the side away from the substrate, the signal transmission time of the second chip stack is adjusted, so that the first and second chip stacks can achieve synchronous transmission.
This achieves near-synchronization of interconnection signals between chip modules, improving transmission efficiency.
Smart Images
Figure CN224306329U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of chip packaging technology, and more specifically, to a chip packaging structure. Background Technology
[0002] The 2.5D packaging structure contains a large number of integrated chips. Typically, a large number of logic dies and HBM chips are integrated using a silicon interposer. Since communication or data transmission is required between adjacent chip modules, wiring is required in the interposer between chip modules to interconnect the logic chips of adjacent chip modules, thus increasing the number of integrated chips.
[0003] The inventors' research revealed that the density of wiring layers on the interposer also increases, which inevitably leads to asynchrony of interconnection signals between chips, resulting in low transmission efficiency. Utility Model Content
[0004] The purpose of this invention is to provide a chip packaging structure that makes the interconnection signals between chip modules more synchronized, thereby improving transmission efficiency.
[0005] The embodiments of this utility model are implemented as follows:
[0006] This utility model embodiment provides a chip packaging structure, including:
[0007] Substrate;
[0008] The first adapter plate is mounted on the substrate;
[0009] Multiple first chip stacks are spaced apart and mounted on the side of the first adapter plate away from the substrate.
[0010] The second adapter plate is attached to the substrate and is spaced apart from the first adapter plate.
[0011] Multiple bridge chips are spaced apart and mounted on the surface of the second adapter plate away from the substrate.
[0012] Multiple second chip stacks are mounted on the surface of the multiple bridge chips away from the substrate.
[0013] The number of bridge chips is the same as the number of the first chip stacks, the number of the second chip stacks is greater than the number of the first chip stacks, each bridge chip is connected to two second chip stacks, and a delay wiring layer is provided on the surface of each bridge chip away from the substrate. At least a portion of the second chip stacks are connected to the delay wiring layer and connected to the corresponding bridge chip through the delay wiring layer. The delay wiring layer is configured to adjust the signal transmission time of the second chip stacks so that the first chip stacks and the second chip stacks can achieve synchronous transmission.
[0014] In an optional embodiment, a plurality of first chip stacks are distributed at equal intervals on the first adapter board to form multiple columns of first chip stacks; a plurality of bridge chips are distributed at equal intervals on the second adapter board to form multiple columns of bridge chips, and a plurality of second chip stacks form multiple columns, wherein the second chip stack has one more column than the first chip stack.
[0015] In an optional implementation, the distance X1 between two adjacent first chip stacks is equal to the distance X2 between two adjacent bridge chips.
[0016] In an optional implementation, each first chip stack includes a plurality of aligned and stacked first memory chips, and the height H1 of each first memory chip is equal to the distance X1 between two adjacent first chip stacks.
[0017] Each of the second chip stacks includes a plurality of aligned and stacked second memory chips, and the height H2 of each second memory chip is equal to the distance X2 between two adjacent bridge chips.
[0018] In an optional embodiment, the plurality of first chip stacks include 3 columns of first chip stacks, the plurality of bridge chips include 3 columns of bridge chips, and the plurality of second chip stacks include 4 columns of second chip stacks. The 4 columns of second chip stacks are mounted on the 3 columns of bridge chips, wherein two columns of second chip stacks are correspondingly mounted on two columns of bridge chips, and the remaining two columns of second chip stacks are connected between two adjacent columns of bridge chips.
[0019] In an optional embodiment, a first adapter layer is provided on the side of the first adapter board away from the substrate, a plurality of first chip stacks are spaced apart on the first adapter layer, and a second adapter layer is provided on the side of the first adapter board close to the substrate, the second adapter layer is provided with first solder balls, and the first solder balls are connected to the substrate.
[0020] In an optional embodiment, the first adapter plate is provided with a first conductive post, and the two ends of the first conductive post are respectively connected to the first adapter circuit layer and the second adapter circuit layer.
[0021] In an optional embodiment, a third transition circuit layer is provided on the side of the second adapter board away from the substrate, and a plurality of the bridge chips are spaced apart on the third transition circuit layer. A fourth transition circuit layer is provided on the side of the second adapter board close to the substrate, and the fourth transition circuit layer is provided with second solder balls, which are connected to the substrate.
[0022] In an optional embodiment, a second conductive post is provided inside the second adapter plate, and the two ends of the second conductive post are respectively connected to the third adapter circuit layer and the fourth adapter circuit layer.
[0023] In an optional embodiment, a molding compound is further disposed on the substrate, the molding compound covering the first adapter plate, the second adapter plate, the plurality of first chip stacks, the plurality of second chip stacks and the plurality of bridge chips.
[0024] The beneficial effects of this utility model embodiment include:
[0025] The chip packaging structure provided in this embodiment of the invention includes a first adapter plate and a second adapter plate spaced apart on a substrate. Multiple first chip stacks are spaced apart on the first adapter plates, and multiple bridge chips are spaced apart on the second adapter plates. Multiple second chip stacks are mounted on the bridge chips, wherein the number of second chip stacks is greater than the number of first chip stacks. Each bridge chip is connected to at least two of the second chip stacks. A delay wiring layer is provided on the surface of each bridge chip away from the substrate. At least a portion of the second chip stacks are connected to the delay wiring layer and, through the delay wiring layer, to the corresponding bridge chips. This delay wiring layer can adjust the signal transmission time of the second chip stacks, enabling synchronous transmission between the first and second chip stacks. Compared to the prior art, this embodiment of the invention, through reasonable arrangement of chip modules and adjustment of signal transmission time using a delay wiring layer, can make the interconnection signals between chip modules more synchronized, thereby improving transmission efficiency. Attached Figure Description
[0026] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this utility model and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0027] Figure 1 A schematic diagram of the chip packaging structure provided in an embodiment of the present utility model from a first-view perspective;
[0028] Figure 2 for Figure 1 Schematic diagram of the stacking structure of the first chip stack in the middle;
[0029] Figure 3 for Figure 1 A schematic diagram of the stacking structure of the second chip stack in the middle;
[0030] Figure 4 A schematic diagram of the chip packaging structure provided in an embodiment of this utility model from a second perspective.
[0031] icon:
[0032] 100 - Chip package structure; 110 - Substrate; 111 - Molded package; 130 - First adapter board; 131 - First adapter circuit layer; 133 - Second adapter circuit layer; 135 - First solder ball; 137 - First conductive pillar; 150 - Second adapter board; 151 - Third adapter circuit layer; 153 - Fourth adapter circuit layer; 155 - Second solder ball; 157 - Second conductive pillar; 170 - First chip stack; 171 - First memory chip; 180 - Second chip stack; 181 - Second memory chip; 190 - Bridge chip; 191 - Delay wiring layer. Detailed Implementation
[0033] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. The components of the embodiments of this utility model described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0034] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.
[0035] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0036] In the description of this utility model, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this utility model is in use. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model. In addition, the terms "first," "second," and "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0037] Furthermore, terms such as "horizontal" and "vertical" do not imply that components must be absolutely horizontal or suspended, but rather that they can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.
[0038] In the description of this utility model, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.
[0039] See Figures 1 to 4 This utility model provides a chip packaging structure 100 that enables the interconnection signals between chip modules to be more synchronized, thereby improving transmission efficiency.
[0040] This utility model provides a chip packaging structure 100, including a substrate 110, a first adapter plate 130, a second adapter plate 150, a plurality of first chip stacks 170, a plurality of second chip stacks 180, and a plurality of bridge chips 190. The first adapter plate 130 is mounted on the substrate 110; the plurality of first chip stacks 170 are spaced apart and mounted on the surface of the first adapter plate 130 away from the substrate 110; the second adapter plate 150 is mounted on the substrate 110 and spaced apart from the first adapter plate 130; the plurality of bridge chips 190 are spaced apart and mounted on the surface of the second adapter plate 150 away from the substrate 110; the plurality of second chip stacks 180 are mounted on the surface of the plurality of bridge chips 190 away from the substrate. One side surface of 110; wherein the number of bridge chips 190 is the same as the number of first chip stacks 170, the number of second chip stacks 180 is greater than the number of first chip stacks 170, each bridge chip 190 is connected to two second chip stacks 180, and a delay wiring layer 191 is provided on the side surface of each bridge chip 190 away from the substrate 110, wherein at least a portion of the second chip stacks 180 are connected to the delay wiring layer 191 and connected to the corresponding bridge chip 190 through the delay wiring layer 191, and the delay wiring layer 191 is configured to adjust the signal transmission time of the second chip stacks 180 so that the first chip stacks 170 and the second chip stacks 180 achieve synchronous transmission.
[0041] Furthermore, the multiple first chip stacks 170, the multiple bridge chips 190, and the multiple second chip stacks 180 are all arranged in multiple columns. In this embodiment, the number of columns of the first chip stacks 170 and the bridge chips 190 can be n, while the number of columns of the second chip stacks 180 can be n+1. The second chip stacks 180 have one more column than the first chip stacks 170. A wiring layer is provided in the substrate 110, and the surface of the substrate 110 is divided into a first chip region and a second chip region. A first adapter board 130 is mounted in the first chip region, and a second adapter board 150 is mounted in the second chip region. The first adapter board 130 and the multiple first chip stacks 170 mounted on it can constitute a first chip module, and the second adapter board 150 and the multiple second chip stacks 180 mounted on it can constitute a second chip module. According to the conventional direct stacking method, the number of second chip stacks 180 is greater, so the interconnection signals between the second chip stacks 180 and the first chip stacks 170 may have a synchronization problem, thereby affecting the transmission efficiency. This embodiment of the invention connects multiple second chip stacks 180 by designing a bridge chip 190. Each bridge chip 190 has a delay wiring layer 191 on its surface away from the substrate 110. At least a portion of the second chip stacks 180 are connected to the delay wiring layer 191 and, through the delay wiring layer 191, to their corresponding bridge chips 190. The delay wiring layer 191 can adjust the signal transmission time of the second chip stacks 180, enabling the first chip stack 170 and the second chip stack 180 to transmit synchronously. By rationally arranging the chip modules and adjusting the signal transmission time through the delay wiring layer 191, the interconnection signals between the chip modules can be made more synchronized, thereby improving transmission efficiency.
[0042] It should be noted that the delay wiring layer 191 mentioned in this embodiment of the present invention, i.e., the delay circuit, utilizes the wiring layer design to form a wire-wound resistor and a TSV to form a capacitor. The delay circuit is electrically connected to the TSV capacitor, thereby forming a delay circuit, which controls the delay time. It mainly utilizes the charging and discharging characteristics of the resistor and capacitor to achieve the delay. When an input signal is applied, the capacitor begins to charge until a certain voltage threshold is reached, at which point the output signal changes. The delay time τ can be estimated using the formula τ = RC, where R is the resistance value and C is the capacitance value. For the principle of the delay circuit achieving the delay, please refer to the relevant descriptions in the prior art.
[0043] It is worth noting that a wiring structure is provided in the substrate 110, and solder balls can also be provided on the bottom side of the substrate 110 to realize external electrical connection and signal connection.
[0044] In some embodiments, multiple first chip stacks 170 are equally spaced on a first adapter board 130, forming multiple columns of first chip stacks 170; multiple bridge chips 190 are equally spaced on a second adapter board 150, forming multiple columns of bridge chips 190; and multiple second chip stacks 180 form multiple columns, with the second chip stacks 180 having one more column than the first chip stacks 170. Specifically, the equally spaced distribution of the multiple columns of first chip stacks 170 ensures consistent signal transmission between them, while the equally spaced distribution of the multiple columns of bridge chips 190 on the second adapter board 150 allows the n+1 columns of second chip stacks 180 processed by the delay wiring layer 191 to be integrated onto the n columns of bridge chips 190. Since the n columns of bridge chips 190 are also equally spaced, consistent signal transmission is also maintained between them.
[0045] In some embodiments, the distance X1 between two adjacent first chip stacks 170 is equal to the distance X2 between two adjacent bridge chips 190. Specifically, the equal distance between the first chip stacks 170 and the equal distance between the bridge chips 190 further ensures that the interconnection signals of the first chip stacks 170 and the second chip stacks 180 are more similar, thereby further improving transmission efficiency.
[0046] It should be noted that in some embodiments, the distance between the first adapter board 130 and the second adapter board 150 is also X1, which can further improve synchronization. Furthermore, the distance between two adjacent first chip stacks 170 is X1, meaning that both the horizontal and vertical spacing is X1; similarly, X2 also means that both the horizontal and vertical spacing is X2.
[0047] In some embodiments, each first chip stack 170 includes a plurality of aligned and stacked first memory chips 171, the height H1 of each first memory chip 171 being equal to the distance X1 between two adjacent first chip stacks 170; each second chip stack 180 includes a plurality of aligned and stacked second memory chips 181, the height H2 of each second memory chip 181 being equal to the distance X2 between two adjacent bridge chips 190. Specifically, the plurality of first memory chips 171 may be HBM chips, and the plurality of first memory chips 171 are aligned and stacked, and each first memory chip 171 can be interconnected using TSV technology. The plurality of second memory chips 181 may be different types of HBM chips, and similarly, the plurality of second memory chips 181 are aligned and stacked, and each second memory chip 181 can also be interconnected using TSV technology. For the specific construction of the first chip stack 170 and the second chip stack 180, reference can be made to existing HBM stacking technology. The HBM chip is a memory chip with TSV conductive pillars and back pads, which enables HBM chip stacking.
[0048] In some embodiments, the plurality of first chip stacks 170 include three columns of first chip stacks 170, and each column of first chip stacks 170 includes two first chip stacks 170. The plurality of bridge chips 190 include three columns of bridge chips 190, and each column of bridge chips 190 includes two bridge chips. The plurality of second chip stacks 180 include four columns of second chip stacks 180, and each column of second chip stacks 180 includes two bridge chips. The four columns of second chip stacks 180 are mounted on the three columns of bridge chips 190, wherein two columns of second chip stacks 180 are correspondingly mounted on two columns of bridge chips 190, and the remaining two columns of second chip stacks 180 are connected between two adjacent columns of bridge chips 190. Specifically, the four columns of second chip stacks 180 are spaced apart, and each bridge chip 190 is connected to two second chip stacks 180, so that two of the four columns of second chip stacks 180 can be connected across the bridge chips 190, while the remaining two columns of second chip stacks 180 can be mounted to the two bridge chips 190 at the two edges.
[0049] It should be noted that in this embodiment, three columns of the second chip stack 180 can be connected to the delay wiring layer 191, while the remaining column of the second chip stack 180 can be directly connected to the pads on the bridge chip 190. The three columns of the second chip stack 180 can be adjusted by using the delay wiring layer 191.
[0050] In some embodiments, a first adapter plate 130 is provided with a first adapter line layer 131 on the side away from the substrate 110, and a plurality of first chip stacks 170 are spaced apart on the first adapter line layer 131. A second adapter line layer 133 is provided on the side of the first adapter plate 130 close to the substrate 110, and the second adapter line layer 133 is provided with first solder balls 135, which are connected to the substrate 110. Specifically, the first adapter plate 130 is a TSV adapter plate material, such as silicon, and the first adapter line layer 131 and the second adapter line layer 133 are formed on both sides of the first adapter plate 130, which can improve signal integration.
[0051] In some embodiments, a first conductive post 137 is provided in the first adapter plate 130, and the two ends of the first conductive post 137 are respectively connected to the first adapter circuit layer 131 and the second adapter circuit layer 133. Specifically, the conductive post has a TSV structure, and the electrical connection between the two circuit layers is realized through TSV technology.
[0052] In some embodiments, a third transition circuit layer 151 is disposed on the side of the second adapter plate 150 away from the substrate 110, and a plurality of bridge chips 190 are spaced apart on the third transition circuit layer 151. A fourth transition circuit layer 153 is disposed on the side of the second adapter plate 150 close to the substrate 110, and a second solder ball 155 is disposed on the fourth transition circuit layer 153 and connected to the substrate 110. Further, a second conductive post 157 is disposed within the second adapter plate 150, and the two ends of the second conductive post 157 are respectively connected to the third transition circuit layer 151 and the fourth transition circuit layer 153.
[0053] In some embodiments, a molding compound 111 is further disposed on the substrate 110, the molding compound 111 covering the first adapter plate 130, the second adapter plate 150, a plurality of first chip stacks 170, a plurality of second chip stacks 180 and a plurality of bridge chips 190.
[0054] In summary, the chip packaging structure 100 provided in this embodiment of the present invention has a first adapter plate 130 and a second adapter plate 150 mounted on a substrate 110 at intervals. Multiple first chip stacks 170 are mounted at intervals on the first adapter plate 130, and multiple bridge chips 190 are mounted at intervals on the second adapter plate 150. Multiple second chip stacks 180 are mounted on the multiple bridge chips 190, wherein the number of second chip stacks 180 is greater than the number of first chip stacks 170. Each bridge chip 190 is connected to at least two of the second chip stacks 180. A delay wiring layer 191 is provided on the surface of each bridge chip 190 away from the substrate 110. At least a portion of the second chip stacks 180 are connected to the delay wiring layer 191 and connected to the corresponding bridge chips 190 through the delay wiring layer 191. The delay wiring layer 191 can adjust the signal transmission time of the second chip stacks 180, enabling the first chip stacks 170 and the second chip stacks 180 to transmit synchronously. Compared with the prior art, the chip packaging structure 100 provided in this embodiment of the present invention can make the interconnection signals between chip modules more synchronized, thereby improving transmission efficiency.
[0055] The above description is merely a preferred embodiment of this utility model and is not intended to limit the utility model. Various modifications and variations can be made to this utility model by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.
Claims
1. A chip packaging structure, characterized in that, include: Substrate; The first adapter plate is mounted on the substrate; Multiple first chip stacks are spaced apart and mounted on the surface of the first adapter plate away from the substrate. The second adapter plate is attached to the substrate and is spaced apart from the first adapter plate. Multiple bridge chips are spaced apart and mounted on the surface of the second adapter plate away from the substrate. Multiple second chip stacks are mounted on the surface of the multiple bridge chips away from the substrate. The number of bridge chips is the same as the number of the first chip stacks, and the number of the second chip stacks is greater than the number of the first chip stacks. Each bridge chip is connected to at least two of the second chip stacks, and a delay wiring layer is provided on the surface of each bridge chip away from the substrate. At least a portion of the second chip stacks are connected to the delay wiring layer and connected to the corresponding bridge chip through the delay wiring layer. The delay wiring layer is configured to adjust the signal transmission time of the second chip stacks so that the first chip stack and the second chip stack can achieve synchronous transmission.
2. The chip packaging structure according to claim 1, characterized in that, Multiple first chip stacks are distributed at equal intervals on the first adapter board, forming multiple columns of first chip stacks; multiple bridge chips are distributed at equal intervals on the second adapter board, forming multiple columns of bridge chips; multiple second chip stacks form multiple columns, and each second chip stack has one more column than the first chip stack.
3. The chip packaging structure according to claim 2, characterized in that, The distance X1 between two adjacent first chip stacks is equal to the distance X2 between two adjacent bridge chips.
4. The chip packaging structure according to claim 2 or 3, characterized in that, Each of the first chip stacks includes a plurality of aligned stacked first memory chips, and the height H1 of each first memory chip is equal to the distance X1 between two adjacent first chip stacks. Each of the second chip stacks includes a plurality of aligned and stacked second memory chips, and the height H2 of each second memory chip is equal to the distance X2 between two adjacent bridge chips.
5. The chip packaging structure according to claim 2, characterized in that, The plurality of first chip stacks include 3 columns of first chip stacks, the plurality of bridge chips include 3 columns of bridge chips, and the plurality of second chip stacks include 4 columns of second chip stacks. The 4 columns of second chip stacks are mounted on the 3 columns of bridge chips, wherein two columns of second chip stacks are mounted on two columns of bridge chips respectively, and the remaining two columns of second chip stacks are connected between two adjacent columns of bridge chips.
6. The chip packaging structure according to claim 1, characterized in that, A first adapter board has a first adapter line layer on the side away from the substrate, and a plurality of first chip stacks are spaced apart on the first adapter line layer. A second adapter line layer is provided on the side of the first adapter board closer to the substrate, and the second adapter line layer has first solder balls connected to the substrate.
7. The chip packaging structure according to claim 6, characterized in that, The first adapter plate is provided with a first conductive post, and the two ends of the first conductive post are respectively connected to the first adapter circuit layer and the second adapter circuit layer.
8. The chip packaging structure according to claim 1, characterized in that, The second adapter board has a third adapter circuit layer on the side away from the substrate, and a plurality of bridge chips are spaced apart on the third adapter circuit layer. The second adapter board has a fourth adapter circuit layer on the side close to the substrate, and the fourth adapter circuit layer has a second solder ball connected to the substrate.
9. The chip packaging structure according to claim 8, characterized in that, The second adapter plate is provided with a second conductive post, and the two ends of the second conductive post are respectively connected to the third adapter circuit layer and the fourth adapter circuit layer.
10. The chip packaging structure according to claim 1, characterized in that, A molding compound is also disposed on the substrate, the molding compound covering the first adapter plate, the second adapter plate, a plurality of first chip stacks, a plurality of second chip stacks and a plurality of bridge chips.