Reset circuit and image forming apparatus

Abstract

The utility model discloses a reset circuit and image forming device, overcome the defect that communication cannot be recovered after communication failure in high speed transmission in the prior art. The reset circuit includes main control chip and memory, and the reset pin of main control chip is connected the reset pin of memory through reset line, when main control chip and memory communication anomaly, main control chip passes through reset line and outputs reset signal to memory, to make main control chip with memory execute reset operation and communicate normally, wherein, reset signal is the first level signal conversion for the second time second level signal of first time, to make main control chip and memory can recover normal communication after communication anomaly through hardware reset mode.

Description

Technical Field

[0001] This utility model relates to a reset circuit and an image forming apparatus. Background Technology

[0002] In current production and daily life, when the main control chip (ARM) and memory (eMMC) in printing equipment transmit data at high speed, they are easily affected by the following factors, leading to communication failure: (1) Electromagnetic interference: Electronic devices, power lines, and wireless signals can all generate electromagnetic interference, leading to communication failure; (2) Signal integrity issues: Signal reflection, crosstalk, attenuation, and other signal problems on the eMMC communication line may cause communication errors; (3) Power supply noise: Fluctuations in power supply voltage affect the normal operation of the eMMC device, leading to communication failure. In the event of communication failure between the main control chip and the memory, the ARM will wait for a certain period of time and then resend the command to the eMMC to ensure that the eMMC can execute the instruction normally. This means that when a communication fails, the main control chip and the memory can only repeatedly retry the communication based on the above results, and cannot restore the communication, reducing the success rate and efficiency of communication. Utility Model Content

[0003] The technical problem to be solved by this utility model is to overcome the defect in the prior art that communication cannot be restored after a communication failure during high-speed transmission between the main control chip and the memory.

[0004] This utility model discloses a reset circuit, including a main control chip and a memory. The reset pin of the main control chip is connected to the reset pin of the memory through a reset line. When the communication between the main control chip and the memory is abnormal, the main control chip outputs a reset signal to the memory through the reset line, so that the communication between the main control chip and the memory is normal after the main control chip performs a reset operation. The reset signal is a first level signal that is sustained for a first time and then converted to a second level signal that is sustained for a second time.

[0005] Preferably, the first level signal is a low level signal, and the second level signal is a high level signal.

[0006] Preferably, the first time is longer than the second time.

[0007] Preferably, it further includes a first resistor, used to control the reset signal to remain at a third level signal when the reset pin of the main control chip is in an idle state, so that the main control chip and the memory do not perform a reset operation.

[0008] Preferably, the third level signal is a high level signal.

[0009] Preferably, one end of the first resistor is connected to the power supply, and the other end of the first resistor is connected to the reset line.

[0010] Preferably, the main control chip's clock pin is connected to the memory's clock pin via a clock line, and the main control chip continuously outputs a clock signal to the memory during the first time period.

[0011] Preferably, the system further includes a main control chip whose instruction pin is connected to the memory's instruction pin via an instruction line. The main control chip sends operation instructions to the memory via the instruction line, and the memory feeds back the result or status information of the command execution to the main control chip via the instruction line.

[0012] Preferably, it also includes a first capacitor, one end of which is connected to the main control chip and the power supply, and the other end is grounded.

[0013] This utility model also discloses an image forming apparatus, including a control unit and a reset circuit as described above. The control unit is used to control the main control chip to output a reset signal to the memory when it detects an abnormal communication between the main control chip and the memory, so that the main control chip and the memory can resume normal communication after performing a reset operation. The reset signal is a first level signal that is sustained for a first time and then converted into a second level signal that is sustained for a second time.

[0014] Compared with the prior art, the reset circuit and image forming device of this utility model can quickly restore communication through hardware reset when the main control chip and memory communication is abnormal. Users do not need to repeatedly retry the operation to restore communication, effectively preventing long-term communication failure. Attached Figure Description

[0015] Figure 1 This is a structural block diagram of the main control chip and memory in this utility model;

[0016] Figure 2 This is a schematic diagram of a reset circuit according to this utility model;

[0017] Figure 3 This is a schematic diagram of the communication between the printing device and the USB peripheral in this utility model;

[0018] Figure 4 This is another communication diagram between the printing device and the USB peripheral in this utility model. Detailed Implementation

[0019] The following detailed description of the embodiments of this utility model, in conjunction with the accompanying drawings, will provide a thorough understanding of how this utility model uses technical means to solve technical problems and achieve corresponding technical effects, enabling its implementation. The embodiments of this utility model and the various features within them can be combined with each other without conflict, and all resulting technical solutions are within the protection scope of this utility model.

[0020] First Embodiment

[0021] Figure 1 This is a structural block diagram of the main control chip and memory in this utility model. Figure 1 The main control chip can be an ARM main control chip in the image forming apparatus, which includes a controller. The memory can be an eMMC in the image forming apparatus, which is a non-volatile memory typically used to store data, application programs, and system programs. This memory includes an interface, a flash memory controller, and flash memory. The interface is used to connect to the controller of the main control chip, thereby enabling communication with the main control chip. The flash memory controller is used for internal operation and management of the flash memory.

[0022] The aforementioned main control chip can be any microcontroller or microprocessor, and the aforementioned memory can be any storage medium that communicates with the aforementioned main control chip. This embodiment does not limit the specific form of the main control chip and the memory.

[0023] Figure 2 This is a schematic diagram of a reset circuit according to this utility model. Figure 2 In this circuit, the reset circuit includes a main control chip and a memory. The reset pin RES0 of the main control chip is connected to the reset pin RES1 of the memory via a reset line. When the communication between the main control chip and the memory is abnormal, the main control chip outputs a reset signal to the memory via the reset line, so that the communication between the main control chip and the memory is normal after the reset operation is performed. The reset signal is a first level signal that is sustained for a first time and then converted to a second level signal that is sustained for a second time.

[0024] In an optional implementation of this embodiment, the first level signal and the second level signal are opposite level signals, preferably. The first level signal is a low level signal, and the second level signal is a high level signal. In some embodiments, the first level signal may also be a high level signal to indicate the execution of a hardware reset operation, while the second level signal is a low level signal.

[0025] As an optional implementation of this embodiment, the first time is longer than the second time. Preferably, the first time is much longer than the second time. For example, the first time can be any value between 100us and 500us, and the second time can be any value between 2us and 10us.

[0026] When the main control chip determines that an abnormality has occurred during the interaction between the main control chip and the memory, such as when the memory is acquiring and / or outputting data, it may be affected by electromagnetic interference, voltage fluctuations, signal anomalies, etc., thus determining that data reading from the memory has failed. Based on this, the main control chip outputs a reset signal to the memory via a reset line, thereby resetting and restarting the memory, and then reading data from the reset and restarted memory again. This reset signal is the signal that triggers the reset and restart behavior.

[0027] It is understandable that when the main control chip determines that the transmitted data is abnormal, it can perform the verification at the hardware level, such as by using the set interrupt and exception mechanism or hardware detection circuit, or it can perform the verification at the software level, such as by using the built-in data verification algorithm, outlier detection or data monitoring software, or it can combine the two levels. This embodiment does not limit the specific verification method.

[0028] In an optional implementation of this embodiment, the reset circuit further includes a first resistor R, one end of which is connected to the power supply VCC, and the other end is connected to the reset line connecting the main control chip and the memory. This first resistor R is a pull-up resistor, used to control the reset signal to maintain a third-level signal when the reset pin RES0 of the main control chip is in an idle state, so that the main control chip and the memory do not perform a reset operation. This third-level signal is used to prevent accidental triggering of the reset operation when the reset pin RES0 of the main control chip is in an idle state, reducing the probability of reset operation errors. In this embodiment, the third-level signal is a high-level signal.

[0029] For example, the power supply provides the corresponding power supply voltage to the main control chip and the memory. This can be achieved by pre-setting corresponding power supply pins on the main control chip and the memory, respectively, and connecting the power supply terminals to the corresponding power supply pins of the main control chip and the memory using power wires or cables. Based on this, the main control chip and the memory can then operate based on the provided power supply voltage. For example, the main control chip can set a certain pin to a high / low level under the supplied power supply voltage.

[0030] As an optional implementation of this embodiment, the reset circuit further includes the clock pin CLK0 of the main control chip being connected to the clock pin CLK1 of the memory via a clock line, and the main control chip continuously outputting a clock signal to the memory in the first time.

[0031] Understandably, in order to ensure that the main control chip and memory can operate in the predetermined timing sequence during reset, the main control chip also needs to continuously send clock signals to the memory through the clock signal line during the process of maintaining the corresponding level.

[0032] As an optional implementation of this embodiment, the reset circuit further includes the instruction pin CMD0 of the main control chip connected to the instruction pin CMD1 of the memory via an instruction line. The main control chip sends operation instructions to the memory via the instruction line, and the memory feeds back the result or status information of the command execution to the main control chip via the instruction line.

[0033] As an optional implementation of this embodiment, the reset circuit further includes the main control chip's data transmission pin DA0 being connected to the memory's data transmission pin DA1 via a data line. The main control chip sends a request to the memory to obtain data via the data line, and the memory feeds back specific data to the main control chip via the data line.

[0034] It is understandable that when using related signal lines to connect two identical pins, a direct connection can be used to connect the two pins together directly through the related signal lines, which is convenient for operation. Alternatively, a soldering connection can be used to solder the related signal lines to the two pins simultaneously, which improves the stability of the connection. Or, a plug-in connection can be used to connect the related signal lines to the two pins simultaneously using a plug and socket, which improves the flexibility of the connection. This embodiment does not limit the specific connection method used.

[0035] As an optional implementation of this embodiment, the reset circuit further includes a first capacitor C, one end of which is connected to the main control chip VDD, and the other end is grounded.

[0036] Taking low-level reset as an example, the working principle of the reset circuit provided in this embodiment is as follows:

[0037] When communication between the ARM and eMMC fails, following the hardware reset procedure of the eMMC 4.51 protocol, the main control chip's ARM outputs a low level to the eMMC's reset pin RES1 for at least a short period, during which the ARM continuously sends a clock signal to the eMMC. At this point, the reset signal is valid. Then, the main control chip controls the eMMC's reset pin RES1 to be high and maintains it for at least a second period, during which the ARM continuously sends a clock signal to the eMMC. This completes the hardware reset procedure, re-initializing the eMMC. The reset operation between the main control chip and the memory is successful, and normal communication can resume. At this point, the main control chip outputs a high level to the eMMC's reset pin RES1 to prevent accidental reset operations.

[0038] Second Embodiment

[0039] This utility model provides an image forming apparatus, including a control unit and a reset circuit as described in the first embodiment or any of its optional embodiments.

[0040] The control unit includes a central processing unit (CPU), etc., which reads the program stored in the memory to execute processing, outputs instruction signals to various functional units, transmits data, etc., and controls the overall image forming apparatus. When an abnormal communication between the main control chip and the memory is detected, the main control chip is controlled to output a reset signal to the memory, so that the main control chip and the memory can resume normal communication after performing a reset operation. The reset signal is a first level signal that is sustained for a first time and then converted to a second level signal that is sustained for a second time.

[0041] The image forming apparatus described above has a main body. A control unit and a reset circuit are disposed within the main body. An input operation unit is also located on the upper part of the image forming apparatus. This input operation unit includes a power button for allowing the user to turn the image forming apparatus on / off, a start button for allowing the user to input instructions such as printing, a cancel button for allowing the user to input instructions such as canceling printing, numeric keys for inputting the number of copies to be printed, and a display unit including an LCD screen with touchscreen functionality for displaying various printing instructions and inputting various settings.

[0042] Third Embodiment

[0043] Figure 3 This is a schematic diagram of the communication between the printing device and the USB peripheral in this utility model. Figure 3 In this embodiment, the printing device is considered the host, and the removable USB peripheral is considered a storage device connected to the printing device via a USB interface. When communication between the printing device and the USB peripheral fails—that is, when the client software corresponding to the printing device receives a transmission error or endpoint stop error information returned by the USB system software—it requests a USB Pipe reset from the USB system software. The USB system software then sends a clear feature command to the USB peripheral through the control channel based on this request. Upon responding to the clear feature command, the USB peripheral clears the error of the specific endpoint indicated by the command and retains the incomplete data in the printing device's buffer. At this time, the driver software in the printing device clears the controller hardware error flag of the specific endpoint corresponding to the pipe (i.e., clears the host controller halt flag), resetting the controller error state within the printing device, thereby restoring normal communication between the printing device and the USB peripheral. It is understood that the specific endpoint mentioned above can be any endpoint from endpoint 0 to endpoint X included in the functional interface shown in the figure; this embodiment does not limit this.

[0044] Figure 4 This is another communication diagram between the printing device and the USB peripheral in this utility model. Figure 4In this process, after the client software successfully receives data sent by the USB peripheral, it requests the USB system software to initiate a USB control transmission `setinterface` command. The USB system software then sends the `setinterface` command to the USB peripheral through the control channel. After responding to the `setinterface` command, the USB peripheral resets the specific endpoint indicated by the command. At this time, the specific endpoint in the printing device is also reset, and any untransmitted data is retained in the printing device's buffer. Afterward, the functional interface resumes normal communication. It is understood that the aforementioned specific endpoint can be any endpoint from endpoint 0 to endpoint X included in the functional interface shown in the diagram; this embodiment does not limit this.

[0045] Although the embodiments disclosed in this utility model are as described above, the content described is merely an implementation method adopted to facilitate understanding of the technical solution of this utility model, and is not intended to limit this utility model. Any person skilled in the art to which this utility model pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this utility model, but the patent protection scope of this utility model shall still be determined by the scope defined in the appended claims.

Claims

1. A reset circuit, characterized in that, The system includes a main control chip and a memory. The reset pin of the main control chip is connected to the reset pin of the memory via a reset line. When the communication between the main control chip and the memory is abnormal, the main control chip outputs a reset signal to the memory via the reset line, so that the communication between the main control chip and the memory is normal after the main control chip performs a reset operation. The reset signal is a first level signal that is sustained for a first time and then converted to a second level signal that is sustained for a second time.

2. The reset circuit according to claim 1, characterized in that, The first level signal is a low level signal, and the second level signal is a high level signal.

3. The reset circuit according to claim 1, characterized in that, The first time is greater than the second time.

4. The reset circuit according to any one of claims 1 to 3, characterized in that, It also includes a first resistor, used to control the reset signal to remain at the third level signal when the reset pin of the main control chip is in an idle state, so that the main control chip and the memory do not perform a reset operation.

5. The reset circuit according to claim 4, characterized in that, The third level signal is a high level signal.

6. The reset circuit according to claim 4, characterized in that, One end of the first resistor is connected to the power supply, and the other end of the first resistor is connected to the reset line.

7. The reset circuit according to claim 1, characterized in that, It also includes the clock pin of the main control chip being connected to the clock pin of the memory via a clock line, and the main control chip continuously outputting a clock signal to the memory during the first time period.

8. The reset circuit according to claim 1, characterized in that, It also includes the instruction pin of the main control chip being connected to the instruction pin of the memory via an instruction line, the main control chip sending operation instructions to the memory via the instruction line, and the memory feeding back the result or status information of the command execution to the main control chip via the instruction line.

9. The reset circuit according to claim 1, characterized in that, It also includes a first capacitor, one end of which is connected to the main control chip and the power supply, and the other end is grounded.

10. An image forming apparatus, characterized in that, The system includes a control unit and a reset circuit according to any one of claims 1 to 9. The control unit is used to control the main control chip to output a reset signal to the memory when an abnormal communication is detected between the main control chip and the memory, so that the main control chip and the memory can resume normal communication after performing a reset operation; wherein the reset signal is a first level signal that is sustained for a first time and then converted to a second level signal that is sustained for a second time.

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