Display assembly and electronic device

Abstract

The application discloses a display assembly and an electronic device, and belongs to the technical field of electronic devices. The display assembly comprises a display panel, the display panel comprising a display area, a first non-display area and a second non-display area; the display area comprises pixel units; the first non-display area and the second non-display area are located on two sides of the display area; a display driving module is arranged in the first non-display area; a demultiplexing circuit is electrically connected to the display driving module at an input end and electrically connected to the pixel units at an output end; the demultiplexing circuit comprises a plurality of switch elements, part of the switch elements are arranged in the first non-display area, and the other part of the switch elements are arranged in the second non-display area.

Description

Technical Field

[0001] This application belongs to the field of electronic equipment technology, specifically relating to a display component and an electronic device. Background Technology

[0002] In related technologies, demultiplexing (Demux) technology can effectively reduce the number of channels in the integrated circuit (IC) of a display device, thereby reducing the cost of the driver IC.

[0003] However, the Demux module will occupy additional circuit area. Taking a common mobile phone display screen as an example, the Demux module is usually placed at the bottom bezel of the mobile phone screen, which results in a large "black border" area at the bottom bezel of the display screen. Utility Model Content

[0004] This application aims to provide a display component and electronic device that can solve the problem of large "black border" area on the bottom bezel of the display screen in the related art.

[0005] In a first aspect, embodiments of this application provide a display component, which includes:

[0006] The display panel includes a display area, a first non-display area, and a second non-display area; wherein the display area includes pixel units, and the first non-display area and the second non-display area are located on both sides of the display area;

[0007] The display driver module is located in the first non-display area;

[0008] The demultiplexing circuit has its input terminal electrically connected to the display driver module and its output terminal electrically connected to the pixel unit. The demultiplexing circuit includes multiple switching elements, some of which are located in the first non-display area and others are located in the second non-display area.

[0009] Secondly, embodiments of this application provide an electronic device including a display component as provided in the first aspect.

[0010] In this embodiment, the switches in the demultiplexing circuit are respectively placed in two different non-display areas at both ends of the display panel. By dispersing the switches, the area occupied by the demultiplexing circuit is no longer concentrated on one side of the display screen, thereby effectively reducing the "black border" area of ​​the single-sided bezel of the display screen.

[0011] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0012] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0013] Figure 1 The present application shows schematic diagrams of the structure of display components according to some embodiments;

[0014] Figure 2 A schematic diagram of the driving timing of the display components according to some embodiments of this application is shown.

[0015] Figure label:

[0016] 10 Display component, 12 Display panel, 122 Display area, 124 First non-display area, 126 Second non-display area, 14 Display driver module, 16 Demultiplexing circuit;

[0017] 200 pixel units, 202 sub-pixels, 2022 first sub-pixel column, 2024 second sub-pixel column, 2026 third sub-pixel column, 2028 fourth sub-pixel column;

[0018] D1 is the first data line, D2 is the second data line, D3 is the third data line, D4 ​​is the fourth data line, D5 is the fifth data line, D6 is the sixth data line, D7 is the seventh data line, and D8 is the eighth data line.

[0019] Demux1 is the first solution multiplexing line, Demux2 is the second solution multiplexing line, Demux3 is the third solution multiplexing line, and Demux4 is the fourth solution multiplexing line;

[0020] T1 is the first switch, T2 is the second switch, T3 is the third switch, T4 is the fourth switch, T5 is the fifth switch, T6 is the sixth switch, T7 is the seventh switch, and T8 is the eighth switch.

[0021] Scan gate scan lines;

[0022] S1 is the first source line, and S2 is the second source line;

[0023] R is the red subpixel, G is the green subpixel, and B is the blue subpixel. Detailed Implementation

[0024] The embodiments of this application will now be described in detail. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0025] The terms "first" and "second" in the specification and claims of this application may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise stated, "multiple" means two or more. Furthermore, "and / or" in the specification and claims indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0026] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0027] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0028] The following is combined Figures 1 to 2 This application describes a display component 10 and an electronic device according to embodiments thereof.

[0029] In some embodiments of this application, a display component 10 is provided. Figure 1 The following are schematic diagrams illustrating the structure of the display component 10 according to some embodiments of this application, such as... Figure 1 As shown, display component 10 includes:

[0030] Display panel 12 includes a display area 122, a first non-display area 124, and a second non-display area 126; wherein, the display area 122 includes pixel units 200, and the first non-display area 124 and the second non-display area 126 are respectively located on both sides of the display area 122.

[0031] Display driver module 14 is located in the first non-display area 124;

[0032] The demultiplexing circuit 16 has its input terminal electrically connected to the display driver module 14 and its output terminal electrically connected to the pixel unit 200. The demultiplexing circuit 16 includes multiple switching elements, some of which are located in the first non-display area 124 and others are located in the second non-display area 126.

[0033] In this embodiment, the display component 10 is, exemplarily, a liquid crystal display (LCD) component. The display component 10 includes a display panel 12, which includes a display area 122, a first non-display area 124, and a second non-display area 126. The display area 122 is the area used to display content when the display component 10 is in operation. The first non-display area 124 and the second non-display area 126 are located on opposite sides of the display area 122. Figure 1 As shown, taking the display component 10 as a mobile phone display screen as an example, the first non-display area 124 is the lower border area of ​​the mobile phone display screen, and the second non-display area 126 is the upper border area of ​​the mobile phone display screen.

[0034] The display assembly 10 also includes a display driver module 14, which is disposed within the first non-display area 124. The display driver module 14 is capable of generating and outputting driving signals for driving the pixel units 200 within the display area 122 to emit light. The display assembly 10 also includes a demultiplexing circuit 16. The demultiplexing circuit 16 can separate composite signals and restore them to their original independent signals. The 1:4 Mux (Multiplexer) demultiplexing circuit 16 can reduce the output channels of the display driver module 14 to 1 / 4 of the original, thereby effectively reducing the production cost of the driver module. However, at the same time, since the demultiplexing circuit 16 adds additional circuit components, it also occupies space at the bottom bezel of the display screen, resulting in a large "black border" area at the bottom of the phone, commonly known as a "big chin".

[0035] To address the aforementioned issues, this application embodiment redesigns the layout of the demultiplexing circuit 16 in the display component 10. By placing the switching components in the demultiplexing circuit 16 in two different non-display areas, the area occupied by the demultiplexing circuit 16 on the single-sided bezel is reduced, thereby shrinking the "black border" area of ​​the single-sided bezel.

[0036] Exemplarily, the demultiplexing circuit 16 includes multiple switching devices, which are, exemplarily, thin-film transistor (TFT) switching devices. Exemplarily, in a TFT-LCD (TFT-Liquid Crystal Display), the TFT switching devices can directly act as pixel-level demultiplexers. The serial signal output by the display driving module 14 can be demultiplexed by the TFT array into an independent control voltage for each pixel unit 200.

[0037] By distributing multiple switches in the demultiplexing circuit 16 within the first non-display area 124 and the second non-display area 126, respectively. For example, taking a mobile phone display screen as an example, assuming the first non-display area 124 is the lower bezel area of ​​the mobile phone display screen and the second non-display area 126 is the upper bezel area of ​​the mobile phone display screen, since at least some of the switches are located in the second non-display area 126, i.e., the upper bezel area of ​​the mobile phone display screen, all switches in the demultiplexing circuit 16 do not need to be located together with the display driver module 14 in the lower bezel area of ​​the mobile phone display screen.

[0038] This application disperses the switching components in the demultiplexing circuit 16 into two different non-display areas at both ends of the display panel 12, thereby reducing the area of ​​the "black border" on one side of the display screen by dispersing the switching components.

[0039] In some embodiments of this application, there are multiple pixel units 200 arranged in an array. Each pixel unit 200 includes four sub-pixels 202, and each sub-pixel 202 is electrically connected to a gate scan line Scan. Among the multiple pixel units 200 arranged in the array, there are multiple columns of pixel units 200. Each column of pixel units 200 includes four columns of sub-pixels 202, and each column of sub-pixels 202 is electrically connected to the demultiplexing circuit 16 through two data lines.

[0040] In this embodiment, the display area 122 of the display panel 12 includes multiple arrayed pixel units 200, each pixel unit 200 comprising four sub-pixels 202. For example, a pixel unit 200 includes one red sub-pixel R, one blue sub-pixel B, and two green sub-pixels G. For example, the four sub-pixels 202 are arranged in an array according to the sequence R, G, B, G… Each sub-pixel 202 is electrically connected to a gate scan line Scan. When the display component 10 refreshes the display content, the N gate scan lines Scan sequentially switch from low to high level. When a gate scan line Scan switches to high level, the sub-pixel 202 electrically connected to the high-level gate scan line Scan is charged, while the sub-pixels 202 electrically connected to other low-level gate scan lines Scan do not charge. This method achieves row-by-row charging of the sub-pixels 202.

[0041] Multiple pixel units 200 within the display area 122 are arranged in an X-row, Y-column array, with the Y-column pixel units 200 forming 4Y-column sub-pixels 202. That is, each column of pixel units 200 includes 4 columns of sub-pixels 202. Each column of sub-pixels 202 is electrically connected to the demultiplexing circuit 16 via two data lines, thereby enabling the demultiplexing circuit 16 to transmit the display drive signal to each column of sub-pixels 202, achieving independent voltage control for each column of sub-pixels 202.

[0042] In some embodiments of this application, the four sub-pixel columns 202 include a first sub-pixel column 2022, a second sub-pixel column 2024, a third sub-pixel column 2026, and a fourth sub-pixel column 2028;

[0043] The data lines include the first data line D1, the second data line D2, the third data line D3, the fourth data line D4, the fifth data line D5, the sixth data line D6, the seventh data line D7, and the eighth data line D8;

[0044] Specifically, the first sub-pixel column 2022 is electrically connected to the first data line D1 and the fifth data line D5, the second sub-pixel column 2024 is electrically connected to the second data line D2 and the sixth data line D6, the third sub-pixel column 2026 is electrically connected to the third data line D3 and the seventh data line D7, and the fourth sub-pixel column 2028 is electrically connected to the fourth data line D4 and the eighth data line D8.

[0045] In this embodiment, the structure of the display component 10 is explained using a column of pixel units 200 as an example. A column of pixel units 200 includes four columns of sub-pixels 202, which are respectively referred to as the first sub-pixel column 2022, the second sub-pixel column 2024, the third sub-pixel column 2026, and the fourth sub-pixel column 2028.

[0046] Each column of sub-pixels 202 is electrically connected to two data lines. Correspondingly, the four columns of sub-pixels 202 are each electrically connected to two of the eight data lines. These eight data lines are designated as the first data line D1, the second data line D2, the third data line D3, the fourth data line D4, the fifth data line D5, the sixth data line D6, the seventh data line D7, and the eighth data line D8.

[0047] Among them, such as Figure 1 As shown, the first data line D1 and the fifth data line D5 are electrically connected to the first sub-pixel column 2022. The second data line D2 and the sixth data line D6 are electrically connected to the second sub-pixel column 2024. The third data line D3 and the seventh data line D7 are electrically connected to the third sub-pixel column 2026. The fourth data line D4 and the eighth data line D8 are electrically connected to the fourth sub-pixel 202.

[0048] Each data line receives a drive signal from the display driver module 14 via a switch in the multiplexing circuit, enabling individual voltage drive control for each sub-pixel 202.

[0049] In some embodiments of this application, the demultiplexing circuit 16 includes:

[0050] The first demultiplexing line Demux1 is electrically connected to the gate of the first switching element T1 and the gate of the third switching element T3.

[0051] The second demultiplexing line Demux2 is electrically connected to the gate of the second switching element T2 and the gate of the fourth switching element T4.

[0052] The third demultiplexing line Demux3 is electrically connected to the gate of the fifth switch T5 and the gate of the seventh switch T7.

[0053] The fourth demultiplexing line Demux4 is electrically connected to the gate of the sixth switch T6 and the gate of the eighth switch T8.

[0054] The first switch T1, the second switch T2, the third switch T3 and the fourth switch T4 are located in the second non-display area 126; the fifth switch T5, the sixth switch T6, the seventh switch T7 and the eighth switch T8 are located in the first non-display area 124.

[0055] In this embodiment, taking a single pixel unit 200 as an example, the single pixel unit 200 includes four sub-pixel columns 202, which are respectively designated as the first sub-pixel column 2022, the second sub-pixel column 2024, the third sub-pixel column 2026, and the fourth sub-pixel column 2028. Each of the above four sub-pixel columns 202 is electrically connected to two data lines, that is, there are a total of eight data lines.

[0056] Correspondingly, the demultiplexing circuit 16 includes 8 switching devices, such as... Figure 1 As shown, the switches are the first switch T1, the second switch T2, the third switch T3, the fourth switch T4, the fifth switch T5, the sixth switch T6, the seventh switch T7, and the eighth switch T8.

[0057] The demultiplexing circuit 16 includes four demultiplexing lines, denoted as Demux1, Demux2, Demux3, and Demux4. The gates of the first switch T1 and the third switch T3 are electrically connected to Demux1. The gates of the second switch T2 and the fourth switch T4 are electrically connected to Demux2. The gates of the fifth switch T5 and the seventh switch T7 are electrically connected to Demux3. The gates of the sixth switch T6 and the eighth switch T8 are electrically connected to Demux4.

[0058] Each of the above eight switching devices is electrically connected to a data line, thereby enabling independent control of the display drive signal switching of each data line.

[0059] The first switch T1, the second switch T2, the third switch T3, and the fourth switch T4 are located in the second non-display area 126, while the fifth switch T5, the sixth switch T6, the seventh switch T7, and the eighth switch T8 are located in the first non-display area 124. By placing half of the multiple switches in the first non-display area 124, i.e., the bottom bezel area of ​​the display screen, and placing the other half of the multiple switches in the second non-display area 126, i.e., the top bezel area of ​​the display screen, excessive space occupied by the demultiplexing circuit 16 on one side of the bezel area is avoided, thereby reducing the black border on one side of the bezel.

[0060] In some embodiments of this application, the third demultiplexing line Demux3 and the fourth demultiplexing line Demux4 are located in the first non-display area 124; at least a portion of the first demultiplexing line Demux1 and at least a portion of the second demultiplexing line Demux2 are located in the second non-display area 126.

[0061] In the embodiments of this application, such as Figure 1As shown, the third demultiplexing circuit Demux3 and the fourth demultiplexing circuit Demux4, as well as the corresponding fifth switch T5, sixth switch T6, seventh switch T7, and eighth switch T8, are located in the first non-display area 124. The first demultiplexing circuit Demux1 and the second demultiplexing circuit Demux2 pass around the periphery of the display panel 12, winding from the first non-display area 124 to the second non-display area 126, thereby placing the first switch T1, the second switch T2, the third switch T3, and the fourth switch T4 within the second non-display area 126. This method reduces the space occupied by the demultiplexing circuit 16 in the first non-display area 124, i.e., the single-sided bezel area, resulting in uniform black borders on the top and bottom bezels of the final mobile phone, avoiding a "large chin" appearance.

[0062] In some embodiments of this application, the demultiplexing circuit 16 includes:

[0063] The first source line S1, the input terminal of the first switch T1, the input terminal of the second switch T2, the input terminal of the third switch T3 and the input terminal of the fourth switch T4 are all electrically connected to the first source line S1.

[0064] The second source line S2, the input terminals of the fifth switch T5, the sixth switch T6, the seventh switch T7, and the eighth switch T8 are all electrically connected to the second source line S2.

[0065] In this embodiment, the demultiplexing circuit 16 further includes a first source line S1 and a second source line S2. The source lines are the core wire network driving the pixel unit 200 to emit light, responsible for transmitting the image signal voltage to each sub-pixel 202. The first source line S1 connects to the input terminals of the first switch T1, the second switch T2, the third switch T3, and the fourth switch T4. By controlling the switching states of the first switch T1, the second switch T2, the third switch T3, and the fourth switch T4, the image signal voltage can be transmitted to the first data line D1, the second data line D2, the third data line D3, and the fourth data line D4, respectively.

[0066] Similarly, the second source line S2 is connected to the input terminals of the fifth switch T5, the sixth switch T6, the seventh switch T7, and the eighth switch T8. By controlling the switching states of the fifth switch T5, the sixth switch T6, the seventh switch T7, and the eighth switch T8, the image signal voltage can be transmitted to the fifth data line D5, the sixth data line D6, the seventh data line D7, and the eighth data line D8, respectively.

[0067] In some embodiments of this application, the first source line S1 is electrically connected to the first data line D1 through the first switch T1, the first source line S1 is electrically connected to the second data line D2 through the second switch T2, the first source line S1 is electrically connected to the third data line D3 through the third switch T3, and the first source line S1 is electrically connected to the fourth data line D4 through the fourth switch T4.

[0068] The second source line S2 is electrically connected to the fifth data line D5 through the fifth switch T5, the second source line S2 is electrically connected to the sixth data line D6 through the sixth switch T6, the second source line S2 is electrically connected to the seventh data line D7 through the seventh switch T7, and the second source line S2 is electrically connected to the eighth data line D8 through the eighth switch T8.

[0069] In the embodiments of this application, such as Figure 1 As shown, the first source line S1 is connected to the first data line D1, the second data line D2, the third data line D3, and the fourth data line D4 via the first switch T1, the second switch T2, the third switch T3, and the fourth switch T4, respectively. By controlling the switching states of the first switch T1 to the fourth switch T4, the image signal voltage is transmitted to different data lines, thereby controlling different sub-pixels 202.

[0070] Similarly, the second source line S2 is connected to the fifth data line D5, the sixth data line D6, the seventh data line D7, and the eighth data line D8 via the fifth switch T5, the sixth switch T6, the seventh switch T7, and the eighth switch T8, respectively. By controlling the switching states of the fifth switch T5 to the eighth switch T8, the image signal voltage can be transmitted to different data lines, thereby controlling different sub-pixels 202.

[0071] Taking the second source line S2 as an example, the transmission process of the image signal voltage Data on the second source line S2 is described. Figure 1 As shown, Scan N to Scan N+4 are all gate scan lines. When Scan N+1 is on and the third demultiplexing line Demux3 is on, the second source line S2 transmits the data of the red sub-pixel R to the seventh data line D7 through the seventh switch T7 of the third demultiplexing line Demux3. When the third demultiplexing line Demux3 is off and the fourth demultiplexing line Demux4 is on, the second source line S2 transmits the data of the green sub-pixel G to the eighth data line D8 through the eighth switch T8 of the fourth demultiplexing line Demux4.

[0072] When Scan N+1 is closed and Scan N+2 is open, the second source line S2 transmits the data of the green sub-pixel G to the sixth data line D6 via the sixth switch T6 of the fourth demultiplexing line Demux4. When the fourth demultiplexing line Demux4 is closed and the third demultiplexing line Demux3 is open, the second source line S2 transmits the data of the blue sub-pixel B to the fifth data line D5 via the fifth switch T5 of the third demultiplexing line Demux3. The data transmission process on the second source line S2 will continue in the above manner. The data transmission of other source lines is similar to that of the second source line S2, and will not be elaborated further here.

[0073] For example, Figure 2 The following diagram illustrates the driving timing of the display component 10 according to some embodiments of this application, such as... Figure 1 and Figure 2 As shown, Scan N to Scan N+4 represent one gate scan line Scan. The drive timing control is as follows:

[0074] In stage t0: all demultiplexed lines are at low level, all gate scan lines are at low level, the first source line S1 and the second source line S2 are at low level, and the first data line D1 to the eighth data line D8 are also at low level. There is no charging behavior in this stage.

[0075] In phase t1: Scan N is at a high level, and the remaining gate scan lines Scan are at a low level. When the first demultiplexing line Demux1 is at a high level, the third switch T3 is turned on, and sub-pixel 13 is charged; when the second demultiplexing line Demux2 is at a high level, the fourth switch T4 is turned on, and sub-pixel 14 202 is charged.

[0076] In phase t2: Scan N+1 is high, and the remaining gate scan lines are low. When the first demultiplexing line Demux1 is high, the first switch T1 opens, and sub-pixel 11 is charged; when the third demultiplexing line Demux3 is high, the seventh switch T7 opens, and sub-pixel 23 is charged. When the second demultiplexing line Demux2 is high, the second switch T2 opens, and sub-pixel 12 is charged; when the fourth demultiplexing line Demux4 is high, the eighth switch T8 opens, and sub-pixel 24 is charged.

[0077] Phase t3: Scan N+2 is high, and the remaining gate scan lines are low. When the first demultiplexing line Demux1 is high, the third switch T3 opens, and sub-pixel 33 begins charging; when the third demultiplexing line Demux3 is high, the fifth switch T5 opens, and sub-pixel 21 begins charging. When the second demultiplexing line Demux2 is high, the fourth switch T4 opens, and sub-pixel 34 begins charging; when the fourth demultiplexing line Demux4 is high, the sixth switch T6 opens, and sub-pixel 22 begins charging.

[0078] In stage t4: Scan N+3 is high, and the remaining gate scan lines are low. When the first demultiplexing line Demux1 is high, the first switch T1 opens, and sub-pixel 31 is charged; when the third demultiplexing line Demux3 is high, the seventh switch T7 opens, and sub-pixel 43 is charged. When the second demultiplexing line Demux2 is high, the second switch T2 opens, and sub-pixel 32 is charged; when the fourth demultiplexing line Demux4 is high, the eighth switch T8 opens, and sub-pixel 44 is charged.

[0079] In stage t5: Scan N+4 is high, and the remaining gate scan lines are low. When the third demultiplexing line Demux3 is high, the fifth switch T5 is turned on, and sub-pixel number 41 is charged; when the fourth demultiplexing line Demux4 is high, the sixth switch T6 is turned on, and sub-pixel number 42 is charged.

[0080] In subsequent stages, refer to the above signal logic and start charging line by line.

[0081] In some embodiments of this application, each pixel unit 200 includes one blue sub-pixel B, one red sub-pixel R, and two green sub-pixels G; wherein the blue sub-pixel B and the red sub-pixel R are not adjacent, and the two green sub-pixels G are not adjacent.

[0082] In this embodiment, a pixel unit 200 includes four sub-pixels 202, namely one blue sub-pixel B, one red sub-pixel R, and two green sub-pixels G. Exemplarily, the four sub-pixels 202 are arranged in the order of red sub-pixel R, green sub-pixel G, blue sub-pixel B, and green sub-pixel G. Exemplarily, the four sub-pixels 202 are arranged in the order of blue sub-pixel B, green sub-pixel G, red sub-pixel R, and green sub-pixel G. Exemplarily, the four sub-pixels 202 are arranged in the order of green sub-pixel G, red sub-pixel R, green sub-pixel G, and blue sub-pixel B.

[0083] In some embodiments of this application, the first sub-pixel column 2022 includes a plurality of red sub-pixels R and a plurality of blue sub-pixels B, and the red sub-pixels R and blue sub-pixels B in the first sub-pixel column 2022 are alternately arranged;

[0084] The third sub-pixel column 2026 includes multiple red sub-pixels R and multiple blue sub-pixels B, and the red sub-pixels R and blue sub-pixels B in the third sub-pixel column 2026 are alternately set, and in the same row of sub-pixels 202, the color of the sub-pixels 202 in the first sub-pixel column 2022 is different from the color of the sub-pixels 202 in the third sub-pixel column 2026.

[0085] The second sub-pixel column 2024 and the fourth sub-pixel column 2028 each include multiple green sub-pixels G.

[0086] In the embodiments of this application, such as Figure 1 As shown, multiple pixel units 200 within the display area 122 are arranged in an X-row, Y-column array, with the Y-column pixel units 200 forming 4Y-column sub-pixels 202. Taking one column of pixel units 200 as a unit, one column of pixel units 200 includes a 4-column × X-row sub-pixel 202 matrix.

[0087] The first sub-pixel column 2022 contains alternating red sub-pixels R and blue sub-pixels B, such as... Figure 1 As shown, in the first sub-pixel 202, the sub-pixels 202 in two adjacent rows are a red sub-pixel R and a blue sub-pixel B, and this pattern is repeated.

[0088] The third sub-pixel column 2026 also contains alternating red sub-pixels R and blue sub-pixels B, such as Figure 1As shown, for sub-pixels 202 in the same row, if sub-pixel 202 in the first sub-pixel column 2022 is a red sub-pixel R, then sub-pixel 202 in the third sub-pixel column 2026 is a blue sub-pixel B. If sub-pixel 202 in the first sub-pixel column 2022 is a blue sub-pixel B, then sub-pixel 202 in the third sub-pixel column 2026 is a red sub-pixel R.

[0089] Sub-pixel 202 in the second sub-pixel column 2024 and the fourth sub-pixel column 2028 are both green sub-pixels G.

[0090] The second aspect of this application provides an electronic device that includes a display component 10 as provided in any of the above embodiments, and therefore also includes all the same technical effects, which will not be repeated here to avoid duplication.

[0091] For example, the electronic devices in the embodiments of this application include, but are not limited to, mobile phones, tablets, smartwatches, smart bracelets, and video game consoles.

[0092] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0093] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A display component, characterized in that, The display component includes: The display panel includes a display area, a first non-display area, and a second non-display area; wherein the display area includes pixel units, and the first non-display area and the second non-display area are respectively located on both sides of the display area; The display driver module is located in the first non-display area; The demultiplexing circuit has its input terminal electrically connected to the display driver module and its output terminal electrically connected to the pixel unit. The demultiplexing circuit includes multiple switching elements, some of which are located in the first non-display area and others of which are located in the second non-display area.

2. The display component according to claim 1, characterized in that, The number of pixel units is multiple, and multiple pixel units are arranged in an array. Each pixel unit includes 4 sub-pixels, and each sub-pixel is electrically connected to a gate scan line. The array of multiple pixel units includes multiple columns of pixel units, each column of pixel units includes 4 columns of sub-pixels, and each column of sub-pixels is electrically connected to the demultiplexing circuit through 2 data lines.

3. The display component according to claim 2, characterized in that, The four sub-pixel columns include a first sub-pixel column, a second sub-pixel column, a third sub-pixel column, and a fourth sub-pixel column; The data lines include a first data line, a second data line, a third data line, a fourth data line, a fifth data line, a sixth data line, a seventh data line, and an eighth data line; Specifically, the first sub-pixel column is electrically connected to the first data line and the fifth data line, the second sub-pixel column is electrically connected to the second data line and the sixth data line, the third sub-pixel column is electrically connected to the third data line and the seventh data line, and the fourth sub-pixel column is electrically connected to the fourth data line and the eighth data line.

4. The display component according to claim 3, characterized in that, The demultiplexing circuit includes: The first demultiplexing circuit is electrically connected to the gate of the first switching element and the gate of the third switching element. The second demultiplexing circuit is electrically connected to the gate of the second switch and the gate of the fourth switch. The third demultiplexing circuit is electrically connected to the gate of the fifth switch and the gate of the seventh switch. The fourth demultiplexing circuit is electrically connected to the gate of the sixth switching element and the gate of the eighth switching element. The first, second, third, and fourth switches are located in the second non-display area; the fifth, sixth, seventh, and eighth switches are located in the first non-display area.

5. The display component according to claim 4, characterized in that, The third demultiplexing line and the fourth demultiplexing line are located within the first non-display area; At least a portion of the first demultiplexed line and at least a portion of the second demultiplexed line are located within the second non-display area.

6. The display component according to claim 4, characterized in that, The demultiplexing circuit further includes: The first source line, the input terminal of the first switch, the input terminal of the second switch, the input terminal of the third switch and the input terminal of the fourth switch are all electrically connected to the first source line; The second source line, the input terminals of the fifth switch, the sixth switch, the seventh switch, and the eighth switch are all electrically connected to the second source line.

7. The display component according to claim 6, characterized in that, The first source line is electrically connected to the first data line through the first switch, the first source line is electrically connected to the second data line through the second switch, the first source line is electrically connected to the third data line through the third switch, and the first source line is electrically connected to the fourth data line through the fourth switch. The second source line is electrically connected to the fifth data line via the fifth switch, the second source line is electrically connected to the sixth data line via the sixth switch, the second source line is electrically connected to the seventh data line via the seventh switch, and the second source line is electrically connected to the eighth data line via the eighth switch.

8. The display component according to any one of claims 2 to 7, characterized in that, Each pixel unit includes one blue sub-pixel, one red sub-pixel, and two green sub-pixels; The blue sub-pixel is not adjacent to the red sub-pixel, and the two green sub-pixels are not adjacent to each other.

9. The display component according to any one of claims 3 to 7, characterized in that, The first sub-pixel column includes multiple red sub-pixels and multiple blue sub-pixels, and the red sub-pixels and blue sub-pixels in the first sub-pixel column are alternately arranged; The third sub-pixel column includes multiple red sub-pixels and multiple blue sub-pixels, and the red sub-pixels and blue sub-pixels in the third sub-pixel column are alternately arranged. In the same row of sub-pixels, the color of the sub-pixels in the first sub-pixel column is different from the color of the sub-pixels in the third sub-pixel column. The second sub-pixel column and the fourth sub-pixel column each include a plurality of green sub-pixels.

10. An electronic device, characterized in that, include: The display component as described in any one of claims 1 to 9.

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