Multichannel logic signal detection analyzer system

Abstract

The utility model relates to the field of embedded application technology discloses a kind of multi-channel logic signal detection analyzer system, comprising: multi-channel logic signal detection analyzer, multi-channel logic signal detection analysis work station and interface module;Multi-channel logic signal detection analyzer, interface module and multi-channel logic signal detection analysis work station are connected by integrated bus, and multi-channel logic signal detection analyzer is also connected to be detected equipment;Among them, the logic signal that the multi-channel logic signal detection analyzer is detected to equipment output is compressed to data, and the logic signal after processing is detected to obtain detection result, and detection result is sent to multi-channel logic signal detection analysis work station by integrated bus;Multi-channel logic signal detection analysis work station is used to display detection result. To solve the problem that channel expansibility is insufficient, and data storage and processing capacity are insufficient, and continuous long time signal analysis cannot be carried out.

Description

Technical Field

[0001] This utility model relates to the field of embedded application technology, and in particular to a multi-channel logic signal detection and analysis instrument system. Background Technology

[0002] With the increasing demand for digital signal logic state analysis and testing, the number of logic signal channels being tested is also increasing. However, multi-channel logic oscilloscope analysis technology or FIFO (First In First Out) memory designed in FPGA (Field-Programmable Gate Array) mode is insufficient to meet the requirements of "analysis of over 100 channels of logic signals". In addition, the logic signal acquisition process generates a large amount of data. If it is not compressed in time, the amount of measurement data will be extremely large, which will bring a huge workload to the subsequent data processing of the system. Therefore, it is difficult to meet the requirements of "analysis of over 100 channels of logic signals" and continuous signal analysis for a long time.

[0003] Typically, embedded control systems use a DIO (Digital Input / Output) bit operation mode to directly read the DIO status bits, reading only one DIO data interface signal at a time, which is inefficient. At the same time, due to the limitation of the number of DIO pins, it is difficult to meet the requirements of designing logic status analysis and detection with more than 100 channels. Utility Model Content

[0004] The purpose of this invention is to provide a multi-channel logic signal detection and analysis system to solve the problems of insufficient channel scalability, insufficient data storage and processing capabilities, and inability to perform continuous long-term signal analysis.

[0005] To address the aforementioned technical problems, this utility model provides a multi-channel logic signal detection and analysis system. The system includes a multi-channel logic signal detection and analysis instrument, a multi-channel logic signal detection and analysis workstation, and an interface module. The multi-channel logic signal detection and analysis instrument, the interface module, and the multi-channel logic signal detection and analysis workstation are connected in series via an integrated bus. The multi-channel logic signal detection and analysis instrument is also connected to a device under test. The multi-channel logic signal detection and analysis instrument is used to compress the logic signal output from the device under test, detect the processed logic signal to obtain a detection result, and send the detection result to the multi-channel logic signal detection and analysis workstation via the integrated bus. The interface module is used to transmit the signal data from the multi-channel logic signal detection and analysis instrument to the multi-channel logic signal detection and analysis workstation. The multi-channel logic signal detection and analysis workstation is used to display the detection result.

[0006] Compared to existing technologies, this utility model's multi-channel logic signal detection and analysis system connects the multi-channel logic signal detection and analysis instrument, interface module, and multi-channel logic signal detection and analysis workstation via an integrated bus. By introducing the interface module, the signal data from the multi-channel logic signal detection and analysis instrument is transmitted to the workstation in a multi-channel manner via the integrated bus. This solves the problem of low single-read efficiency in traditional DIO bit operation mode and improves the parallel transmission efficiency of multi-channel data. Furthermore, the multi-channel logic signal detection and analysis instrument performs data compression processing on the logic signals of the device under test, reducing the amount of data stored and transmitted. This solves the problems of high data storage pressure and high workload in subsequent data processing during logic signal acquisition, thereby improving the system's storage and processing efficiency and meeting the needs of continuous long-term signal analysis.

[0007] In addition, the multi-channel logic signal detection and analysis instrument includes at least a control chip, a test signal generator, a logic signal detector, and a data storage module. The control chip, as a central node, is connected to the test signal generator, the logic signal detector, and the data storage module via the integrated bus. The control chip is used to generate a detection signal based on the acquired logic signal, perform data compression processing on the logic signal, and send the processed logic signal and the detection signal to the logic signal detector. The control chip is also used to send the detection result generated by the logic signal detector to the multi-channel logic signal detection and analysis workstation and the data storage module. The test signal generator is used to generate a test signal, which is forwarded to the logic signal detector via the control chip. The logic signal detector is used to detect the processed logic signal based on the detection signal, perform a self-test based on the test signal forwarded by the control chip, and send the detection result and the self-test result to the control chip. The data storage module is used to store the processed logic signal and the detection result.

[0008] In addition, the control chip includes at least a DIO interface and an SDIO interface; wherein, the control chip is connected to the integrated bus through the DIO interface, and then connected to the test signal generator and the logic signal detector through the integrated bus to transmit the detection signal and the processed logic signal; the control chip is connected to the integrated bus through the SDIO interface, and then connected to the data storage module through the integrated bus to transmit the processed logic signal and the detection result.

[0009] In addition, the interface module includes at least a USB interface and an ETH interface.

[0010] Additionally, the USB interface is either a native USB interface or an RS-232 interface; the ETH interface is an RJ45 network port.

[0011] In addition, the logic signal detector includes several logic detection interfaces, each of which is connected to the control chip via the integrated bus; wherein, the logic detection interface is used to receive the detection signal and the test signal.

[0012] In addition, the integrated bus includes a data bus, an address bus, and a control bus.

[0013] In addition, the multi-channel logic signal detection and analysis instrument also includes a front-end signal interface for connecting to external devices to obtain the logic signals of the external devices.

[0014] In addition, the multi-channel logic signal detection and analysis instrument also includes a register; the register is connected to the front-end signal interface and is used to store the acquired logic signals of the device under test.

[0015] In addition, the multi-channel logic signal detection and analysis workstation is a PC-based multi-channel logic signal detection and analysis workstation. Attached Figure Description

[0016] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of a multi-channel logic signal detection and analysis instrument system according to an embodiment of the present invention;

[0018] Figure 2 This is a schematic diagram of the structure of a multi-channel logic signal detection and analysis instrument according to an embodiment of the present invention;

[0019] Figure 3 This is a schematic diagram of the structure of a logic signal detector according to an embodiment of the present invention;

[0020] Figure 4 This is a schematic diagram of the interface module provided according to an embodiment of the present utility model. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this utility model clearer, the various embodiments of this utility model will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the various embodiments of this utility model to facilitate a better understanding of the invention. However, the technical solutions claimed in the claims of this utility model can be implemented even without these technical details and with various variations and modifications based on the following embodiments.

[0022] One embodiment of this utility model relates to a multi-channel logic signal detection and analysis instrument system. For example... Figure 1As shown. The multi-channel logic signal detection and analysis system includes: a multi-channel logic signal detection and analysis instrument 101, a multi-channel logic signal detection and analysis workstation 103, and an interface module 102; the multi-channel logic signal detection and analysis instrument 101, the interface module 102, and the multi-channel logic signal detection and analysis workstation 103 are connected in series via an integrated bus, and the multi-channel logic signal detection and analysis instrument 101 is also connected to the device under test; wherein, the multi-channel logic signal detection and analysis instrument 101 is used to compress the logic signal output by the device under test, detect the processed logic signal to obtain the detection result, and send the detection result to the multi-channel logic signal detection and analysis workstation 103 via the integrated bus; the interface module 102 is used to transmit the signal data of the multi-channel logic signal detection and analysis instrument 101 to the multi-channel logic signal detection and analysis workstation 103; the multi-channel logic signal detection and analysis workstation 103 is used to display the detection result.

[0023] Specifically, the multi-channel logic signal detection and analysis system includes at least: a multi-channel logic signal detection and analysis instrument 101, an interface module 102, and a multi-channel logic signal detection and analysis workstation 103. The multi-channel logic signal detection and analysis instrument 101 and the multi-channel logic signal detection and analysis workstation 103 are connected via the interface module 102. The multi-channel logic signal detection and analysis instrument 101 can connect to the multi-channel logic signal detection and analysis workstation 103 via either a USB interface or an RJ45 network interface in the interface module 102, thereby transmitting signal data from the multi-channel logic signal detection and analysis instrument 101 to the multi-channel logic signal detection and analysis workstation 103.

[0024] The multi-channel logic signal detection and analysis workstation 103 can be a PC-based workstation that can display, analyze, and process logic digital signals.

[0025] This invention connects a multi-channel logic signal detection and analysis instrument 101, an interface module 102, and a multi-channel logic signal detection and analysis workstation 103 in series via an integrated bus. By introducing the interface module 102, the signal data from the multi-channel logic signal detection and analysis instrument 101 is transmitted to the workstation via the integrated bus in a multi-channel manner. This solves the problem of low single-read efficiency in traditional DIO bit operation mode and improves the parallel transmission efficiency of multi-channel data. Furthermore, the multi-channel logic signal detection and analysis instrument 101 performs data compression processing on the logic signals of the device under test, reducing the amount of data stored and transmitted. This solves the problems of high data storage pressure and high workload in subsequent data processing during logic signal acquisition, thereby improving the system's storage and processing efficiency and meeting the needs of continuous long-term signal analysis.

[0026] To facilitate better understanding by those skilled in the art Figure 1 The structure of the digital sensor simulator shown below will be further explained.

[0027] In some embodiments, the specific structure of the multi-channel logic signal detection and analysis instrument can also be as follows: Figure 2 As shown, it includes the following components:

[0028] The multi-channel logic signal detection and analysis instrument includes a control chip 201, a test signal generator 202, a logic signal detector 203, and a data storage module 204. The control chip 201, acting as a central node, is connected to the test signal generator 202, the logic signal detector 203, and the data storage module 204 via an integrated bus. The control chip 201 generates a detection signal based on the acquired logic signal, performs data compression on the logic signal, and sends the processed logic signal and detection signal to the logic signal detector 203. The control chip 201 also sends the detection results generated by the logic signal detector 203 to the multi-channel logic signal detection and analysis workstation and the data storage module 204. The test signal generator 202 generates a test signal, which is forwarded to the logic signal detector 203 via the control chip 201. The logic signal detector 203 detects the processed logic signal based on the detection signal and performs a self-test based on the test signal forwarded by the control chip 201, sending the detection results and self-test results back to the control chip 201. The data storage module 204 stores the processed logic signal and the detection results.

[0029] The control chip 201 can be an STM32F407 embedded control chip. This invention stores a data compression program designed in C language within the STM32F407 control chip to achieve data compression processing. By analyzing the signal to be detected, data similarity and repetition are judged to establish "basic block compressed data." Further secondary compression combines data based on the necessity of block data transmission characteristics, forming a highly efficient compressed data file, facilitating subsequent data decompression and transmission processing, and improving the efficiency of the condensed data. The implementation process of the data compression program can be as follows: First, the acquired logic signal data is standardized in format, with 32 channels of data forming a data block, including: a relative sampling timestamp δt, a data packet number, and 32 channel logic data values. The control chip 201 identifies the logic signal data sampled each time within the relative sampling timestamp δt, determines whether the logic signal data is the same, and thus determines whether to update the data. The data blocks are further combined: a data block group number is determined, and each group consists of 32 channel logic data values. The data packets for each data transmission can be of varying lengths, with the number of data packets determined on a per-packet basis. The above methods can reduce the amount of data processed and transmitted, resulting in high transmission efficiency.

[0030] In this way, the multi-channel logic signal detection and analysis system of this invention can immediately perform data processing and compression calculations on the acquired data, significantly reducing the amount of subsequent data processing, data storage, and data transmission. Simultaneously, the compressed data forms data acquisition and transmission packets, facilitating storage on external storage devices and enabling communication and data exchange between the multi-channel logic signal detection and analysis system and the logic signal detection and analysis workstation.

[0031] In some embodiments, the control chip 201 in the multi-channel logic signal detection and analysis instrument may also have the following structure: the control chip 201 further includes at least a DIO interface 205 and an SDIO interface 206; wherein, the control chip is connected to the integrated bus through the DIO interface 205, and then connected to the test signal generator 202 and the logic signal detector 203 through the integrated bus to transmit the detection signal and the processed logic signal; the control chip is connected to the integrated bus through the SDIO (Secure Digital Input / Output) interface 206, and then connected to the data storage module 204 through the integrated bus to transmit the processed logic signal and the detection result.

[0032] The control chip has an SDIO interface 206 and a DIO general interface. The control chip connects to the test signal generator 202 and the logic signal detector 203 through the DIO general interface. The DIO general interface connects to the data bus and address bus that conform to the memory operation mode, and the sampling storage content transmission mode greatly improves the data acquisition and analysis capability of logic signal detection and analysis.

[0033] The test signal generator 202 is used to generate 32 standard test signals with preset frequencies and waveforms, which facilitates "self-testing" before the equipment is used, ensuring that the multi-channel logic signal detection and analysis instrument is in good working order.

[0034] The storage module 204 can be a TF card, and the control chip implements a standard TF card interface through the general-purpose SDIO interface 206 to connect the TF card. By implementing read and write functions based on the TF card, the system's measurement data storage capacity is significantly improved, expanding from the original M-level to the G-level. This increases the continuous multi-channel logic signal sampling and analysis time of the multi-channel logic signal detection and analysis instrument to over 8 hours. Furthermore, several acquired data files are stored with different file names, providing data traceability. Thus, by designing the storage module, the long-term operation requirements of the high-speed digital logic signal detection device are met, while the large amount of acquired measurement data can be completely preserved and retrieved through files, providing data traceability for historical measurement processes.

[0035] In some embodiments, for the logic signal detector in a multi-channel logic signal detection and analysis instrument, such as Figure 3 As shown, it may include the following structural components: The logic signal detector 203 includes several logic detection interfaces (2031 to 2036), each logic detection interface is connected to the control chip 201 through the integrated bus, and the logic signal detector 203 receives detection signals and test signals through the logic detection interfaces.

[0036] Each logic detection interface is a 32-channel interface. Depending on the required number of channels, multiple logic detection interfaces can be combined to obtain logic signal interfaces with 32 channels (2031), 64 channels (combination of 2031 and 2032), 96 channels (combination of 2031 to 2033), 128 channels (combination of 2031 to 2034), 160 channels (combination of 2031 to 2035), or 192 channels (combination of 2031 to 2036). This allows the logic signal detector to receive detection and test signals through different channels, thus solving the problem of synchronous locking technology in real-time logic signal acquisition and realizing a method for simultaneous reading under a single instruction in an embedded system.

[0037] Those skilled in the art will understand that there can be more than one logic signal detector in this invention. Multiple logic signal detectors can be connected to the control chip of a multi-channel logic signal detection and analysis instrument at the same time. This can obtain a larger number of logic data acquisition, processing and analysis channels, solve the problem of synchronization locking technology for real-time acquisition of logic signals, and make the synchronization of digital logic signal measurement less than 1μs (microseconds).

[0038] Furthermore, in some embodiments, the multi-channel logic signal detection and analysis instrument also includes a front-end signal interface for connecting to external devices to obtain logic signals from the external devices.

[0039] The front-end signal interface can be a conditioning interface for logic signal transmission, specifically N 32-channel standard interfaces. The multi-channel logic signal detection and analysis instrument receives the logic signals to be analyzed through its multiple 32-channel standard interfaces, and performs detection, analysis, and compression on the logic signals of each channel. The processed data can then be stored locally, written to a TF card in a compressed data format, and transmitted in real-time to the connected multi-channel logic signal detection and analysis workstation via the interface module. This enables multi-channel logic data analysis and waveform display.

[0040] This invention incorporates long-line signal conditioning measures and impedance matching real-time filtering at the front-end signal interface to meet the requirements of long-line transmission of transistor digital logic signals. Typically, long-line transmission of transistor digital logic signals (5-15 meters) requires signal enhancement processing. A common solution is to enhance the 0-3V digitized signal to ±6V or 0-12V. This invention utilizes the Laplace signal processing principle to condition the measured signal in a multi-channel logic signal detection and analysis instrument, ensuring the measured logic signal meets the requirements for measurement data acquisition applications.

[0041] Furthermore, in some embodiments, the multi-channel logic signal detection and analysis instrument also includes a register; the register is connected to the front-end signal interface and is used to store the acquired logic signals of the device under test.

[0042] The multi-channel logic signal detection and analysis instrument's front-end signal interface connects to several registers to buffer the logic signals to be detected, awaiting subsequent reading of the logic signal data by the logic signal detector. The data reading of the multi-channel logic signal detection and analysis instrument conforms to the memory unit bus rules of embedded systems; therefore, reading one byte of data at a time means processing data from 16 channels, greatly improving data processing capabilities.

[0043] Furthermore, in some embodiments, the interface module includes at least: a USB (Universal Serial Bus) interface and an ETH (Ethernet Interface) interface; the USB interface is a native USB interface or an RS-232 interface; the ETH interface is an RJ45 network port.

[0044] Among them, the USB interface in the interface module is an interface that can realize USB function, which can be a native USB interface or an RS-232 interface; the ETH interface is a network interface type, which can be an RJ45 network interface or other interfaces that can realize network communication function.

[0045] like Figure 4 As shown, the interface module is connected to the control chip of the multi-channel logic signal detection and analysis instrument through various interfaces.

[0046] The interface module converts the UART (Universal Asynchronous Receiver / Transmitter) interface of the control chip of the multi-channel logic signal detection and analysis instrument into a USB-enabled interface via an RS-232 interface. The native USB interface functions as a USB flash drive read / write interface, allowing the control chip of the multi-channel logic signal detection and analysis instrument to store the generated detection results. The ETH interface (RJ45 network interface) of the interface module connects to the control chip of the multi-channel logic signal detection and analysis instrument, and the other end of the ETH interface also connects to the multi-channel logic signal detection and analysis workstation. In this way, the multi-channel logic signal detection and analysis instrument can be connected to the multi-channel logic signal detection and analysis workstation through the above interfaces. The USB and RJ45 network interfaces have a data transmission capacity of up to 1000KBd, enabling the system to meet the requirements of high-speed data acquisition and exchange, with data acquisition synchronization accuracy reaching 10⁻⁶ seconds (1μS).

[0047] Furthermore, in some embodiments, the integrated bus includes a data bus, an address bus, and a control bus.

[0048] Specifically, the number of channels on the data bus, address bus, and control bus between the multi-channel logic signal detection and analysis instrument, the multi-channel logic signal detection and analysis workstation, and the interface module are completely matched; the number of channels on the data bus, address bus, and control bus between the control chip, test signal generator, logic signal detector, and data storage module inside the multi-channel logic signal detection and analysis instrument is completely matched; and the number of channels on the data bus between the multi-channel logic signal detection and analysis instrument and the external device under test is completely matched. Therefore, during signal transmission or signal reading, one byte of data can be read at a time, meaning that data from 16 channels is processed in one read, greatly improving data processing capabilities.

[0049] It is understood that the same or similar parts in the above embodiments can be referred to each other, and the contents not described in detail in some embodiments can be referred to the same or similar contents in other embodiments.

[0050] It should be noted that in the description of this embodiment, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this embodiment, unless otherwise stated, "multiple" or "many" means at least two.

[0051] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this embodiment. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0052] Those skilled in the art will understand that the above embodiments are specific examples of implementing the present invention, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the present invention.

[0053] Those skilled in the art will understand that the above embodiments are specific examples of implementing the present invention, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the present invention.

Claims

1. A multi-channel logic signal detection and analysis instrument system, characterized in that, The system includes: a multi-channel logic signal detection and analysis instrument, a multi-channel logic signal detection and analysis workstation, and an interface module; the multi-channel logic signal detection and analysis instrument, the interface module, and the multi-channel logic signal detection and analysis workstation are connected in series via an integrated bus, and the multi-channel logic signal detection and analysis instrument is also connected to the device under test; wherein... The multi-channel logic signal detection and analysis instrument is used to compress the logic signals output by the device under test, detect the processed logic signals to obtain detection results, and send the detection results to the multi-channel logic signal detection and analysis workstation via the integrated bus; wherein... The multi-channel logic signal detection and analysis instrument includes at least a control chip, a test signal generator, a logic signal detector, and a data storage module. The control chip, acting as a central node, is connected to the test signal generator, the logic signal detector, and the data storage module via the integrated bus. The control chip includes at least a DIO interface and an SDIO interface. The control chip connects to the integrated bus via the DIO interface, and then connects to the test signal generator and the logic signal detector via the integrated bus. The control chip connects to the integrated bus via the SDIO interface, and then connects to the data storage module via the integrated bus. The logic signal detector includes several logic detection interfaces, and each logic detection interface is connected to the control chip through the integrated bus; The multi-channel logic signal detection and analysis instrument also includes a register; the register is connected to the front-end signal interface and is used to store the acquired logic signals of the device under test; The interface module is used to transmit the signal data of the multi-channel logic signal detection and analysis instrument to the multi-channel logic signal detection and analysis workstation; The multi-channel logic signal detection and analysis workstation is used to display the detection results.

2. The multi-channel logic signal detection and analysis system according to claim 1, characterized in that, The control chip is used to generate a detection signal based on the acquired logic signal, perform data compression processing on the logic signal, and send the processed logic signal and detection signal to the logic signal detector; the control chip is also used to send the detection result generated by the logic signal detector to the multi-channel logic signal detection and analysis workstation and the data storage module; The test signal generator is used to generate a test signal and send the test signal to the control chip; The logic signal detector is used to detect the processed logic signal according to the detection signal, and to perform a self-test according to the test signal sent by the control chip, and to send the detection result and the self-test result to the control chip. The data storage module is used to store the processed logic signal and the detection result.

3. The multi-channel logic signal detection and analysis system according to claim 2, characterized in that, The control chip transmits the detection signal and the processed logic signal; The control chip transmits the processed logic signal and the detection result.

4. The multi-channel logic signal detection and analysis system according to claim 1 or 2, characterized in that, The interface module includes at least a USB interface and an ETH interface.

5. The multi-channel logic signal detection and analysis system according to claim 4, characterized in that, The USB interface is either a native USB interface or an RS-232 interface; the ETH interface is an RJ45 network port.

6. The multi-channel logic signal detection and analysis system according to claim 2, characterized in that, The logic detection interface is used to receive the detection signal and the test signal.

7. The multi-channel logic signal detection and analysis system according to claim 1, characterized in that, The integrated bus includes a data bus, an address bus, and a control bus.

8. The multi-channel logic signal detection and analysis system according to claim 1, characterized in that, The multi-channel logic signal detection and analysis instrument also includes a front-end signal interface for connecting to the device under test in order to obtain the logic signals of the device under test.

9. The multi-channel logic signal detection and analysis system according to claim 1, characterized in that, The multi-channel logic signal detection and analysis workstation is a PC-based multi-channel logic signal detection and analysis workstation.

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