Signal processing device and receiver

By combining the reference clock signal acquisition module and the crystal oscillator calibration module, the problem of unstable voltage-controlled crystal oscillator frequency was solved, and a high-precision 102.4MHz clock signal output was achieved, meeting the high-precision requirements of the signal processing device.

CN224343179UActive Publication Date: 2026-06-09JIANGSU CHANGWU COMM TECH CO LTD
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Patent Information

Application Number
CN202521682566.7
Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
Filing Date
2025-08-08
Publication Date
2026-06-09
Estimated Expiration
2035-08-08

AI Technical Summary

Technical Problem

The frequency stability and accuracy of voltage-controlled crystal oscillators are affected by factors such as temperature sensitivity, power supply noise, voltage fluctuations and ambient humidity, which can lead to unstable clock signals and affect the accuracy of signal acquisition and processing.

Method used

A combination of a reference clock signal acquisition module, a 10MHz crystal oscillator calibration module, and a 102.4MHz phase-locked loop module is used to calibrate the 10MHz clock signal using the reference clock signal, and the programmable controller is used for adjustment and configuration to ensure the accurate output of the 102.4MHz clock signal.

Benefits of technology

The frequency stability of the 102.4MHz clock signal reached the ±1E-8 level, meeting the high-precision requirements of signal acquisition and processing, and providing accurate acquisition clock and system clock for digital processing devices.

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Abstract

This utility model belongs to the field of electronic circuit technology, specifically relating to a signal processing device and receiver. The signal processing device includes: a programmable controller, a reference clock signal acquisition module, a 10MHz crystal oscillator calibration module, and a 102.4MHz phase-locked loop (PLL) module. The reference clock signal acquisition module acquires a reference clock signal; the 10MHz crystal oscillator calibration module outputs the original 10MHz clock signal to the programmable controller, and the programmable controller feeds back a corresponding adjustment signal to the 10MHz crystal oscillator calibration module; and the 102.4MHz PLL module outputs a 102.4MHz clock signal. This utility model achieves real-time adjustment of the crystal frequency error, enabling the signal processing device to output a 102.4MHz clock signal at the ±1E-8 level, providing accurate acquisition and system clocks for digital processing devices, and meeting the high-precision requirements of signal acquisition and signal processing.
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