On-chip test integrated circuit for power amplifier

Abstract

The utility model is suitable for microwave amplifier technical field provides a kind of wafer test integrated circuit of power amplifier, it includes: power amplifier, N probe device and power supply, N is positive integer;The gate electrode pressure point and drain electrode pressure point of the power amplifier are separately arranged as separate pressure point, and each separate gate electrode pressure point and / or drain electrode pressure point is respectively connected to the corresponding channel of power supply by corresponding probe device.This utility model can greatly reduce the feedback or crosstalk between multistage amplifier, reduce self-excitation, and then improve the stability of wafer test amplifier.

Description

Technical Field

[0001] This utility model belongs to the field of microwave amplifier technology, and in particular relates to an on-chip test integrated circuit for a power amplifier. Background Technology

[0002] Typically, for monolithic microwave integrated circuits (MMICs), especially multi-stage MMICs, due to their high gain and wide frequency coverage, coupled with the limitation of chip area, it is impossible to place large decoupling capacitors on the chip. Therefore, the focus can only be on the in-band and high-frequency stability of the amplifier, while the stability at the low-frequency end usually requires the addition of large decoupling capacitors, bypass capacitors, and resistors outside the chip.

[0003] However, due to the inability to add suitable capacitors and resistors to the external components when performing on-chip testing of the power amplifier, the on-chip test self-oscillates, making it impossible to obtain test data for the entire wafer, which in turn affects subsequent work. Utility Model Content

[0004] In view of this, the present invention provides an on-chip test integrated circuit for power amplifiers to solve the problem of self-oscillation that is easily generated when power amplifiers are tested on-chip in the prior art.

[0005] The first aspect of this utility model provides an on-chip test integrated circuit for a power amplifier, comprising: a power amplifier, N probe devices, and a power supply, where N is a positive integer;

[0006] The gate electrode and drain electrode of the power amplifier are each set as separate electrodes, and each separate gate electrode and / or drain electrode is connected to a corresponding channel of the power supply via a corresponding probe device.

[0007] In one possible implementation, the probe device includes: two probes and M decoupling capacitors, where M is a positive integer;

[0008] M decoupling capacitors are fixedly connected between the two probes;

[0009] One end of the first probe between the two probes is connected to the gate electrode point or the drain electrode point, and the other end of the first probe is connected to the corresponding channel of the power supply. One end of the other second probe between the two probes is used for grounding, and the other end is connected to the corresponding channel of the power supply.

[0010] In one possible implementation, the probe device further includes: a probe holder and an epoxy resin substrate;

[0011] The two probes are respectively fixed on the corresponding epoxy resin substrates, and the epoxy resin substrates are fixed on the probe holders.

[0012] In one possible implementation, the two probes are arranged side by side.

[0013] In one possible implementation, the two probes are welded to a corresponding epoxy resin substrate;

[0014] A metal microstrip line is fixed on each epoxy resin substrate and soldered to the tail of the corresponding probe. One metal microstrip line is used to connect to the corresponding channel of the power supply, and the other metal microstrip line is used for grounding.

[0015] In one possible implementation, when M is greater than or equal to 2, decoupling capacitors of different capacitance values ​​are welded to different positions between the two probes.

[0016] In one possible implementation, the power supply is a DC power supply, and N separate power supply channels are provided.

[0017] In one possible implementation, the power amplifier is a two-stage or higher amplifier.

[0018] In one possible implementation, the probe is a DC probe.

[0019] The beneficial effects of this utility model embodiment compared with the prior art are as follows: First, the separate electrode pressure point used in the power amplifier improves the isolation between each stage at the chip level. Second, a separate power supply channel is used for power supply, which further increases the isolation between each stage. Finally, corresponding probes are used to connect the electrode pressure point and the power supply channel, which further improves the isolation, greatly reduces feedback or crosstalk between multi-stage amplifiers, reduces self-oscillation, and thus improves the stability of the on-chip test amplifier. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the structure of a power amplifier in the prior art provided by this utility model embodiment;

[0022] Figure 2 This is a schematic diagram of the on-chip test integrated circuit of the power amplifier provided in this embodiment of the present invention;

[0023] Figure 3 This is a schematic diagram of the probe device provided in an embodiment of the present invention. Detailed Implementation

[0024] In the following description, specific details such as particular system structures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of the present invention. However, those skilled in the art will understand that the present invention can be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.

[0025] To illustrate the technical solution described in this utility model, specific embodiments are described below.

[0026] Power amplifiers in the prior art, such as Figure 1 As shown, the gate electrode and drain electrode are interconnected in the power amplifier. During on-chip testing, signal crosstalk between the interconnected electrodes can easily occur, leading to signal feedback between multiple amplifier stages and oscillation at a specific frequency, resulting in self-oscillation.

[0027] Therefore, this invention provides an on-chip test integrated circuit for a power amplifier, see [link to relevant documentation]. Figure 2 The structural diagram shown is described in detail below:

[0028] The on-chip test integrated circuit for the power amplifier includes: a power amplifier 1, N probe devices 2, and a power supply 3, where N is a positive integer;

[0029] The gate electrode and drain electrode of the power amplifier 1 are set as separate electrodes, and each separate gate electrode and / or drain electrode is connected to a corresponding channel of the power supply 3 through a corresponding probe device 2.

[0030] See Figure 2 Power amplifier 1 is a two-stage amplifier. In this embodiment, the number of stages of the power amplifier is not limited, and it can be a two-stage or higher amplifier.

[0031] See Figure 2 The gate electrode voltage point of power amplifier 1 is denoted by VG, and the drain electrode voltage point of power amplifier 1 is denoted by VD. In this embodiment, the gate electrode and drain electrode are separated in the prior art and no longer interconnected within the chip, but are set as separate gate electrode voltage points and drain electrode voltage points. Figure 2This includes separate gate electrode voltage points VG1 and VG2, and separate drain electrode voltage points VD1 and VD2. This improves the isolation between stages, thereby reducing feedback and inter-stage winding, reducing self-oscillation during on-chip testing, and improving the stability of the power amplifier during on-chip testing.

[0032] It should be noted that the connection between the individual gate electrode pressure point and the drain electrode pressure point and the corresponding probe can be by contact, that is, the corresponding probe can be in contact with the pressure point. In this way, the probe device can be used as a separate device on different power amplifiers, can be reused, and improves applicability.

[0033] It should be noted that, see Figure 2 As shown, the power amplifier 1 may also include an input matching module, an inter-electrode matching module, and an output matching module. A corresponding capacitor, such as capacitor C0, capacitor C1, capacitor C2, and capacitor C3, is also connected to the gate electrode voltage point and the drain electrode voltage point, respectively.

[0034] In one embodiment, see Figure 3 As shown, the probe device 2 may include: two probes and M decoupling capacitors 22, where M is a positive integer;

[0035] M decoupling capacitors 22 are fixedly connected between the two probes;

[0036] One end of any first probe 211 between the two probes is connected to the gate electrode point or the drain electrode point, and the other end of the first probe 211 is connected to the corresponding channel of the power supply 3. One end of the other second probe 212 between the two probes is grounded, and the other end is connected to the corresponding channel of the power supply 3. In this way, the gate electrode point and / or drain electrode point of the power amplifier 1 are respectively connected to the corresponding channel of the power supply through the corresponding first probe 211, so that each point can be powered independently, which further increases the isolation between stages of the power amplifier, greatly reduces feedback or crosstalk between multiple amplifiers, and thus improves the stability of the on-chip test amplifier.

[0037] In addition, the decoupling resistor between the two probes can effectively eliminate self-excitation and oscillation problems generated during on-chip testing, further improving the stability of the on-chip test integrated circuit of the power amplifier.

[0038] In one embodiment, the probe device 2 may further include: a probe holder 23 and an epoxy resin substrate 24;

[0039] The two probes are respectively fixed on corresponding epoxy resin substrates 24, and the epoxy resin substrates 24 are fixed on the probe holders 23. Fixing the two probes to the probe holders 23 can better protect the probes, prevent breakage, and make them more convenient to use.

[0040] In one embodiment, the two probes are arranged side by side, which is not only smaller in size than a probe card, but also easier to move and use.

[0041] In one embodiment, the two probes are soldered onto a corresponding epoxy resin substrate 24;

[0042] A metal microstrip line is fixed on each epoxy resin substrate 24 and soldered to the tail of the corresponding probe. One metal microstrip line is used to connect to the corresponding channel of the power supply, and the other metal microstrip line 22 is used for grounding.

[0043] Using a soft-material metal microstrip line for grounding or connecting to the power supply can reduce the length of the probe, lower the cost, protect the probe from breakage, and make it easier to connect to the power supply, thus improving operability.

[0044] In one embodiment, when M is greater than or equal to 2, decoupling capacitors of different capacitance values ​​are welded at different positions between the two probes.

[0045] For example, the front ends of the two probes are fixed with probe front capacitors, the middle part of the two probes is fixed with probe middle capacitors, and the tail ends of the two probes are fixed with probe tail capacitors, and the capacitance values ​​of the probe front capacitors, probe middle capacitors, and probe tail capacitors are different.

[0046] Optionally, the capacitance values ​​of the probe tip capacitor, probe middle capacitor, and probe tail capacitor are arranged in ascending order. The capacitance values ​​of the probe tip capacitor, probe middle capacitor, and probe tail capacitor can be fine-tuned according to different test circuits.

[0047] By welding capacitors of different capacitance values ​​to the front and middle parts of the probe, and welding a large-value decoupling capacitor to its tail, the actual distance between chips can be reduced, thereby reducing the influence of parasitic parameters and eliminating self-excitation and oscillation.

[0048] In one embodiment, see Figure 2 As shown, the power supply 3 is a DC power supply and has N separate power supply channels to ensure that each channel is powered independently, which further increases the isolation between each level.

[0049] In one embodiment, the probe is a DC probe.

[0050] In the on-chip test integrated circuit of the power amplifier described above, the gate electrode voltage point and the drain electrode voltage point of the power amplifier are respectively set as separate voltage points, and each separate gate electrode voltage point and / or drain electrode voltage point is respectively connected to the corresponding channel of the power supply through a corresponding probe device.

[0051] First, the use of a separate electrode point in the power amplifier improves the isolation between stages at the chip level. Second, the use of multi-channel power supply further increases the isolation between stages. Finally, the use of DC decoupling probes eliminates the influence of power supply leads, further improving isolation, greatly reducing feedback or crosstalk between multi-stage amplifiers, reducing self-oscillation, and thus improving the stability of the on-chip test amplifier.

[0052] The above-described embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model, and should all be included within the protection scope of this utility model.

Claims

1. An on-chip test integrated circuit for a power amplifier, characterized in that, include: A power amplifier, N probe devices, and a power supply, where N is a positive integer; The gate electrode and drain electrode of the power amplifier are each set as separate electrodes, and each separate gate electrode and / or drain electrode is connected to a corresponding channel of the power supply via a corresponding probe device.

2. The on-chip test integrated circuit for the power amplifier as described in claim 1, characterized in that, The probe device includes: two probes and M decoupling capacitors, where M is a positive integer; M decoupling capacitors are fixedly connected between the two probes; One end of the first probe between the two probes is connected to the gate electrode point or the drain electrode point, and the other end of the first probe is connected to the corresponding channel of the power supply. One end of the other second probe between the two probes is used for grounding, and the other end is connected to the corresponding channel of the power supply.

3. The on-chip test integrated circuit for the power amplifier as described in claim 2, characterized in that, The probe device further includes: a probe holder and an epoxy resin substrate; The two probes are respectively fixed on the corresponding epoxy resin substrates, and the epoxy resin substrates are fixed on the probe holders.

4. The on-chip test integrated circuit for the power amplifier as described in claim 2, characterized in that, The two probes are arranged side by side.

5. The on-chip test integrated circuit for the power amplifier as described in claim 3, characterized in that, The two probes are welded onto the corresponding epoxy resin substrates; A metal microstrip line is fixed on each epoxy resin substrate and soldered to the tail of the corresponding probe. One metal microstrip line is used to connect to the corresponding channel of the power supply, and the other metal microstrip line is used for grounding.

6. The on-chip test integrated circuit for the power amplifier as described in claim 2, characterized in that, When M is greater than or equal to 2, decoupling capacitors of different capacitance values ​​are welded at different positions between the two probes.

7. The on-chip test integrated circuit for the power amplifier as described in any one of claims 1-6, characterized in that, The power supply is a DC power supply, and it has N separate power supply channels.

8. The on-chip test integrated circuit for the power amplifier as described in any one of claims 1-6, characterized in that, The power amplifier is a two-stage or higher amplifier.

9. The on-chip test integrated circuit for the power amplifier as described in any one of claims 1-6, characterized in that, The probe is a DC probe.

Images