Four-input serial adder and multi-input serial adder
By designing four-input and multi-input serial adders and adopting a serial accumulation and parallel carry approach, the problems of high resource overhead and bit width limitation of adder tree circuits are solved, achieving high computational performance and flexible adder bit width support.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- BEIJING GL MICROELECTRONICS TECHNOLOGY CO LTD
- Filing Date
- 2025-06-23
- Publication Date
- 2026-06-12
AI Technical Summary
Existing adder tree circuits suffer from high resource overhead, high computational latency, and insufficient flexibility, especially in parallel adder tree circuits. Furthermore, serial pulse signal accumulation calculations are prone to overflow and increased computational latency.
A four-input serial adder and a multi-input serial adder were designed. By dividing the input module and the output module into serial adders, a serial accumulation and parallel carry method was adopted to ensure that the input period and the output period are equal to the maximum bit width of the input addend. D flip-flops and selectors were used to process the carry data.
It effectively reduces hardware resource consumption, solves the maximum bit width limitation, improves computing performance, supports arbitrary bit width addition, and saves hardware resource overhead.
Smart Images
Figure CN224354845U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of digital integrated circuit design technology, and in particular to a four-input serial adder and a multi-input serial adder. Background Technology
[0002] In the field of digital integrated circuit design, most operations involve addition, so mature digital integrated circuit systems typically contain a large number of adders. Among these, the adder tree circuit is a common circuit structure that can sum multiple addends. The internal structure of an adder tree circuit generally contains multiple adders, arranged in a tree-like structure from most to least numerous levels. Sequential circuits as pipeline delays can be inserted between each level of the adder tree circuit to improve the final circuit performance. However, existing adder tree circuits have the following drawbacks or limitations:
[0003] 1. Most existing adder tree circuits are parallel adder tree circuits. The data in parallel adder tree circuits is parallel data, and the adders are also parallel adders. On the one hand, as the number of addends and the bit width of addends increase, the resource overhead of parallel adder tree circuits also increases continuously. Parallel computing also increases computational latency, resulting in poor computational performance. On the other hand, once the design of a parallel adder tree circuit is fixed, the maximum bit width that the circuit supports is also fixed, thus limiting the flexibility of the circuit.
[0004] 2. Serial pulse generation in digital systems is one method to address the high hardware overhead of parallel computing. Serial pulse generation outputs each bit of a binary number sequentially on a single signal line according to the clock cycle; different clock cycle numbers can output binary numbers with different bit widths. However, for the accumulation calculation of multi-input serial pulse signals, the general method involves serial-into-parallel conversion, transforming the serial data into parallel data before calculation, ultimately returning to a parallel adder tree circuit, failing to fully utilize the characteristics of serial signals in circuit design.
[0005] 3. The design of circuits such as adders and addition trees requires consideration of carry issues. For example, the output sum of a two-input 8-bit adder is 9 bits, while the output sum of a four-input 8-bit adder is 10 bits. The bit width of a serial pulse signal determines the minimum number of clock cycles for that number. When performing summation calculations on multiple serial pulse signals, if the output cycle count is equal to the input cycle count, an addition overflow problem can easily occur, leading to an incorrect final result. If the input cycle count is equal to the output cycle count, the original calculation cycle will increase, resulting in increased calculation delay. Utility Model Content
[0006] In view of the above-mentioned problems in the prior art, the purpose of this utility model is to provide a four-input serial adder and a multi-input serial adder, which solves the problem of accumulation of multi-input pulse signals. The number of input periods and output periods are equal to the maximum bit width of the input addend, thus ensuring the performance of the adder tree circuit.
[0007] To achieve the above objectives, according to one aspect of the present invention, a four-input serial adder is provided, the device comprising a first input module, a second input module, and a first output module;
[0008] The first input module adds the first input serial data and the second input serial data to obtain the first accumulated data and the first carry data;
[0009] The second input module adds the third input serial data and the fourth input serial data to obtain the second accumulated data and the second carry data;
[0010] The first output module adds the first accumulated data and the second accumulated data to obtain the total accumulated data and the third carry data, and adds the first carry data, the second carry data and the third carry data to obtain the total carry data.
[0011] The total carry data and the total accumulated data are concatenated to form the output of the four-input serial adder.
[0012] Furthermore, the first input module includes a first full adder, a first D flip-flop, and a first selector;
[0013] The first full adder adds the current bit of the first input serial data, the current bit of the second input serial data, and the carry from the previous valid clock cycle in each valid clock cycle to obtain the first accumulated data and the first carry data.
[0014] The input terminals of the first selector are respectively connected to the carry output terminal and the clear data terminal of the first full adder, and the output terminal is connected to the input terminal of the first D flip-flop, which is used to output the clear data or the first carry data to the first D flip-flop according to the enable signal;
[0015] The input of the first D flip-flop is connected to the output of the first selector, and the output is connected to the carry input of the first full adder, for delaying the clear data or the first carry data by one cycle before outputting.
[0016] Furthermore, the second input module includes a second full adder, a second D flip-flop, and a second selector;
[0017] The second full adder adds the current bit of the third input serial data, the current bit of the fourth input serial data, and the carry from the previous valid clock cycle in each valid clock cycle to obtain the second accumulated data and the second carry data.
[0018] The input terminals of the second selector are respectively connected to the carry output terminal and the clear data terminal of the second full adder, and the output terminal is connected to the input terminal of the second D flip-flop, which is used to output the clear data or the second carry data to the second D flip-flop according to the enable signal;
[0019] The input of the second D flip-flop is connected to the output of the second selector, and the output is connected to the carry input of the second full adder, for delaying the clear data or the second carry data by one cycle before outputting.
[0020] Furthermore, the first output module includes a third full adder, a third D flip-flop, a third selector, and a fourth full adder;
[0021] The third full adder adds the current bit of the first accumulated data, the current bit of the second accumulated data, and the carry from the previous valid clock cycle in each valid clock cycle to obtain the total accumulated data and the third carry data.
[0022] The input terminals of the third selector are respectively connected to the carry output terminal and the clear data terminal of the third full adder, and the output terminal is connected to the input terminal of the third D flip-flop, which is used to output the clear data or the third carry data to the third D flip-flop according to the enable signal;
[0023] The input of the third D flip-flop is connected to the output of the third selector, and the output is connected to the carry input of the third full adder, which is used to delay the output of the clear data or the third carry data by one cycle; the fourth full adder adds the first carry data, the second carry data and the third carry data to obtain the total carry data.
[0024] Furthermore, the device also includes a timing module, which includes at least one D flip-flop;
[0025] The D flip-flop is connected to the output terminal corresponding to the signal to be delayed.
[0026] According to another aspect of the present invention, a multi-input serial adder is provided, the device comprising a third input module, a fourth input module, a second output module, and a third output module;
[0027] The third input module adds the first four-channel serial input data to obtain the first total carry data and the first total accumulated data;
[0028] The fourth input module adds the second four-way input serial data to obtain the second total carry data and the second total accumulated data;
[0029] The second output module adds the first total accumulated data and the second total accumulated data to obtain the multi-input accumulated data and the intermediate total carry data;
[0030] The third output module adds the first total carry data, the second total carry data, and the intermediate total carry data to obtain the multi-input carry data;
[0031] The third input module, the fourth input module, and the second output module are four-input serial adders as described in the first aspect of this utility model.
[0032] The multi-input carry data and multi-input accumulated data are concatenated to form the output of the multi-input serial adder.
[0033] Furthermore, it also includes a fifth input module and a sixth input module;
[0034] The fifth input module adds the third and fourth input serial data to obtain the third total carry data and the third total accumulated data;
[0035] The sixth input module adds the fourth four-way input serial data to obtain the fourth total carry data and the fourth total accumulated data;
[0036] The second output module adds the first total accumulated data, the second total accumulated data, the third total accumulated data, and the fourth total accumulated data to obtain the multi-input accumulated data and the intermediate total carry data;
[0037] The third output module adds the first total carry data, the second total carry data, the third total carry data, the fourth total carry data, and the intermediate total carry data to obtain multi-input carry data;
[0038] The fifth and sixth input modules are four-input serial adders as described in the first aspect of this utility model.
[0039] Furthermore, the third output module includes an adder.
[0040] Furthermore, the device also includes a timing module, which includes at least one D flip-flop;
[0041] The D flip-flop is connected to the output terminal corresponding to the signal to be delayed.
[0042] In summary, this utility model provides a four-input serial adder and a multi-input serial adder. The four-input serial adder includes a first input module, a second input module, and a first output module. The first input module adds the first input serial data and the second input serial data to obtain a first accumulated data and a first carry data. The second input module adds the third input serial data and the fourth input serial data to obtain a second accumulated data and a second carry data. The first output module adds the first accumulated data and the second accumulated data to obtain a total accumulated data and a third carry data, and adds the first carry data, the second carry data, and the third carry data to obtain a total carry data. The technical solution provided by this utility model embodiment is that all addends in the serial adder are serial pulse signals, which solves the problem of huge resource consumption caused by parallel addition calculation and solves the maximum bit width limitation of traditional parallel adder trees. Theoretically, the bit width of addends supported by this utility model embodiment is arbitrary. The technical solution provided by this utility model embodiment also solves the problem of accumulation of multiple input pulse signals. Its internal accumulation and summation calculation adopts serial, and the accumulation and carry calculation adopts parallel. The final number of input cycles and output cycles are equal to the maximum bit width of the input addends, which ensures the performance of the serial adder. Attached Figure Description
[0043] Figure 1 This is a structural block diagram of the input serial adder device according to Embodiment 4 of this utility model;
[0044] Figure 2 This is a structural block diagram of the input serial pulse addition tree circuit of Embodiment 2 of this utility model;
[0045] Figure 3 This is a waveform diagram of the input serial pulse addition tree circuit performing calculations according to Embodiment 2 of this utility model;
[0046] Figure 4 This is a structural block diagram of a two-input serial pulse addition tree circuit including a timing module, according to an embodiment of the present invention.
[0047] Figure 5 This is a waveform diagram of the input serial adder device during calculation in Embodiment 4 of this utility model;
[0048] Figure 6 This is a structural block diagram of a four-input serial adder device including a timing module according to an embodiment of the present invention;
[0049] Figure 7 This is a structural block diagram of a multi-input serial adder device of this utility model, taking eight inputs as an example;
[0050] Figure 8 This is a structural block diagram of a multi-input serial adder device of this utility model, using sixteen inputs as an example;
[0051] Figure 9 This is a schematic diagram of the interface of the multi-input (including four-input) serial adder provided in the embodiment of this utility model. Detailed Implementation
[0052] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to specific embodiments and accompanying drawings. It should be understood that these descriptions are merely exemplary and not intended to limit the scope of this utility model. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concept of this utility model.
[0053] It should be noted that, unless otherwise defined, the technical or scientific terms used in one or more embodiments of this utility model should have the ordinary meaning understood by one of ordinary skill in the art to which this utility model pertains. The terms "first," "second," and similar words used in one or more embodiments of this utility model do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0054] The technical solution of this utility model will now be described in detail with reference to the accompanying drawings. An embodiment of this utility model provides a four-input serial adder. Figure 1 The diagram shows a structural block diagram of the input serial adder device according to Embodiment 4 of this utility model. Figure 1As shown, the four-input serial adder includes a first input module 101, a second input module 102, and a first output module 103. The first input module 101 is used to add the first input serial data i_SerialBus[0] and the second input serial data i_SerialBus[1] to obtain the first accumulated data and the first carry data; the second input module 102 is used to add the third input serial data i_SerialBus[2] and the fourth input serial data i_SerialBus[3] to obtain the second accumulated data and the second carry data; the first output module is used to add the first accumulated data and the second accumulated data to obtain the total accumulated data o_SerialSum and the third carry data, and add the first carry data, the second carry data and the third carry data to obtain the total carry data (o_ParallelCarry[0] and o_ParallelCarry[1]); wherein, the total carry data (o_ParallelCarry[0] and o_ParallelCarry[1]) and the total accumulated data o_SerialSum are concatenated to form the output of the four-input serial adder.
[0055] According to some optional embodiments, the first input module 101 includes a first full adder 1011, a first D flip-flop 1012, and a first selector 1013. The first full adder 1011 is used to add the current bit of the first input serial data i_SerialBus[0], the current bit of the second input serial data i_SerialBus[1], and the carry of the previous valid clock cycle in each effective clock cycle to obtain the first accumulated data and the first carry data; the input terminal of the first selector 1013 is connected to the carry output terminal Co and the clear data (e.g., 1'b0) of the first full adder 1011 respectively, and the output terminal is connected to the input terminal D of the first D flip-flop 1012, which is used to output the clear data or the first carry data to the first D flip-flop 1012 according to the enable signal i_SerialEn; the input terminal D of the first D flip-flop 1012 is connected to the output terminal of the first selector 1013, and the output terminal Q is connected to the carry input terminal Ci of the first full adder 1011, which is used to output the clear data or the first carry data to the first full adder 1011 after a delay of one cycle.
[0056] According to some optional embodiments, the second input module 102 includes a second full adder 1021, a second D flip-flop 1022, and a second selector 1023. The second full adder 1021 is used to add the current bit of the third input serial data i_SerialBus[2], the current bit of the fourth input serial data i_SerialBus[3], and the carry of the previous valid clock cycle in each effective clock cycle to obtain the second accumulated data and the second carry data; the input terminal of the second selector 1023 is connected to the carry output terminal Co and the clear data (e.g., 1'b0) of the second full adder 1021 respectively, and the output terminal is connected to the input terminal D of the second D flip-flop 1022, which is used to output the clear data or the second carry data to the second D flip-flop 1022 according to the enable signal i_SerialEn; the input terminal D of the second D flip-flop 1022 is connected to the output terminal of the second selector 1023, and the output terminal Q is connected to the carry input terminal Ci of the second full adder 1021, which is used to output the clear data or the second carry data to the second full adder 1021 after a delay of one cycle.
[0057] According to some optional embodiments, the first output module 103 includes a third full adder 1031, a third D flip-flop 1032, a third selector 1033, and a fourth full adder 1034. The third full adder 1031 is used to add the current bit of the first accumulated data, the current bit of the second accumulated data, and the carry from the previous valid clock cycle in each effective clock cycle to obtain the total accumulated data o_SerialSum and the third carry data. The input of the third selector 1033 is connected to the carry output Co of the third full adder 1031 and the clear data (e.g., 1'b0), and its output is connected to the input D of the third D flip-flop 1032, used to output to the third D flip-flop 1032 according to the enable signal i_SerialEn. The clear data or the third carry data; the input terminal D of the third D flip-flop 1032 is connected to the output terminal of the third selector 1033, and the output terminal Q is connected to the carry input terminal Ci of the third full adder 1031, which is used to delay the clear data or the third carry data by one cycle and output it to the third full adder 1031; the fourth full adder 1034 is used to add the first carry data, the second carry data and the third carry data to obtain the total carry data (o_ParallelCarry[0] and o_ParallelCarry[1]).
[0058] In the fourth embodiment of this utility model, parts of the first input module 101, the second input module 102, and the first output module 103 in the input serial adder can be implemented using an integrated two-input serial pulse adder tree circuit. Figure 2 The diagram shows the block diagram of a two-input serial pulse adder tree circuit, as follows: Figure 2As shown, the two-input serial pulse adder tree circuit includes a full adder 1001, a D flip-flop 1002, and a selector 1003. The full adder 1001 is used to accumulate and output two serial pulse signals. The D flip-flop 1002 is used to register the carry-in or clear data (e.g., 1'b0) of the low-order bit and output it after a delay of one cycle. The selector 1003 is used to provide the clear data or carry-in of the low-order bit to the D flip-flop 1002. This is because when the two-input serial pulse adder tree circuit sums the least significant bit, the carry-in Ci data of the full adder 1001 should be 0. When summing other bits, the carry-in Ci data of the full adder 1001 should come from the carry-in of the previous bit. The interface of the two-input serial pulse adder tree circuit includes: a serial data i_SerialBus[1:0] input interface, each bit representing a serial data; an enable signal i_SerialEn, used to control the internal selector 1003 to switch the output; a clock signal i_Clk; an accumulation and sum result signal o_SerialSum of the two-input serial pulse signals; and a parallel carry result signal o_ParallelCarry of the two-input serial pulse signals.
[0059] Figure 3 The image shows the waveform of the two-input serial pulse adder tree circuit performing calculations, as shown below. Figure 3 As shown, the meanings of each signal are as follows:
[0060] Tadd: Valid time of serial pulse signal (or serial data). For the serial data interface i_SerialBus, each signal is input in the order of least significant bit (LSB) first, followed by most significant bit (MSB).
[0061] Tclr: Serial data end period, at least 1 period. During this period, the enable signal i_SerialEn needs to be pulled low to ensure that when the next set of data begins to be calculated, a carry-in of 0 is provided to the least significant bit.
[0062] Tsum: The effective period of the accumulated sum data o_SerialSum, which is the same as the number of periods of the input serial data i_SerialBus.
[0063] Tcar: The effective period of the carry data o_ParallelCarry, which is 1 period. The carry data is parallel.
[0064] like Figure 3As shown, the two-input serial pulse adder tree circuit completes two addition calculations of serial data. According to the enable signal i_SerialEn, the input serial data i_SerialBus[0] and i_SerialBus[1] input two sets of addends within the Tadd period. The binary numbers of the first set of addends are 4'b1010 and 4'b1101, which correspond to the decimal numbers 10 and 13 respectively. The binary numbers of the second set of addends are 3'b111 and 3'b111, which correspond to the decimal numbers 7 and 7 respectively. According to the cumulative sum data o_SerialSum and the carry data o_ParallelCarry, the two sets of binary numbers are 5'b10111 and 4'b1110, which correspond to the decimal numbers 23 and 14 respectively, satisfying the addition operations 10+13=23 and 7+7=14. The input bit width of the two-input serial pulse adder tree circuit can be dynamically adjusted.
[0065] To increase computational latency and improve computational performance, timing modules can also be added to the two-input serial pulse addition tree circuit. Figure 4 The diagram shows a block diagram of a two-input serial pulse adder tree circuit including a timing module, as shown below. Figure 4 As shown, the configuration of the full adder 1001, D flip-flop 1002, and selector 1003 is the same as that of the two-input serial pulse addition tree circuit in the above embodiment. The two output terminals S and Co of the full adder 1001 are respectively connected to timing modules composed of D flip-flops 1004 and 1005. In terms of timing, for each additional timing module added inside the two-input serial pulse addition tree circuit, the output accumulated sum data o_SerialSum and carry data o_ParallelCarry are delayed by one clock cycle. Therefore... Figure 4 The output of the two-input serial pulse adder tree circuit, including the timing module, will be delayed by one clock cycle.
[0066] Figure 5 The diagram shows the waveform of the input serial adder in Embodiment 4 of this utility model during calculation. Figure 5 As shown, the meanings of each signal are as follows:
[0067] Tadd: Valid time of serial data. Each signal of the serial data i_SerialBus inputs data in the order of least significant bit (LSB) first, most significant bit (MSB) last.
[0068] Tclr: Serial data end period, at least 1 clock cycle. During this period, the enable signal i_SerialEn needs to be pulled low to ensure that when the next set of serial data begins to be calculated, a carry-in of 0 is provided to the least significant bit.
[0069] Tsum: The effective number of cycles of the total accumulated data o_SerialSum. This number of cycles is the same as the number of cycles of the input serial data i_SerialBus. If the number of cycles of the four input serial data i_SerialBus[3:0] are different, the number of cycles of Tsum is equal to the maximum number of cycles in the input serial data.
[0070] Tcar: The effective period of the total carry data o_ParallelCarry, which is 1 clock cycle. The total carry data is parallel, and the total carry data and the total accumulated data are concatenated to form the output of the four-input serial adder.
[0071] like Figure 5 As shown, the four-input serial adder completes the addition calculation of two input serial data. According to the input serial data i_SerilaBus, the first addends are 2'b10, 2'b01, 2'b11, and 2'b00, which correspond to the decimal numbers 2, 1, 3, and 0, respectively. The second addends are 4'b1100, 4'b0100, 4'b1111, and 4'b1001, which correspond to the decimal numbers 12, 4, 15, and 9, respectively. Based on the total sum data o_SerialSum, the bit width of the total carry data o_ParallelCarry becomes [1:0]. At this time, the two total sum data o_SerialSum are 2'b10 and 4'b1000, and the two total carry data o_ParallelCarry are 1'b1 and 2'b10. The two sets of binary numbers formed by concatenation are 3'b110 and 6'b101000, which correspond to the decimal numbers 6 and 40 respectively.
[0072] According to some alternative embodiments, the four-input serial adder may further include a timing module, which includes at least one D flip-flop connected to the output terminal corresponding to the signal to be delayed. Figure 6 The diagram shows a block diagram of a four-input serial adder including a timing module, as shown below. Figure 6As shown, the configuration of the first input module 101, the second input module 102, and the first output module 103 of the four-input serial adder is the same as that provided in the above embodiment of the present invention. In addition, a first timing module 104 is provided at each output terminal of the first input module 101, the second input module 102, and the enable signal i_SerialEn as the first stage of the pipeline timing unit, including D flip-flops 1041, 1042, 1043, 1044, and 1045; a second timing module 105 is provided at each output terminal of the first output module 103 as the second stage of the pipeline timing unit, including D flip-flops 1051, 1052, and 1053. Therefore, the output of the four-input serial adder will be delayed by two clock cycles.
[0073] According to another aspect of the present invention, a multi-input serial adder is provided, comprising a third input module, a fourth input module, a second output module, and a third output module; the third input module is used to add first four-channel input serial data to obtain a first total carry data and a first total accumulated data; the fourth input module is used to add second four-channel input serial data to obtain a second total carry data and a second total accumulated data; the second output module is used to add the first total accumulated data and the second total accumulated data to obtain multi-input accumulated data and intermediate total carry data; the third output module is used to add the first total carry data, the second total carry data, and the intermediate total carry data to obtain multi-input carry data; wherein, the third input module, the fourth input module, and the second output module are, for example, a four-input serial adder as provided in the above embodiments of the present invention, and the multi-input carry data and the multi-input accumulated data are concatenated to form the output of the multi-input serial adder.
[0074] Figure 7 The diagram shows a block diagram of a multi-input serial adder with eight inputs as an example. Figure 7As shown, the multi-input serial adder includes a third input module 201, a fourth input module 202, a second output module 203, and a third output module 204. The third input module 201 adds the first four-channel input serial data i_SerialBus[3:0] to obtain a first total carry data and a first total accumulated data; the fourth input module 202 adds the second four-channel input serial data i_SerialBus[7:4] to obtain a second total carry data and a second total accumulated data; the second output module 203 adds the first total accumulated data and the second total accumulated data to obtain multi-input accumulated data o_SerialSum and intermediate total carry data; the third output module 204 adds the first total carry data, the second total carry data, and the intermediate total carry data to obtain multi-input carry data o_ParallelCarry[2:0]. The multi-input carry data o_ParallelCarry[2:0] and the multi-input accumulated data o_SerialSum are concatenated to form the output of the multi-input serial adder. The third input module 201, the fourth input module 202, and the second output module 203 can all adopt the four-input serial adder device provided in the above embodiments of this utility model. For specific structures, please refer to... Figure 1 The block diagram shown illustrates that, since the second output module 203 only has two input serial data channels, other unused input serial data can be padded with zeros. A more preferred example is the two-input serial pulse addition tree circuit provided in the above embodiments of this invention. For a specific structure, please refer to [example diagram]. Figure 4 The structural block diagram is shown. The third output module 204 includes an adder. In this embodiment, the third output module 204 is constructed using a two-input 2-bit wide adder 2041 and a two-input mixed bit-width adder 2042, depending on the number of input and output bits. The adder 2041 and the adder 2042 can be constructed as full adders and / or half adders.
[0075] Figure 8 The diagram shows a block diagram of a multi-input serial adder with sixteen inputs as an example. Figure 8As shown, the multi-input serial adder includes a third input module 301, a fourth input module 302, a fifth input module 303, a sixth input module 304, a second output module 305, and a third output module 306. The third input module 301 is used to add the first four-channel input serial data i_SerialBus[3:0] to obtain a first total carry data and a first total accumulated data; the fourth input module 302 is used to add the second four-channel input serial data i_SerialBus[7:4] to obtain a second total carry data and a second total accumulated data; the fifth input module 303 is used to add the third four-channel input serial data i_SerialBus[11:8] to obtain a third total carry data and a third total accumulated data; and the sixth input module 304 is used to add the fourth four-channel input serial data i_SerialBus[15:12] to obtain a fourth total carry data and a fourth total accumulated data. The second output module 305 is used to add the first total accumulated data, the second total accumulated data, the third total accumulated data, and the fourth total accumulated data to obtain multi-input accumulated data o_SerialSum and intermediate total carry data; the third output module 306 is used to add the first total carry data, the second total carry data, the third total carry data, the fourth total carry data, and the intermediate total carry data to obtain multi-input carry data o_ParallelCarry[3:0]. The third input module 301, the fourth input module 302, the fifth input module 303, the sixth input module 304, and the second output module 305 can all adopt the four-input serial adder device provided in the above embodiment. For specific structures, please refer to the following. Figure 1 The structural block diagram is shown. The third output module 306 includes adders. In this embodiment, the third output module 306 is constructed using two-input 2-bit wide adders 3061 and 3062, two-input 3-bit wide adders 3063, and two-input mixed-bit wide adders 3064, depending on the number of input and output bits. Adders 3061, 3062, 3063, and 3064 can all be constructed using full adders and / or half adders.
[0076] According to some optional embodiments, the multi-input serial adder further includes a timing module, which includes at least one D flip-flop. The D flip-flop is connected to the output terminal corresponding to the signal to be delayed. The timing module is configured in the same way as the four-input serial adder described above, and its repeated description will be omitted here.
[0077] Figure 9 This diagram illustrates the interface of a multi-input (including four-input) serial adder provided in an embodiment of the present invention. Figure 9As shown, the interface includes a serial data interface i_SerialBus[N-1:0], an enable signal interface i_SerialEn, a clock signal interface i_Clk, a multi-input accumulator data interface o_SerialSum, and a multi-input carry data interface o_ParallelCarry[log2N-1:0]. The interface bit width is calculated based on the value of N, where N represents the number of bits of input serial data. The internal structure construction rules of the multi-input (including four-input) serial adder are as shown in the above embodiments of this utility model.
[0078] In summary, this utility model provides a four-input serial adder and a multi-input serial adder. The four-input serial adder includes a first input module, a second input module, and a first output module. The first input module adds the first input serial data and the second input serial data to obtain a first accumulated data and a first carry data. The second input module adds the third input serial data and the fourth input serial data to obtain a second accumulated data and a second carry data. The first output module adds the first accumulated data and the second accumulated data to obtain a total accumulated data and a third carry data, and adds the first carry data, the second carry data, and the third carry data to obtain a total carry data. The technical solution provided by this embodiment of the invention addresses the problem of excessive resource consumption in parallel addition calculations by using serial pulse signals for all addends in the serial adder. It also overcomes the maximum bit width limitation of traditional parallel adder trees, theoretically allowing for arbitrary addend bit widths. Furthermore, the solution solves the problem of accumulating multiple input pulse signals. Internally, the summation calculation is serial, while the carry calculation is parallel. The final input and output cycle counts are equal to the maximum bit width of the input addends, ensuring the performance of the serial adder. This solution effectively saves hardware resources; for example, the area of a sixteen-input serial adder is approximately 30% of the area of a conventional parallel sixteen-input 8-bit wide adder tree circuit. This solution also supports addition with arbitrary addend bit widths. While a parallel sixteen-input 8-bit wide adder tree circuit supports a maximum addend data bit width of only 8 bits, the sixteen-input serial adder provided by this embodiment can input 16 bits or more.
[0079] It should be understood that the specific embodiments described above are merely illustrative or explanatory of the principles of this utility model and do not constitute a limitation thereof. Therefore, any modifications, equivalent substitutions, improvements, etc., made without departing from the spirit and scope of this utility model should be included within its protection scope. Furthermore, the appended claims are intended to cover all variations and modifications falling within the scope and boundaries of the appended claims, or equivalent forms of such scope and boundaries.
Claims
1. A four-input serial adder, characterized in that, The device includes a first input module, a second input module, and a first output module; The first input module adds the first input serial data and the second input serial data to obtain the first accumulated data and the first carry data; The second input module adds the third input serial data and the fourth input serial data to obtain the second accumulated data and the second carry data; The first output module adds the first accumulated data and the second accumulated data to obtain the total accumulated data and the third carry data, and adds the first carry data, the second carry data and the third carry data to obtain the total carry data. The total carry data and the total accumulated data are concatenated to form the output of the four-input serial adder.
2. The apparatus according to claim 1, characterized in that, The first input module includes a first full adder, a first D flip-flop, and a first selector; The first full adder adds the current bit of the first input serial data, the current bit of the second input serial data, and the carry from the previous valid clock cycle in each valid clock cycle to obtain the first accumulated data and the first carry data. The input terminals of the first selector are respectively connected to the carry output terminal and the clear data terminal of the first full adder, and the output terminal is connected to the input terminal of the first D flip-flop, which is used to output the clear data or the first carry data to the first D flip-flop according to the enable signal; The input of the first D flip-flop is connected to the output of the first selector, and the output is connected to the carry input of the first full adder, for delaying the clear data or the first carry data by one cycle before outputting.
3. The apparatus according to claim 2, characterized in that, The second input module includes a second full adder, a second D flip-flop, and a second selector; The second full adder adds the current bit of the third input serial data, the current bit of the fourth input serial data, and the carry from the previous valid clock cycle in each valid clock cycle to obtain the second accumulated data and the second carry data. The input terminals of the second selector are respectively connected to the carry output terminal and the clear data terminal of the second full adder, and the output terminal is connected to the input terminal of the second D flip-flop, which is used to output the clear data or the second carry data to the second D flip-flop according to the enable signal; The input of the second D flip-flop is connected to the output of the second selector, and the output is connected to the carry input of the second full adder, for delaying the clear data or the second carry data by one cycle before outputting.
4. The apparatus according to claim 3, characterized in that, The first output module includes a third full adder, a third D flip-flop, a third selector, and a fourth full adder; The third full adder adds the current bit of the first accumulated data, the current bit of the second accumulated data, and the carry from the previous valid clock cycle in each valid clock cycle to obtain the total accumulated data and the third carry data. The input terminals of the third selector are respectively connected to the carry output terminal and the clear data terminal of the third full adder, and the output terminal is connected to the input terminal of the third D flip-flop, which is used to output the clear data or the third carry data to the third D flip-flop according to the enable signal; The input of the third D flip-flop is connected to the output of the third selector, and the output is connected to the carry input of the third full adder, which is used to delay the output of the clear data or the third carry data by one cycle; the fourth full adder adds the first carry data, the second carry data and the third carry data to obtain the total carry data.
5. The apparatus according to any one of claims 1-4, characterized in that, The device further includes a timing module, which includes at least one D flip-flop; The D flip-flop is connected to the output terminal corresponding to the signal to be delayed.
6. A multi-input serial adder, characterized in that, The device includes a third input module, a fourth input module, a second output module, and a third output module; The third input module adds the first four-channel serial input data to obtain the first total carry data and the first total accumulated data; The fourth input module adds the second four-way input serial data to obtain the second total carry data and the second total accumulated data; The second output module adds the first total accumulated data and the second total accumulated data to obtain the multi-input accumulated data and the intermediate total carry data; The third output module adds the first total carry data, the second total carry data, and the intermediate total carry data to obtain the multi-input carry data; Wherein, the third input module, the fourth input module and the second output module are four-input serial adders as described in any one of claims 1-5; The multi-input carry data and multi-input accumulated data are concatenated to form the output of the multi-input serial adder.
7. The apparatus according to claim 6, characterized in that, It also includes a fifth input module and a sixth input module; The fifth input module adds the third and fourth input serial data to obtain the third total carry data and the third total accumulated data; The sixth input module adds the fourth four-way input serial data to obtain the fourth total carry data and the fourth total accumulated data; The second output module adds the first total accumulated data, the second total accumulated data, the third total accumulated data, and the fourth total accumulated data to obtain the multi-input accumulated data and the intermediate total carry data; The third output module adds the first total carry data, the second total carry data, the third total carry data, the fourth total carry data, and the intermediate total carry data to obtain multi-input carry data; The fifth input module and the sixth input module are four-input serial adders as described in any one of claims 1-5.
8. The apparatus according to claim 7, characterized in that, The third output module includes an adder.
9. The apparatus according to any one of claims 6-8, characterized in that, The device further includes a timing module, which includes at least one D flip-flop; The D flip-flop is connected to the output terminal corresponding to the signal to be delayed.