A high-integration low-level control system
By employing a highly integrated low-level control system in the particle accelerator and integrating radio frequency and digital signal processing using an RFSoC chip, the problems of large size, high power consumption, and long latency of traditional systems are solved, achieving miniaturization, low power consumption, and low latency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- CHINA SPALLATION NEUTRON SOURCE SCI CENT
- Filing Date
- 2025-01-13
- Publication Date
- 2026-06-16
AI Technical Summary
Traditional low-level control systems are large in size, consume a lot of power, and have long delays, which limits the performance improvement of particle accelerators.
It adopts a highly integrated low-level control system, including an RF transceiver integrated chip and a digital signal processing module, integrating an RF analog-to-digital converter and an RF digital-to-analog converter, and using an RFSoC chip to achieve high sampling rate and real-time signal processing.
It achieves miniaturization, low power consumption, and low latency of the low-level control system, improving system response speed and reliability, and is suitable for particle accelerators with various frequency requirements.
Smart Images
Figure CN224366333U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of accelerator technology, and more specifically to a highly integrated low-level control system. Background Technology
[0002] Particle accelerators are devices that use electromagnetic fields to accelerate charged particles. They can accelerate charged particles such as electrons, protons, and other particles. A low-level control system is an essential component of a particle accelerator. It suppresses amplitude and phase fluctuations of signals within the accelerator cavity through feedback mechanisms. Therefore, precise control of the radio frequency signals within the cavity is crucial. Traditional low-level control systems suffer from problems such as large size, high power consumption, and long delays, limiting performance improvements in particle accelerators. Therefore, a highly integrated low-level control system is urgently needed to address these issues. Utility Model Content
[0003] This application provides a highly integrated low-level control system, which has advantages such as miniaturization, low latency, and high integration. The technical solution is as follows:
[0004] On the one hand, a highly integrated low-level control system is provided for a particle accelerator, the particle accelerator including a cavity; characterized in that the low-level control system includes: an integrated radio frequency transceiver chip and a digital signal processing module;
[0005] The radio frequency transceiver integrated chip includes a radio frequency analog-to-digital conversion module and a radio frequency digital-to-analog conversion module;
[0006] The radio frequency analog-to-digital conversion module is connected to the cavity of the particle accelerator and the digital signal processing module, respectively. The radio frequency analog-to-digital conversion module is used to receive a first radio frequency signal from the cavity, sample the first radio frequency signal, and convert the sampled first radio frequency signal into a digital signal and then send it to the digital signal processing module.
[0007] The digital signal processing module is also connected to the radio frequency digital-to-analog converter module. The digital signal processing module is used to perform logical operations on the received digital signal to obtain the target signal, and send the target signal to the radio frequency digital-to-analog converter module.
[0008] The digital signal processing module is also used to acquire target data and process the target data to obtain display data for display. The target data is used to indicate the processing progress of the digital signal by the digital signal processing module, or to indicate relevant information of the target signal.
[0009] The radio frequency digital-to-analog converter module is also connected to the cavity of the particle accelerator. The radio frequency digital-to-analog converter module is used to convert the received target signal into a second radio frequency signal and send the second radio frequency signal to the cavity to control the amplitude and / or phase of the signal in the cavity.
[0010] Optionally, the radio frequency transceiver integrated chip includes an RFSoC (Radio Frequency System on a Chip) chip.
[0011] Optionally, the digital signal processing module is integrated on the RFSoC chip.
[0012] Optionally, the radio frequency analog-to-digital conversion module includes a radio frequency analog-to-digital converter, the radio frequency digital-to-analog conversion module includes a radio frequency digital-to-analog converter, and the digital signal processing module includes an FPGA chip;
[0013] The RFSoC chip includes the radio frequency analog-to-digital converter, the radio frequency digital-to-analog converter, and the FPGA chip;
[0014] The radio frequency analog-to-digital converter is connected to the cavity of the particle accelerator and the FPGA chip;
[0015] The FPGA chip is also connected to the radio frequency digital-to-analog converter;
[0016] The radio frequency digital-to-analog converter is also connected to the cavity of the particle accelerator.
[0017] Optionally, the FPGA chip includes a logic unit and a processing unit;
[0018] The logic unit and the processing unit are connected;
[0019] The processing unit is used to send control signals to the logic unit, and the control signals are used to indicate the mode of the logic operation processing;
[0020] The logic unit is used to perform logical operations on the received digital signal according to the control signal after receiving the control signal, to obtain the target signal, and to send the target signal to the radio frequency digital-to-analog converter.
[0021] The processing unit is used to acquire target data, process the target data to obtain display data, and send the display data to the target device, which is a device that needs to know relevant information.
[0022] Optionally, the processing unit includes an ARM (Advanced RISC Machine) processor.
[0023] Optionally, the low-level control system further includes a power amplification module;
[0024] The power amplification module is connected to the radio frequency digital-to-analog converter module and the cavity, respectively. The power amplification module is used to amplify the second radio frequency signal sent by the radio frequency digital-to-analog converter module and send the amplified second radio frequency signal to the cavity to establish an electromagnetic field in the cavity and realize the acceleration effect of the particle accelerator on the beam in the cavity.
[0025] Optionally, the radio frequency analog-to-digital converter includes any one or more of an analog-to-digital converter, a digital attenuator, a mixer, a calibrator, and a decimation filter;
[0026] The radio frequency digital-to-analog converter includes any one or more of a digital-to-analog converter, a mixer, an interpolator, and an amplifier.
[0027] Optionally, the radio frequency analog-to-digital converter includes an analog-to-digital converter, a digital attenuator, a mixer, a calibrator, and a decimation filter;
[0028] The analog-to-digital converter is connected to the digital attenuator and the calibrator respectively, the calibrator is also connected to the mixer, and the mixer is also connected to the decimation filter.
[0029] The radio frequency digital-to-analog converter includes a digital-to-analog converter, a mixer, an interpolator, and an amplifier;
[0030] The digital-to-analog converter is connected to the mixer and the amplifier, respectively, and the mixer is also connected to the interpolator.
[0031] Optionally, the low-level control system further includes a memory module, a trigger module, and a clock management module;
[0032] The memory module is connected to the digital signal processing module and is used to preset and store the waveforms required by the cavity of the particle accelerator in multiple working modes.
[0033] The triggering module is connected to the digital signal processing module and is used to receive trigger signals to enable the cavity to switch between the multiple working modes;
[0034] The clock management module is connected to the digital signal processing module and the radio frequency analog-to-digital converter respectively, and is used to set the sampling clock signal required by the cavity and the working clock signal required by the digital signal processing module.
[0035] The technical solution provided in this application can bring at least the following beneficial effects:
[0036] The low-level control system provided in this application includes an RF transceiver integrated chip and a digital signal processing module; the RF transceiver integrated chip integrates an RF analog-to-digital converter and an RF digital-to-analog converter; since the RF transceiver integrated chip can operate at a high sampling rate, the RF transceiver integrated chip of this application can directly sample and process the first RF signal, and the RF transceiver integrated chip can capture and process RF signals in real time, thereby improving the system response speed and reducing the system delay. Attached Figure Description
[0037] Figure 1 This is a schematic diagram of the structure of a particle accelerator provided in an embodiment of this application;
[0038] Figure 2 This is a schematic diagram of another particle accelerator provided in an embodiment of this application;
[0039] Figure 3 This is a schematic diagram of another particle accelerator provided in the embodiments of this application;
[0040] Figure 4 This is a schematic diagram of another particle accelerator provided in the embodiments of this application;
[0041] Figure 5 This is a schematic diagram of another particle accelerator provided in the embodiments of this application;
[0042] Figure 6 This is a schematic diagram of another particle accelerator provided in the embodiments of this application;
[0043] Figure 7 This is a schematic diagram of another particle accelerator provided in the embodiments of this application;
[0044] Figure 8 This is a schematic diagram of the structure of a radio frequency analog-to-digital converter provided in an embodiment of this application;
[0045] Figure 9 This is a schematic diagram of the structure of a radio frequency digital-to-analog converter provided in an embodiment of this application. Detailed Implementation
[0046] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. Similar elements in different embodiments are referred to by related similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of the present application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to the present application are not shown or described in the specification. This is to avoid obscuring the core parts of the present application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.
[0047] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments, and the operational steps involved in each embodiment can also be rearranged or adjusted in a manner that is obvious to those skilled in the art. Therefore, the specification and drawings are only for clearly describing a particular embodiment and do not imply that they represent the necessary components and / or order.
[0048] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).
[0049] RFSoC is a highly integrated solution that integrates radio frequency signal processing and digital signal processing on a single chip, offering advantages such as miniaturization, low power consumption, low latency, high performance, and short design cycles. This integration not only reduces board area but also lowers inter-board communication latency and product power consumption, thus providing a highly efficient and energy-saving solution.
[0050] Based on this, embodiments of this application provide a highly integrated low-level control system. This low-level control system includes an RF transceiver integrated chip, and RF signal processing is performed on the RF transceiver integrated chip, such as an RFSoC chip. Furthermore, when the RF transceiver integrated chip is an RFSoC chip, digital signal processing can also be performed on the RFSoC chip. In addition, since the RF transceiver integrated chip integrates an RF analog-to-digital converter and an RF digital-to-analog converter, the low-level control system provided by embodiments of this application has advantages such as miniaturization, low power consumption, low latency, and high integration.
[0051] The technical solution of this application will be described in detail below with reference to the embodiments.
[0052] Figure 1This is a schematic diagram of a particle accelerator provided in an embodiment of this application. The particle accelerator includes a highly integrated low-level control system provided in this embodiment. Please refer to... Figure 1 The low-level control system includes an RF transceiver integrated chip 1 and a digital signal processing module 2. The RF transceiver integrated chip 1 includes an RF analog-to-digital converter module 11 and an RF digital-to-analog converter module 12. The RF analog-to-digital converter module 11 is connected to both the cavity of the particle accelerator and the digital signal processing module 2. The RF analog-to-digital converter module 11 receives a first RF signal from the cavity, samples the first RF signal, converts the sampled first RF signal into a digital signal, and sends it to the digital signal processing module 2. The digital signal processing module 2 is also connected to the RF digital-to-analog converter module 12. The digital signal processing module 2 performs logical operations on the received digital signal to obtain a target signal and sends the target signal to the RF digital-to-analog converter module 12. The digital signal processing module 2 also acquires target data and processes the target data to obtain display data for display. The target data indicates the processing progress of the digital signal processing module 2 or indicates relevant information about the target signal. The radio frequency digital-to-analog converter module 12 is also connected to the cavity of the particle accelerator. The radio frequency digital-to-analog converter module 12 is used to convert the received target signal into a second radio frequency signal and send the second radio frequency signal to the cavity to control the amplitude and / or phase of the signal in the cavity.
[0053] Because the RF analog-to-digital converter module is connected to the cavity of the particle accelerator, it can receive a first RF signal from the cavity. This first RF signal can be a cavity field (cavity probe signal) or a positive and negative signal of the feed power, etc.
[0054] After receiving the first radio frequency (RF) signal, the RF analog-to-digital (ADC) module can sample it. After sampling, it can process the sampled RF signal to convert it into a digital signal. Since the RF ADC module is also connected to a digital signal processing (DSP) module, after converting the sampled RF signal into a digital signal, it can send this digital signal to the DSP module. The DSP module can then perform logical operations on this digital signal to obtain the target signal. The target signal refers to the signal that the DSP module needs to obtain after performing logical operations on the digital signal.
[0055] Furthermore, the digital signal processing module can acquire target data and process it to obtain display data for display purposes. When the target data indicates the processing progress of the digital signal by the digital signal processing module, the module can process the target signal to obtain display data that shows the processing progress. Thus, technicians can remotely log in to access this display data and understand the processing progress of the digital signal. When the target data indicates relevant information about the target signal, the module can process the target signal to obtain display data that shows that relevant information. Thus, technicians can remotely log in to access this display data and understand the relevant information about the target signal.
[0056] It should be noted that the above description is based on the target data indicating the processing progress of the digital signal by the digital signal processing module or related information used to indicate the target signal. Alternatively, in application, the target data can also be used to indicate other information, which is not limited in this application embodiment.
[0057] The digital signal processing module is also connected to the radio frequency digital-to-analog converter module. Therefore, the digital signal processing module can send the processed target signal to the radio frequency digital-to-analog converter module. In this way, the radio frequency digital-to-analog converter module can continue to process the target signal to convert it into a second radio frequency signal.
[0058] The radio frequency digital-to-analog converter module is also connected to the cavity of the particle accelerator. Therefore, after the radio frequency digital-to-analog converter module obtains the second radio frequency signal, it can also send the second radio frequency signal to the cavity, thereby realizing the amplitude and / or phase control of the signal in the cavity.
[0059] As described above, the first radio frequency (RF) signal enters the low-level control system through the particle accelerator cavity. This control system then processes the RF signal to obtain a second RF signal, which is then sent back into the cavity. In other words, this is a feedback process. The low-level control system subsequently receives the second RF signal from the cavity, processes it to obtain a third RF signal, and then sends this third signal back to the particle accelerator cavity. This allows for precise control and processing of the RF signal, enabling the particle accelerator to precisely control the amplitude and / or phase of the signal within the cavity.
[0060] It should be noted that this application only improves the hardware portion of the existing low-level control system; that is, this application does not improve any software / algorithm / control logic portion of the existing low-level control system. The specific data processing flows within the aforementioned RF transceiver integrated chip 1 and digital signal processing module 2 all employ existing technologies in the field. The above description of the processing flows is merely illustrative and does not limit the scope of the processing flow.
[0061] In some embodiments, please refer to Figure 2 The radio frequency transceiver integrated chip 1 includes an RFSoC chip 13.
[0062] An RFSoC chip is a system-on-a-chip that integrates radio frequency (RF) functions. It combines analog and digital signal processing capabilities on a single chip, aiming to simplify the design and implementation of wireless communication systems. RFSoC chips are typically used in applications requiring high performance and high integration, such as 5G communications, satellite communications, radar systems, and wireless equipment.
[0063] RFSoC chips feature high integration, combining multiple RF functions and a digital signal processor onto a single chip, reducing system complexity and size. RFSoC chips also offer excellent flexibility, supporting various communication standards and frequency bands and can be configured via software to suit different application requirements. Furthermore, RFSoC chips provide high-bandwidth and low-latency signal processing capabilities, making them suitable for handling complex RF signals with high performance. Moreover, due to their integrated design and optimized power management, RFSoC chips can deliver high performance while reducing energy consumption.
[0064] Therefore, applying RFSoC chips to low-level control systems can not only reduce the size of the low-level control system, but also reduce power consumption and latency, thereby improving the reliability and stability of the low-level control system.
[0065] In some embodiments, please refer to Figure 3 The digital signal processing module 2 is integrated onto the RFSoC chip 13. This means that the RFSoC chip can also include a digital signal processing module, thus further increasing the integration level of the RFSoC.
[0066] In some embodiments, please refer to Figure 4The RF analog-to-digital converter module 11 includes an RF analog-to-digital converter 111, the RF digital-to-analog converter module 12 includes an RF digital-to-analog converter 121, and the digital signal processing module 2 includes an FPGA (Field-Programmable Gate Array) chip 21. The RFSoC chip 13 includes an RF analog-to-digital converter (RF ADC) 111, an RF digital-to-analog converter (RF DAC) 121, and an FPGA chip 21. The RF ADC 111 is connected to the particle accelerator cavity and the FPGA chip 21. The FPGA chip 21 is also connected to the RF digital-to-analog converter 121, and the RF digital-to-analog converter 112 is also connected to the particle accelerator cavity.
[0067] In other words, an RFSoC chip can integrate an RF analog-to-digital converter (ADC), an RF digital-to-analog converter (DAC), and an FPGA chip. The ADC is connected to the cavity of the particle accelerator, thus receiving and processing a first RF signal from the cavity to convert it into a digital signal. The ADC is also connected to the FPGA chip, allowing it to send the resulting digital signal to the FPGA for further processing to obtain the target signal. The FPGA is also connected to the DAC, enabling it to send the target signal to the DAC for conversion into a second RF signal. Finally, the ADC, after receiving the second RF signal, can send it back to the particle accelerator cavity, thereby controlling the amplitude and / or phase of the signal within the cavity.
[0068] An RF analog-to-digital converter (ADC) is a device specifically designed to convert radio frequency (RF) signals into digital signals. Compared to traditional ADCs, RF ADCs can handle higher frequency signals. Furthermore, RF ADCs have a very high sampling rate, meeting the requirement of directly sampling the first RF signal. In other words, because the sampling rate of an RF ADC is much higher than that of a traditional ADC, it can capture the high-frequency components of the RF signal. The RF ADC can directly sample the first RF signal without first down-converting it to an intermediate frequency (IF) or baseband. Thus, low-level control systems no longer require complex analog down-conversion devices; instead, they can directly sample the first RF signal, thereby simplifying their architecture.
[0069] After sampling the first radio frequency (RF) signal, the RF analog-to-digital converter (ADC) needs to quantize it. During quantization, the continuous RF signal is converted into a discrete digital signal. The RF ADC then sends this digital signal to the FPGA chip for subsequent processing. Because the RF ADC has high resolution, it ensures the accuracy of the digital signal.
[0070] After receiving the digital signal, the FPGA chip can perform corresponding logical operations on the digital signal according to the control requirements of the low-level control system for the amplitude and / or phase of the signal in the cavity, thereby obtaining the target signal and sending the target signal to the radio frequency digital-to-analog converter.
[0071] Since the target signal is a digital signal, the RF digital-to-analog converter needs to convert the target signal line into an analog signal after receiving it; that is, to convert discrete digital values into continuous voltage or current signals. Furthermore, since the obtained analog signal may be a baseband signal or an intermediate frequency (IF) signal, rather than an RF signal, it is necessary to shift the analog signal into the RF range; that is, to convert the baseband or IF signal into a higher-frequency RF signal, thereby obtaining a second RF signal.
[0072] In some embodiments, please refer to Figure 5 The FPGA chip 21 includes a logic unit 211 and a processing unit 212; the logic unit 211 and the processing unit 212 are connected. The processing unit 212 is used to send control signals to the logic unit 211, which are used to indicate the mode of logical operation processing; after receiving the control signal, the logic unit 211 is used to perform logical operation processing on the received digital signal according to the control signal to obtain the target signal, and send the target signal to the radio frequency digital-to-analog converter 121; the processing unit 212 is also used to acquire target data, process the target data to obtain display data, and send the display data to the target device, which is a device that needs to know relevant information.
[0073] In other words, an FPGA chip includes a logic unit (PL) and a processing unit (PS). Since the FPGA chip is integrated onto an RFSoC chip, the RFSoC chip integrates both the PL and PS. In the RFSoC architecture, the PS is primarily responsible for running the operating system and application programs, while the PL is used to implement high-speed digital signal processing functions. Therefore, the PS can send control signals to the PL to instruct the PL on how to perform logical operations on the digital signal to obtain the target signal. The PL can then process the digital signal according to the control signals to obtain the target signal, thus achieving precise control over the digital signal.
[0074] In some embodiments, data transfer between the logic unit and the processing unit can be performed via DMA (Direct Memory Access).
[0075] As described above, technicians can obtain relevant display data through remote login. After the processing unit processes the target data to obtain the display data, it needs to send the display data to the device logged in by the technician, i.e., the target device, so that the technician can access the relevant information through the target device.
[0076] In some embodiments, please refer to Figure 6 The processing unit 212 includes an ARM processor 2121.
[0077] Since the processing unit includes an ARM processor, it can be concluded that the RFSoC chip also integrates an ARM processor. Because the ARM processor can run an operating system, it enables human-computer interaction functions, allowing technicians to better understand relevant information.
[0078] Moreover, since the low-level control system uses an RFSoC chip that integrates an ARM processor, there is no need to equip the system with a dedicated CPU for high-level data processing and algorithm implementation. Compared with other existing low-level control systems that may require a dedicated CPU for high-level data processing and algorithm implementation, the low-level control system provided in this application embodiment can reduce development difficulty and shorten the design cycle.
[0079] It should be noted that the above explanation focuses on the application of RFSoC chips in low-level control systems. Alternatively, RFSoC chips can also be applied to BPM (Beam Position Monitor) probes in particle accelerators. That is, the RFSoC chip can be connected to the BPM probe, enabling high-energy physics applications such as beam measurement. Furthermore, RFSoC chips can also be used in the development and design of interlocking protection, tuning control, and other related functions.
[0080] In some embodiments, please refer to Figure 7 The low-level control system also includes a power amplification module 3. The power amplification module 3 is connected to the radio frequency digital-to-analog converter module 12 and the cavity, respectively. The power amplification module 3 is used to amplify the second radio frequency signal sent by the radio frequency digital-to-analog converter module 12 and send the amplified second radio frequency signal to the cavity to establish an electromagnetic field in the cavity, thereby realizing the acceleration effect of the particle accelerator on the beam in the cavity.
[0081] It should be noted that technicians can determine the specific model of the power amplifier module according to actual needs, and this application embodiment does not impose any restrictions on this.
[0082] In some embodiments, the RF analog-to-digital converter 111 includes one or more of an analog-to-digital converter, a digital attenuator, a mixer, a calibrator, and a decimation filter; the RF digital-to-analog converter 121 includes one or more of a digital-to-analog converter, a mixer, an interpolator, and an amplifier. That is, the embodiments of this application do not limit the structure of the RF analog-to-digital converter 111 and the RF digital-to-analog converter 121.
[0083] In some embodiments, to improve the ability of the RFSoC chip to sample and output radio frequency signals of different frequencies, and to achieve precise control of the radio frequency signals, the RF digital-to-analog converter 111 may include all the components described above. Please refer to [reference needed]. Figure 8 In other words, the radio frequency analog-to-digital converter 111 may include an analog-to-digital converter, a digital attenuator, a mixer, a calibrator, and a decimation filter; wherein the analog-to-digital converter is connected to the digital attenuator and the calibrator respectively, the calibrator is also connected to the mixer, and the mixer is also connected to the decimation filter.
[0084] Additionally, in some embodiments, to enable the low-level control system to accurately generate radio frequency signals, the radio frequency analog-to-digital converter (RF converter) 121 may include all the components described above. Please refer to [reference needed]. Figure 9 In other words, an RF digital-to-analog converter includes a digital-to-analog converter, a mixer, an interpolator, and an amplifier; the digital-to-analog converter is connected to the mixer and the amplifier respectively, and the mixer is also connected to the interpolator.
[0085] It should be noted that the above description focuses on the application of the RFSoC chip in the low-level control system of a particle accelerator. However, in practical applications, the RFSoC chip can have other uses. For example, it can be connected to the BPM (Beam Position Monitor) probe of a particle accelerator. The BPM probe is used to detect beam position information. Therefore, by connecting the RFSoC chip to the BPM probe, it can achieve high-energy physics applications such as beam measurement. Alternatively, the RFSoC chip can also be used for the development and design of interlocking protection, tuning control, and other related technologies.
[0086] In some embodiments, the low-level control system further includes a memory module, a trigger module, and a clock management module. The memory module is connected to the digital signal processing module and is used to preset and store the waveforms required by the particle accelerator cavity in multiple operating modes. The trigger module is connected to the digital signal processing module and is used to receive trigger signals to enable switching of the cavity between multiple operating modes. The clock management module is connected to both the digital signal processing module and the radio frequency analog-to-digital converter (RF analog-to-digital converter) and is used to set the sampling clock signal required by the cavity and the operating clock signal required by the digital signal processing module.
[0087] It should be noted that the specific data processing flows within the aforementioned memory module, trigger module, clock management module, RF transceiver integrated chip, and digital signal processing module all employ existing technologies in this field. For example, each of the above modules can directly adopt the DDR memory module 23 disclosed in the Chinese patent document CN110234196B, entitled "A Digital Low-Level System for a Synchrotron," which stores at least 256 waveforms of the magnetic alloy loading cavity high-frequency system 3, each waveform including frequency and voltage, with different sweep ranges and cavity voltage amplitude waveforms for different operating modes. The trigger module 24 receives the optical trigger signal sent by the accelerator control system to achieve switching between various operating modes of the magnetic alloy loading cavity high-frequency system 3. The clock management module 25 is used to set... The sampling clock signal of the high-frequency system 3 with a fixed magnetic alloy loading cavity and the working clock signal of the digital signal processing module 27 are used. The analog-to-digital conversion module 26 is used to acquire the cavity electric field sampling signal of the high-frequency system 3 with a fixed magnetic alloy loading cavity according to the set sampling clock signal and convert it into a digital signal. The digital signal processing module 27 is used to read the waveform of the corresponding working mode in the DDR memory module 23 according to the working mode information contained in the optical trigger signal, and to perform logical operation processing on the digital signal using a digital PI algorithm according to the waveform of the working mode to obtain the corrected excitation signal. The digital-to-analog conversion module 28 is used to convert the corrected excitation signal into an analog signal, and then... After filtering out noise, the bandpass filter module 31 of the alloy loading cavity high-frequency system 3 excites the solid-state power amplifier module 32 of the magnetic alloy loading cavity high-frequency system 3. The amplified power is fed into the magnetic alloy cavity 33 of the magnetic alloy loading cavity high-frequency system 3, and an electric field corresponding to the waveform of the working mode is established in the magnetic alloy cavity 33. This allows the magnetic alloy cavity 33 to accelerate particles according to the corresponding working mode, realizing the switching of multiple different working modes of the magnetic alloy loading cavity high-frequency system 3. In a preferred embodiment, the digital signal processing module 27 includes a reference signal numerically controlled oscillator 271, a quadrature demodulation unit 272, a phase detection unit 273, and an amplitude PI control unit 274. 74. A first digital multiplier 275, a phase PI (proportional-integral) control unit 276, and an output signal numerically controlled oscillator 277. The reference signal numerically controlled oscillator 271 is used to obtain a reference signal based on a preset sweep frequency control word and a working clock signal. The quadrature demodulation unit 272 is used to perform quadrature demodulation on the digital signal and the obtained reference signal to obtain two I / Q (quadrature) signals, which serve as input signals for the subsequent phase detection unit. The phase detection unit 273 is used to perform digital detection on the two I / Q signals to obtain the amplitude of the digital signal, and to perform phase difference detection on the two I / Q signals to obtain the phase difference between the digital signal and the reference signal.The amplitude PI control unit 274 subtracts a preset amplitude value from the amplitude of the digital signal, and after amplitude PI adjustment, obtains a voltage amplitude signal regulated by negative feedback. This voltage amplitude signal is used to control the output signal amplitude of the output signal numerically controlled oscillator 277 by controlling the first digital multiplier 275. The phase PI control unit 276, based on the proportional and integral coefficients, adjusts the phase difference between the digital signal and the reference signal by phase PI adjustment to obtain the phase difference adjustment amount between the reference signal and the digital signal. This adjustment amount is used to control the phase control word of the output signal numerically controlled oscillator 277. The output signal numerically controlled oscillator 277 generates an output excitation signal based on the phase control word and a preset sweep frequency control word. This output excitation signal is a sinusoidal signal, and its amplitude and phase are controlled by the amplitude PI control unit 274 and the phase PI control unit 276, respectively, to form a phase negative feedback stable loop. The first digital multiplier 275 multiplies the voltage amplitude signal with the output excitation signal to obtain the amplitude-corrected excitation signal, etc.
[0088] The low-level control system provided in this application includes an RF transceiver integrated chip and a digital signal processing module. The RF transceiver integrated chip integrates an RF analog-to-digital converter and an RF digital-to-analog converter. Since the RF transceiver integrated chip can operate at a high sampling rate, it can directly sample and process the first RF signal. Furthermore, the RF transceiver integrated chip can capture and process RF signals in real time, improving system response speed and reducing system latency. Moreover, the RF transceiver integrated chip may include an RFSoC chip. Because the RFSoC chip has high integration, it enables miniaturization and high integration of the low-level control system. In addition, the RFSoC chip may also include an RF digital-to-analog converter and an RF analog-to-digital converter. Since the RF digital-to-analog converter and the RF analog-to-digital converter have high precision and low noise characteristics, they can control, process, and generate RF signals. The digital signal processing module may also include an FPGA chip, which can be integrated on the RFSoC chip. The FPGA chip includes an ARM processor, thus not only further miniaturizing the low-level control system but also enabling it to run an independent operating system for application development or human-computer interaction.
[0089] Furthermore, due to the wide frequency coverage of RFSoC chips, low-level control systems incorporating RFSoC chips can be adapted to particle accelerators with varying frequency requirements, enhancing the flexibility of the low-level control system provided in this application embodiment and broadening its application prospects. Moreover, integrating the RF analog-to-digital converter, RF digital-to-analog converter, and FPGA chip onto the RFSoC chip reduces the development difficulty and design cycle of the circuit board, thereby saving development costs and human resources for the low-level control system. Additionally, the RF analog-to-digital converter has a higher sampling rate than traditional analog-to-digital converters, enabling real-time capture and processing of RF signals, thereby improving the response speed of the low-level control system and reducing latency.
[0090] This document describes various exemplary embodiments with reference to them. However, those skilled in the art will recognize that changes and modifications can be made to the exemplary embodiments without departing from the scope of this document. For example, various operational steps and components for performing operational steps can be implemented in different ways depending on the specific application or considering any number of cost functions associated with the operation of the system (e.g., one or more steps can be deleted, modified, or combined with other steps).
[0091] While the principles herein have been illustrated in various embodiments, numerous modifications to the structure, arrangement, proportions, elements, materials, and components, particularly suited to specific environmental and operational requirements, may be used without departing from the principles and scope of this disclosure. These modifications and other alterations or alterations will be included within the scope of this document.
[0092] The foregoing specific descriptions have been described with reference to various embodiments. However, those skilled in the art will recognize that various modifications and changes can be made without departing from the scope of this disclosure. Therefore, considerations for this disclosure are to be illustrative rather than restrictive, and all such modifications are to be included within its scope. Similarly, advantages, other advantages, and solutions to problems with respect to various embodiments have been described above. However, benefits, advantages, solutions to problems, and any elements that produce these, or make them more explicit, should not be construed as critical, essential, or necessary. The term “comprising” and any other variations thereof as used herein are non-exclusive inclusion, meaning that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed or not part of the process, method, system, article, or apparatus. Furthermore, the term “coupled” and any other variations thereof as used herein refer to physical connections, electrical connections, magnetic connections, optical connections, communication connections, functional connections, and / or any other connections.
[0093] Those skilled in the art will recognize that many changes can be made to the details of the above embodiments without departing from the basic principles of this invention. Therefore, the scope of this invention should be determined only by the claims.
Claims
1. A highly integrated low-level control system applied to a particle accelerator, the particle accelerator comprising a cavity; characterized in that, The low-level control system includes: an integrated radio frequency transceiver chip and a digital signal processing module; The radio frequency transceiver integrated chip includes a radio frequency analog-to-digital conversion module and a radio frequency digital-to-analog conversion module; The radio frequency analog-to-digital conversion module is connected to the cavity of the particle accelerator and the digital signal processing module, respectively. The radio frequency analog-to-digital conversion module is used to receive a first radio frequency signal from the cavity, sample the first radio frequency signal, and convert the sampled first radio frequency signal into a digital signal and then send it to the digital signal processing module. The digital signal processing module is also connected to the radio frequency digital-to-analog converter module. The digital signal processing module includes an FPGA chip, which includes a logic unit and a processing unit. The processing unit is used to send a control signal to the logic unit. After receiving the control signal, the logic unit is used to perform logical operations on the received digital signal according to the control signal to obtain a target signal, and then send the target signal to the radio frequency digital-to-analog converter module. The processing unit is also used to acquire target data and process the target data to obtain display data for display. The target data is used to indicate the processing progress of the digital signal by the digital signal processing module, or to indicate relevant information of the target signal. The radio frequency digital-to-analog converter module is also connected to the cavity of the particle accelerator. The radio frequency digital-to-analog converter module is used to convert the received target signal into a second radio frequency signal and send the second radio frequency signal to the cavity to control the amplitude and / or phase of the signal in the cavity.
2. The low-level control system as described in claim 1, characterized in that, The radio frequency transceiver integrated chip includes an RFSoC chip.
3. The low-level control system as described in claim 2, characterized in that, The digital signal processing module is integrated on the RFSoC chip.
4. The low-level control system according to any one of claims 2-3, characterized in that, The radio frequency analog-to-digital conversion module includes a radio frequency analog-to-digital converter, and the radio frequency digital-to-analog conversion module includes a radio frequency digital-to-analog converter; The RFSoC chip includes the radio frequency analog-to-digital converter, the radio frequency digital-to-analog converter, and the FPGA chip; The radio frequency analog-to-digital converter is connected to the cavity of the particle accelerator and the FPGA chip; The FPGA chip is also connected to the radio frequency digital-to-analog converter; The radio frequency digital-to-analog converter is also connected to the cavity of the particle accelerator.
5. The low-level control system as described in claim 1, characterized in that, The processing unit includes an ARM processor.
6. The low-level control system as described in claim 1, characterized in that, The low-level control system also includes a power amplifier module; The power amplification module is connected to the radio frequency digital-to-analog converter module and the cavity, respectively. The power amplification module is used to amplify the second radio frequency signal sent by the radio frequency digital-to-analog converter module and send the amplified second radio frequency signal to the cavity to establish an electromagnetic field in the cavity and realize the acceleration effect of the particle accelerator on the beam in the cavity.
7. The low-level control system as described in claim 4, characterized in that, The radio frequency analog-to-digital converter includes any one or more of an analog-to-digital converter, a digital attenuator, a mixer, a calibrator, and a decimation filter. The radio frequency digital-to-analog converter includes any one or more of a digital-to-analog converter, a mixer, an interpolator, and an amplifier.
8. The low-level control system as described in claim 7, characterized in that, The radio frequency analog-to-digital converter includes an analog-to-digital converter, a digital attenuator, a mixer, a calibrator, and a decimation filter; The analog-to-digital converter is connected to the digital attenuator and the calibrator respectively, the calibrator is also connected to the mixer, and the mixer is also connected to the decimation filter. The radio frequency digital-to-analog converter includes a digital-to-analog converter, a mixer, an interpolator, and an amplifier; The digital-to-analog converter is connected to the mixer and the amplifier, respectively, and the mixer is also connected to the interpolator.
9. The low-level control system as described in claim 4, characterized in that, The low-level control system also includes a memory module, a trigger module, and a clock management module; The memory module is connected to the digital signal processing module and is used to preset and store the waveforms required by the cavity of the particle accelerator in multiple working modes. The triggering module is connected to the digital signal processing module and is used to receive trigger signals to enable the cavity to switch between the multiple working modes; The clock management module is connected to the digital signal processing module and the radio frequency analog-to-digital converter respectively, and is used to set the sampling clock signal required by the cavity and the working clock signal required by the digital signal processing module.