An ultra-low power sleep and multi-path wake-up circuit for 28V systems

Abstract

The utility model discloses a kind of ultra-low power hibernate and multi-path wake-up circuit for 28V system, it is related to wake-up circuit technical field, the circuit includes main control MCU and CAN bus transceiver U3, further include: power control and conversion circuit, power control and conversion circuit are connected with main control MCU and CAN bus transceiver U3 respectively, for under the control of main control MCU after receiving hibernate instruction and circuit power disconnect;28V trigger logic processing circuit, 28V trigger logic processing circuit is connected with CAN bus transceiver U3, for receiving input 28V high level signal, and make power control and conversion circuit and circuit power between conduction after receiving 28V high level signal, to solve the problem of rising power consumption that only MCU hibernate other functional part still in working state in existing, simultaneously in the case where not being equipped with logic chip and low-voltage system, the double-path simultaneous wake-up function of adaptation 28V is realized.

Description

Technical Field

[0001] This utility model relates to the field of wake-up circuit technology, and more specifically, it relates to an ultra-low power sleep and multiple wake-up circuit for a 28V system. Background Technology

[0002] In vehicle systems, a 28V battery is generally used to power the system. In order to meet the requirements of low power consumption, the relevant equipment is required to enter a power-off state when the vehicle is not running. However, some special equipment, such as instruments, need to enter a sleep state when the vehicle is not running. When certain operations are involved, the equipment needs to be woken up and put into working state.

[0003] Current sleep mode methods primarily involve the MCU entering sleep mode to reduce power consumption; however, other functional circuits in the system remain powered on, and their power consumption is not reduced. Current wake-up methods typically include CAN bus wake-up and hardware wake-up. CAN bus wake-up: the MCU exits sleep mode upon receiving a specific wake-up message; hardware wake-up: the MCU exits sleep mode after an external operation, such as pressing a button or switching on a switch. When the requirement is for two or more simultaneous actions to wake up, a corresponding logic chip is needed. However, current logic chips are not compatible with low-voltage systems of 5V and below, and cannot meet the needs of the 28V automotive system. To adapt to the 28V system, additional circuits need to be designed for voltage reduction, which increases cost and space requirements. Utility Model Content

[0004] The purpose of this invention is to provide an ultra-low power sleep and multi-channel wake-up circuit for 28V systems, so as to solve the problem of increased power consumption caused by only the MCU going into sleep mode while other functional parts are still working. At the same time, it can achieve dual-channel simultaneous wake-up function adapted to 28V without the need for logic chips and low-voltage systems.

[0005] The above-mentioned technical objective of this utility model is achieved through the following technical solution:

[0006] This application provides an ultra-low power sleep and multiple wake-up circuit for a 28V system, including a main control MCU and a CAN bus transceiver U3, wherein the main control MCU and the CAN bus transceiver U3 are connected, and further includes:

[0007] The power control and conversion circuit is connected to the main control MCU and the CAN bus transceiver U3 respectively, and is used to disconnect the circuit power supply under the control of the main control MCU after receiving the sleep command;

[0008] The 28V trigger logic processing circuit is connected to the CAN bus transceiver U3. It is used to receive the input 28V high-level signal and, after receiving the 28V high-level signal, enables the power control and conversion circuit to conduct between the power supply and the circuit power supply.

[0009] Based on the above technical solution, the present invention can be further improved as follows.

[0010] Furthermore, the aforementioned power control and conversion circuit includes diode D1, resistors R1 and R2, MOSFET Q1, power conversion chip U1, transistor Q2, resistors R5 and R3, diodes D5 and D6, resistor R8, and diode D7, which are connected together.

[0011] Furthermore, the source of the aforementioned MOSFET Q1 is connected to the power conversion chip U1, the gate of the MOSFET Q1 is connected to one end of the resistor R1 and the input terminal of the diode D1, the source of the MOSFET Q1 is connected to the other end of the resistor R1 and the output terminal of the diode D1, and the source of the MOSFET Q1 forms the power input terminal P1.

[0012] The gate of MOSFET Q1 is also connected to one end of resistor R2, the other end of resistor R2 is connected to the collector of MOSFET Q2, the two ends of resistor R5 are connected to the base and emitter of MOSFET Q2 respectively, and the base of MOSFET Q2 is also connected to one end of resistor R3 and one end of resistor R8 respectively.

[0013] The other end of resistor R3 is connected to the input of diode D5, the output of diode D5 is connected to the output of diode D6, and the input of diode D6 is connected to CAN bus transceiver U3; the other end of resistor R8 is connected to the output of diode D7, and the input of diode D7 is connected to the main control MCU.

[0014] Furthermore, the power supply VCC output by the aforementioned power conversion chip U1 is used to power the main control MCU and the CAN bus transceiver U3.

[0015] Furthermore, the aforementioned 28V trigger logic processing circuit includes diodes D2, D3, and D4, resistors R4, R7, and R9, transistor Q3, and resistor R6, which are connected to each other.

[0016] Furthermore, the input terminals of diode D2 and diode D3 respectively form wake-up source P2 and wake-up source P3. The input terminal of diode D4 is connected to one end of resistor R7 and the emitter of transistor Q3 respectively. The other end of resistor R7 is grounded. The base of transistor Q3 is connected to one end of resistor R6. The other end of resistor R6 and the collector of transistor Q3 respectively form wake-up source P5 and wake-up source P4.

[0017] The output terminals of diodes D2, D3, and D4 are interconnected, and after connection, they are also connected to one end of resistor R4 and one end of resistor R9 respectively. The other end of resistor R4 is grounded, and the other end of resistor R9 is connected to CAN bus transceiver U3.

[0018] Furthermore, the CAN-TX and CAN-RX pins of the main control MCU are connected to the TXD and RXD pins of the CAN bus transceiver U3, respectively; the MOSI, MISO, SCLK, and CS pins of the main control MCU are connected to the SDI, SDO, SCK, and SCSN pins of the CAN bus transceiver U3, respectively.

[0019] Furthermore, the above also includes a CAN bus circuit, which is formed through the CAN bus transceiver U3.

[0020] Furthermore, the aforementioned CAN bus circuit includes a CAN bus transceiver U3, resistors R10, R11, and R12 that are connected to each other.

[0021] Furthermore, one end of resistor R10 and one end of resistor R12 form external CAN bus ports P6 and P7 respectively, and the ends of resistor R10 and R12 are also connected to the two ends of resistor R11 respectively; the other ends of resistor R10 and R12 are connected to the CANH pin and CANL pin of CAN bus transceiver U3 respectively.

[0022] Compared with the prior art, the present invention has at least the following beneficial effects:

[0023] The overall circuit is simple and occupies little space. It can meet the direct hardware wake-up of 28V systems without the need for additional dedicated logic chips and voltage conversion, reducing costs and hardware design space. At the same time, it is powered off as a whole after entering sleep mode, further reducing power consumption. It can also simultaneously meet the functions of CAN bus wake-up, multi-channel AND logic hardware trigger wake-up, and multi-channel OR logic hardware wake-up. Attached Figure Description

[0024] The accompanying drawings, which are included to provide a further understanding of the embodiments of the present invention and form part of this application, do not constitute a limitation thereof. In the drawings:

[0025] Figure 1 This is a schematic diagram showing the connection of the ultra-low power sleep and multiple wake-up circuits in an embodiment of this utility model. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. The components of the embodiments of this utility model described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0027] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0028] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0029] In the description of the embodiments of this utility model, "a plurality of" means at least two.

[0030] In the description of the embodiments of this utility model, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.

[0031] Example 1: Currently, in sleep mode, only the MCU is powered off, while other functional circuits remain powered on. When the requirement is for two or more channels to operate simultaneously to wake up, a corresponding logic chip is needed. However, current logic chips are not compatible with low-voltage systems of 5V and below, and cannot meet the needs of automotive 28V systems. Therefore, this example provides an ultra-low-power sleep and multi-channel wake-up circuit for 28V systems, such as... Figure 1 As shown, it includes a main control MCU and a CAN bus transceiver U3, and the main control MCU and the CAN bus transceiver U3 are connected.

[0032] Optionally, the CAN-TX and CAN-RX pins of the main control MCU are connected to the TXD and RXD pins of the CAN bus transceiver U3, respectively; the MOSI, MISO, SCLK, and CS pins of the main control MCU are connected to the SDI, SDO, SCK, and SCSN pins of the CAN bus transceiver U3, respectively.

[0033] The above also includes a CAN bus circuit, which is formed through a CAN bus transceiver U3. The CAN bus circuit includes the CAN bus transceiver U3, resistors R10, R11, and R12, which are interconnected. (See [link to relevant documentation]). Figure 1 .

[0034] Specifically, one end of resistor R10 and one end of resistor R12 form external CAN bus ports P6 and P7 respectively, and the ends of resistor R10 and R12 are also connected to the two ends of resistor R11 respectively; the other ends of resistor R10 and R12 are connected to the CANH pin and CANL pin of CAN bus transceiver U3 respectively.

[0035] Furthermore, this ultra-low power sleep and multiple wake-up circuit also includes:

[0036] The power control and conversion circuit is connected to both the main control MCU and the CAN bus transceiver U3. It is used to disconnect the circuit power supply under the control of the main control MCU after receiving a sleep command.

[0037] Specifically, the power control and conversion circuit includes diode D1, resistors R1 and R2, MOSFET Q1, power conversion chip U1, transistor Q2, resistors R5 and R3, diode D5, diode D6, resistor R8, and diode D7, which are connected in a series. Figure 1 As shown.

[0038] In this configuration, the source of MOSFET Q1 is connected to power conversion chip U1, the gate of MOSFET Q1 is connected to one end of resistor R1 and the input terminal of diode D1, and the drain of MOSFET Q1 is connected to the other end of resistor R1 and the output terminal of diode D1, with the drain of MOSFET Q1 forming the power input terminal P1. The gate of MOSFET Q1 is also connected to one end of resistor R2, and the other end of resistor R2 is connected to the collector of transistor Q2. The two ends of resistor R5 are connected to the base and emitter of transistor Q2, respectively. The base of transistor Q2 is also connected to one end of resistor R3 and one end of resistor R8, respectively. The other end of resistor R3 is connected to the input terminal of diode D5, the output terminal of diode D5 is connected to the output terminal of diode D6, and the input terminal of diode D6 is connected to CAN bus transceiver U3. The other end of resistor R8 is connected to the output terminal of diode D7, and the input terminal of diode D7 is connected to the main control MCU.

[0039] Optionally, the power supply VCC output by the power conversion chip U1 is used to power the main control MCU and the CAN bus transceiver U3.

[0040] Furthermore, this ultra-low power sleep and multiple wake-up circuit also includes:

[0041] The 28V trigger logic processing circuit is connected to the CAN bus transceiver U3. It is used to receive the input 28V high-level signal and, after receiving the 28V high-level signal, enables the power control and conversion circuit to conduct between the power supply and the circuit power supply.

[0042] Specifically, the aforementioned 28V trigger logic processing circuit includes diodes D2, D3, and D4, resistors R4, R7, and R9, transistor Q3, and resistor R6, which are interconnected. (See [link to relevant documentation]). Figure 1 .

[0043] Specifically, the input terminals of diodes D2 and D3 form wake-up sources P2 and P3, respectively. The input terminal of diode D4 is connected to one end of resistor R7 and the emitter of transistor Q3, with the other end of resistor R7 grounded. The base of transistor Q3 is connected to one end of resistor R6, and the other end of resistor R6 and the collector of transistor Q3 form wake-up sources P5 and P4, respectively. The output terminals of diodes D2, D3, and D4 are interconnected and, after connection, are also connected to one end of resistor R4 and one end of resistor R9, with the other end of resistor R4 grounded. The other end of resistor R9 is connected to the CAN bus transceiver U3.

[0044] Example 2: The ultra-low power sleep and multiple wake-up circuit provided in this example consists of a main control MCU, a CAN bus transceiver U3, a power control and conversion circuit, and a 28V trigger logic processing circuit. Its circuit schematic is shown below. Figure 1As shown, where:

[0045] P1 is a 28V power input port;

[0046] P2, P3, P4, and P5 are external 28V hardware wake-up sources; P2, P3, P4 / P5 are logical "OR" wake-up sources; and P4 and P5 are logical "AND" wake-up sources.

[0047] P6 and P7 are external CAN bus ports;

[0048] The power control and conversion circuit consists of diode D1, resistors R1 and R2, MOSFET Q1, power conversion chip U1, transistor Q2, resistors R5 and R3, diodes D5 and D6, resistor R8, and diode D7. D1 is a Zener diode, Q1 is a P-MOSFET, U1 is a power conversion chip (adjusted according to the power supply voltage of the MCU and other functional devices), Q2 is the controller of MOSFET Q1, controlled by MCU U2 and CAN transceiver U3; resistors R1, R2, R3, R5, R8, diodes D5 and D6 are used for protection of the control circuit.

[0049] U3 is a CAN bus transceiver with wake-up function, which can be configured to wake up via SPI bus; U3, together with resistors R10, R11 and R12, form a CAN bus circuit, and resistor R11 is the matching resistor for the CAN bus.

[0050] Diodes D2, D3, and D4, resistors R4, R7, and R9, transistor Q3, and resistor R6 form a 28V trigger logic processing circuit; see [link to relevant documentation]. Figure 1 28V_WAKE3 and 28V_WAKE4 form an AND logic through the Q3 NPN transistor. When the 28V_WAKE4 terminal is high (28V), the Q3 transistor is turned on. When the 28V_WAKE3 terminal is high, the voltage divider circuit composed of Q3, D4, R4, and R9 enters pin 9 of U3 to trigger and wake up the device. Diodes D2, D3, and D4 form an OR logic, which also serves to prevent reverse current. When any one of them is high, the voltage divider circuit composed of R4 and R9 enters pin 9 of U3 to trigger and wake up the device.

[0051] The overall operation of the ultra-low power sleep and multiple wake-up circuit provided in this embodiment is as follows:

[0052] When the main control MCU receives the sleep command via the CAN bus, it configures the U3 CAN transceiver via the SPI bus. After the wake-up function reset (pin 7 of U3 outputs a low level) takes effect, the control IO outputs a low level through diode D7, transistor Q2 is turned off, MOSFET Q1 is not turned on, the VCCIN power supply voltage cannot be converted through U1, and the power supply of the entire circuit is disconnected. At this time, only the wake-up function part of the U3 CAN transceiver is working, powered by VCCIN. The power consumption is extremely small, thereby reducing the overall power consumption.

[0053] When one of P2 or P3 is allowed by the design to be a 28V high-level input, the hardware wake-up function of the U3 CAN transceiver takes effect. The U3 CAN transceiver outputs a high level at pin 7, which, after voltage division by resistors R3 and R5, turns on transistor Q2. Then, MOSFET Q1 conducts, power is input, and the entire circuit powers on and enters the working state. The main control MCU outputs a high level through the IO to keep transistor Q2 in the conducting state. At the same time, the U3 CAN transceiver is configured via the SPI bus to disable the wake-up function; this is a multi-channel logic "OR" wake-up.

[0054] When both P4 and P5 have a 28V high-level input, transistor Q3 turns on. The high level on P4 triggers the U3CAN transceiver to wake up. Pin 7 of the U3CAN transceiver outputs a high level, which, through resistors R3 and R5, divides the voltage and turns on transistor Q2. Then, MOSFET Q1 turns on, power is input, and the entire circuit powers on and enters the working state. The main control MCU outputs a high level through the I / O pin to keep transistor Q2 on. Simultaneously, the U3CAN transceiver is configured via the SPI bus to disable the wake-up function; this is a dual-channel AND logic wake-up.

[0055] If a CAN bus wake-up command is received, pin 7 of the U3CAN transceiver outputs a high level. After voltage division by resistors R3 and R5, transistor Q2 is turned on, and then MOSFET Q1 is turned on. With power input, the entire circuit powers on and enters the working state. The main control MCU outputs a high level through IO to keep transistor Q2 in the on state. At the same time, the U3 CAN transceiver is configured via the SPI bus to disable the wake-up function.

[0056] The overall circuit provided in this embodiment is simple, occupies little space, and can meet the direct hardware wake-up of the 28V system without the need for additional dedicated logic chips and voltage conversion, reducing costs and hardware design space; at the same time, the entire circuit is powered off after entering the sleep state, further reducing power consumption; it can also simultaneously meet the functions of CAN bus wake-up, multi-channel AND logic hardware trigger wake-up, and multi-channel OR logic hardware wake-up.

[0057] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this utility model. It should be understood that the above description is only a specific embodiment of this utility model and is not intended to limit the scope of protection of this utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the scope of protection of this utility model.

Claims

1. An ultra-low power sleep and multiple wake-up circuit for a 28V system, comprising a main control MCU and a CAN bus transceiver U3, wherein the main control MCU and the CAN bus transceiver U3 are connected, characterized in that, Also includes: A power control and conversion circuit is connected to the main control MCU and the CAN bus transceiver U3 respectively, and is used to disconnect the circuit power supply under the control of the main control MCU after receiving a sleep command; A 28V trigger logic processing circuit is connected to the CAN bus transceiver U3. It is used to receive the input 28V high-level signal and, after receiving the 28V high-level signal, to connect the power control and conversion circuit with the circuit power supply.

2. The ultra-low power sleep and multiple wake-up circuit for a 28V system according to claim 1, characterized in that, The power control and conversion circuit includes diode D1, resistors R1 and R2, MOSFET Q1, power conversion chip U1, transistor Q2, resistors R5 and R3, diode D5, diode D6, resistor R8, and diode D7, which are connected together.

3. The ultra-low power sleep and multiple wake-up circuit for a 28V system according to claim 2, characterized in that, The source of the MOS transistor Q1 is connected to the power conversion chip U1, the gate of the MOS transistor Q1 is connected to one end of the resistor R1 and the input terminal of the diode D1, the source of the MOS transistor Q1 is connected to the other end of the resistor R1 and the output terminal of the diode D1, and the source of the MOS transistor Q1 forms the power input terminal P1. The gate of the MOS transistor Q1 is also connected to one end of the resistor R2, the other end of the resistor R2 is connected to the collector of the transistor Q2, the two ends of the resistor R5 are respectively connected to the base and emitter of the transistor Q2, and the base of the transistor Q2 is also respectively connected to one end of the resistor R3 and one end of the resistor R8. The other end of the resistor R3 is connected to the input terminal of the diode D5, the output terminal of the diode D5 is connected to the output terminal of the diode D6, and the input terminal of the diode D6 is connected to the CAN bus transceiver U3. The other end of the resistor R8 is connected to the output terminal of the diode D7, and the input terminal of the diode D7 is connected to the main control MCU.

4. The ultra-low power sleep and multiple wake-up circuit for a 28V system according to claim 2, characterized in that, The power supply VCC output by the power conversion chip U1 is used to power the main control MCU and the CAN bus transceiver U3.

5. The ultra-low power sleep and multiple wake-up circuit for a 28V system according to claim 1, characterized in that, The 28V trigger logic processing circuit includes diodes D2, D3, and D4, resistors R4, R7, and R9, transistor Q3, and resistor R6, which are connected to each other.

6. The ultra-low power sleep and multiple wake-up circuit for a 28V system according to claim 5, characterized in that, The input terminals of diode D2 and diode D3 form wake-up sources P2 and P3, respectively. The input terminal of diode D4 is connected to one end of resistor R7 and the emitter of transistor Q3. The other end of resistor R7 is grounded. The base of transistor Q3 is connected to one end of resistor R6. The other end of resistor R6 and the collector of transistor Q3 form wake-up sources P5 and P4, respectively. The output terminals of diodes D2, D3, and D4 are interconnected, and after connection, they are also connected to one end of resistor R4 and one end of resistor R9, respectively. The other end of resistor R4 is grounded, and the other end of resistor R9 is connected to the CAN bus transceiver U3.

7. The ultra-low power sleep and multiple wake-up circuit for a 28V system according to claim 1, characterized in that, The CAN-TX and CAN-RX pins of the main control MCU are respectively connected to the TXD and RXD pins of the CAN bus transceiver U3; the MOSI, MISO, SCLK, and CS pins of the main control MCU are respectively connected to the SDI, SDO, SCK, and SCSN pins of the CAN bus transceiver U3.

8. An ultra-low power sleep and multiplex wake-up circuit for a 28V system according to any one of claims 1-7, characterized in that, It also includes a CAN bus circuit, which is formed by a CAN bus transceiver U3.

9. The ultra-low power sleep and multiple wake-up circuit for a 28V system according to claim 8, characterized in that, The CAN bus circuit includes the CAN bus transceiver U3, resistor R10, resistor R11, and resistor R12, which are connected.

10. The ultra-low power sleep and multiplex wake-up circuit for a 28V system according to claim 9, characterized in that, One end of resistor R10 and one end of resistor R12 form external CAN bus ports P6 and P7, respectively, and the ends of resistor R10 and R12 are also connected to the two ends of resistor R11, respectively; the other ends of resistor R10 and R12 are connected to the CANH pin and CANL pin of CAN bus transceiver U3, respectively.

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