HBN appliance and its power-off reset circuit

Abstract

The utility model discloses a kind of HBN appliances and its power-off reset circuit, power-off reset circuit includes first switch module, second switch module, third switch module, voltage divider module, fourth switch module and fifth switch module, when the control signal that control module outputs is normal, first switch module, second switch module and third switch module are all on, power supply voltage is powered to control module;When the control signal that control module outputs is abnormal, first switch module and second switch module are all disconnected, when USB interface connects USB equipment, fifth switch module is on, fourth switch module is on first preset time and then off, voltage divider module is divided voltage first preset time and then stops voltage division to power supply voltage, third switch module is off first preset time and then on again, to make control module carry out power-off reset;The technical scheme does not need external reset button, compact structure, response is quick, improve the reliability of system and user use safety.

Description

Technical Field

[0001] This utility model relates to the field of HBN device technology, and in particular to an HBN device and its power-off reset circuit. Background Technology

[0002] HNB (Heat Not Burning) appliances, as a new type of product, rely on precise control of the heating element to achieve low-temperature heating. Currently, HNB appliances generally use microcontrollers to control the heating process, working in conjunction with temperature sensing, battery management, and button operation modules. However, in practical applications, if the microcontroller software malfunctions, such as entering an infinite loop or experiencing response blockage, heating may continue uninterrupted, leading to high-temperature risks and, in severe cases, even threatening user safety.

[0003] Traditional solutions often employ hardware reset circuits, such as a reset button, allowing manual operation to reset the microcontroller in case of system malfunction. However, this approach not only requires additional structural space, increasing product size, but also makes it inconvenient for users to operate. Furthermore, in some microcontrollers, the reset pin may be reused or fail, reducing the reliability of the reset. Utility Model Content

[0004] This utility model provides an HBN device and its power-off reset circuit to solve the above-mentioned technical problems.

[0005] The first aspect of this utility model provides a power-off reset circuit for an HBN device, comprising:

[0006] The first switch module has one end connected to the power supply voltage, and its control end receives the control signal output by the control module.

[0007] The second switch module has its control terminal connected to the other end of the first switch module, and one end of its terminal is grounded.

[0008] The third switch module has one end connected to the power supply voltage, the other end connected to the power supply port of the control module, and its control terminal connected to the other end of the second switch module.

[0009] The voltage divider module has its first end connected to the control terminal of the third switch module and its second end grounded.

[0010] The fourth switch module has one end connected to the power supply voltage and the other end connected to the third terminal of the voltage divider module.

[0011] The fifth switch module has one end connected to the control terminal of the fourth switch module and the other end grounded. Its control terminal is a USB interface.

[0012] When the control signal output by the control module is normal, the first switch module, the second switch module and the third switch module are all turned on, and the power supply voltage supplies power to the control module.

[0013] When the control signal output by the control module is abnormal, both the first and second switch modules are disconnected. When the USB interface is connected to a USB device, the fifth switch module is turned on. The fourth switch module is turned on for a first preset time and then turned off. The voltage divider module divides the power supply voltage for a first preset time and then stops dividing the voltage. The third switch module is turned off for a first preset time and then turned on again, so that the control module can be power-off reset.

[0014] Optionally, the control signal output by the control module is normally a pulse signal that the control module periodically outputs when the heating program is normal. This pulse signal has a falling edge that periodically switches from high level to low level.

[0015] Optionally, the abnormal control signal output by the control module is one of continuously outputting a high-level signal and a low-level signal when the heating program is abnormal.

[0016] Optionally, the first switching module includes a third PMOS transistor, a sixth resistor, a seventh resistor, and a third capacitor. The source of the third PMOS transistor, one end of the sixth resistor, and one end of the seventh resistor are all connected to one end of the first switching module. The gate of the third PMOS transistor is connected to the other end of the sixth resistor and one end of the third capacitor, respectively. The other end of the third capacitor and the other end of the seventh resistor are all connected to the control terminal of the first switching module. The drain of the third PMOS transistor is the other end of the first switching module.

[0017] Optionally, the second switching module includes an NMOS transistor, an eighth resistor, and a second capacitor. The gate of the NMOS transistor, one end of the eighth resistor, and one end of the second capacitor are connected together as the control terminal of the second switching module. The source of the NMOS transistor, the other end of the second capacitor, and the other end of the eighth resistor are connected together as one end of the second switching module. The drain of the NMOS transistor is the other end of the second switching module.

[0018] Optionally, the third switching module includes a first PMOS transistor, the source of the first PMOS transistor is one end of the third switching module, the drain of the first PMOS transistor is the other end of the third switching module, and the gate of the first PMOS transistor is the control terminal of the third switching module.

[0019] Optionally, the voltage divider module includes a first resistor and a fifth resistor. One end of the first resistor is the third terminal of the voltage divider module, and the other end of the first resistor and one end of the fifth resistor are connected together to form the first terminal of the voltage divider module. The other end of the fifth resistor is the second terminal of the voltage divider module.

[0020] Optionally, the fourth switching module includes a second PMOS transistor, a second resistor, a third resistor, and a first capacitor. The source of the second PMOS transistor, one end of the second resistor, and one end of the third resistor are all connected to one end of the fourth switching module. The gate of the second PMOS transistor is connected to the other end of the third resistor and one end of the first capacitor. The other end of the first capacitor and the other end of the second resistor are all connected to the control terminal of the fourth switching module. The drain of the second PMOS transistor is the other end of the fourth switching module.

[0021] Optionally, the fifth switching module includes an NPN transistor, a ninth resistor, and a tenth resistor. The collector of the NPN transistor is one end of the fifth switching module, and the base of the NPN transistor is connected to one end of the ninth resistor and one end of the tenth resistor, respectively. The other end of the ninth resistor is the control terminal of the fifth switching module, and the emitter of the NPN transistor and the other end of the tenth resistor are connected together to form the other end of the fifth switching module.

[0022] A second aspect of this utility model provides an HBN device, which includes the power-off reset circuit and control module described in the first aspect.

[0023] The technical advantages of this utility model embodiment are as follows: By introducing an intelligent power-off reset circuit composed of multi-level switch modules into the HNB device, when the control module malfunctions, the power supply to the control module can be automatically cut off and briefly interrupted by inserting a USB device to achieve power-off reset. When the control module is operating normally, the circuit remains in a conducting state to ensure uninterrupted power supply, thereby achieving a dual control effect of uninterrupted normal control and automatic reset in abnormal states. This technical solution does not require an external reset button, has a compact structure, responds quickly, and improves the reliability of the system and the safety of user operation. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the description of the embodiments of this utility model will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1This is a schematic diagram of the first structure of a power-off reset circuit for an HBN device provided in Embodiment 1 of this utility model;

[0026] Figure 2 This is a schematic diagram of the second structure of the power-off reset circuit of an HBN device provided in Embodiment 1 of this utility model;

[0027] In the diagram: 101, First switch module; 102, Second switch module; 103, Third switch module; 104, Voltage divider module; 105, Fourth switch module; 106, Fifth switch module. Detailed Implementation

[0028] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present utility model.

[0029] It should be understood that this invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of this invention to those skilled in the art. In the drawings, for clarity, the dimensions of layers and regions, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0030] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this utility model, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0031] To fully understand this utility model, detailed structures and steps will be presented in the following description to illustrate the technical solution proposed by this utility model. Preferred embodiments of this utility model are described in detail below; however, in addition to these detailed descriptions, this utility model may have other embodiments.

[0032] Example 1

[0033] This embodiment provides a power-off reset circuit for an HBN device, such as... Figure 1 As shown, it includes:

[0034] The first switch module 101 has one end connected to the power supply voltage VCC, and its control terminal receives the control signal output by the control module.

[0035] The second switch module 102 has its control terminal connected to the other end of the first switch module 101, and one end of its terminal is grounded.

[0036] The third switch module 103 has one end connected to the power supply voltage VCC, the other end connected to the power supply port of the control module, and its control terminal connected to the other end of the second switch module 102.

[0037] Voltage divider module 104, its first end is connected to the control terminal of third switch module 103, and its second end is grounded;

[0038] The fourth switch module 105 has one end connected to the power supply voltage VCC and the other end connected to the third terminal of the voltage divider module 104.

[0039] The fifth switch module 106 has one end connected to the control terminal of the fourth switch module 105 and the other end grounded. Its control terminal is a USB interface.

[0040] When the control signal output by the control module is normal, the first switch module 101, the second switch module 102 and the third switch module 103 are all turned on, and the power supply voltage VCC supplies power to the control module.

[0041] When the control signal output by the control module is abnormal, both the first switch module 101 and the second switch module 102 are disconnected. When the USB interface is connected to a USB device, the fifth switch module 106 is turned on, the fourth switch module 105 is turned on for a first preset time and then turned off, the voltage divider module 104 divides the power supply voltage for a first preset time and then stops dividing the voltage, and the third switch module 103 is turned off for a first preset time and then turned on again, so that the control module can be powered off and reset.

[0042] The system comprises the following modules: a first switch module 101, one end of which is connected to the power supply voltage VCC, and its control terminal connected to the control signal output by the control module, used to control the switching on or off based on the status of the control signal. A second switch module 102, its control terminal connected to the other end of the first switch module 101, and one end grounded, used to pull the signal transmitted by the first switch module 101 low. A third switch module 103, one end of which is connected to the power supply voltage, and the other end connected to the power supply terminal VDD of the control module, and its control terminal connected to the output terminal of the second switch module 102, its on / off state determining whether the control module receives power. A voltage divider module is used to divide the power supply voltage VCC when the second switch module 102 is not on, to determine the control terminal level of the third switch module 103. A fourth switch module 105, one end of which is connected to the power supply voltage, and the other end connected to the intermediate node of the voltage divider module 104, its control terminal connected to the output terminal of the fifth switch module 106, used to turn on when a USB device is inserted, providing a short-term voltage divider to raise the gate voltage of the third switch module 103, thereby turning it off. The fifth switch module 106 has its control terminal connected to the VBUS signal of the USB interface, one end grounded, and the other end connected to the control terminal of the fourth switch module 105. It is used to pull down the voltage of the fourth switch module 105 when a USB device is detected being inserted, thereby turning on the fourth switch module 105. When the control module is normally outputting a control signal, this signal is periodically pulled low, turning on the first switch module 101, the second switch module 102, and subsequently the third switch module 103. The power supply voltage VCC provides a continuous and stable power supply to the control module via the third switch module 103. When the control module program malfunctions or the heating program is not running, the output control signal remains at a constant level, and both the first and second switch modules 101 and 102 are turned off. The control terminal voltage of the third switch module 103 is determined by the voltage divider module 104 and remains in the off state. At this time, when a USB device is connected to the USB interface, the fifth switch module 106 turns on, thereby turning on the fourth switch module 105. Power is supplied to the voltage divider network within a first preset time, causing the control terminal voltage of the third switch module 103 to rise and turn off, achieving a short-term power outage for the control module. After the first preset time has elapsed, the fourth switch module 105 automatically turns off, the third switch module 103 resumes conduction, and the control module regains power, thus completing a power outage reset.

[0043] The technical advantages of the solution provided in this embodiment are as follows: By introducing an intelligent power-off reset circuit composed of multi-level switch modules into the HNB device, when the control module malfunctions, the power supply to the control module can be automatically cut off and briefly interrupted by inserting a USB device to achieve power-off reset. When the control module is operating normally, the circuit remains in a conducting state to ensure uninterrupted power supply, thereby achieving a dual control effect of uninterrupted normal control and automatic reset in abnormal states. This technical solution does not require an external reset button, has a compact structure, responds quickly, and improves the reliability of the system and the safety of user operation.

[0044] In one implementation, the control signal output by the control module is normally a periodic pulse signal output by the control module when the heating program is normal. The control signal output by the control module is abnormal when the heating program malfunctions and continuously outputs either a high-level signal or a low-level signal.

[0045] The control module is preferably a microcontroller unit (MCU), which is responsible for controlling the heating program of the HNB appliance. When the MCU is in normal operation and executing the heating logic, it periodically outputs a control signal OUT_MCU through an IO pin. This pulse signal has a falling edge that periodically switches from high to low. Specifically, the control signal OUT_MCU is a periodic pulse signal. That is, in each heating control cycle, the MCU will periodically pull the OUT_MCU pin low for a period of time (e.g., several milliseconds) and then return it to high. The period and duty cycle of this pulse signal can be set according to the heating control logic, and are commonly tens to hundreds of milliseconds per cycle. This periodic change can effectively trigger the subsequent MOSFET to conduct, thereby continuously maintaining the MCU's power supply. When the MCU is in an abnormal state (e.g., program freeze, stuck in an infinite loop, or performing an abnormal jump), the OUT_MCU signal will lose its periodic change and remain at a continuous high or continuous low level. At this time, the first switch module 101 cannot conduct normally, causing the second switch module 102 and the third switch module 103 to be turned off successively.

[0046] As one implementation method, such as Figure 2 As shown, the first switching module 101 includes a third PMOS transistor Q3, a sixth resistor R6, a seventh resistor R7, and a third capacitor C3. The source of the third PMOS transistor Q3, one end of the sixth resistor R6, and one end of the seventh resistor R7 are all connected to one end of the first switching module 101. The gate of the third PMOS transistor Q3 is connected to the other end of the sixth resistor R6 and one end of the third capacitor, respectively. The other end of the third capacitor and the other end of the seventh resistor R7 are all connected to the control terminal of the first switching module 101. The drain of the third PMOS transistor Q3 is the other end of the first switching module 101.

[0047] The third PMOS transistor Q3 is turned on when the gate-source voltage reaches a preset value, thereby transmitting the power supply VCC voltage to the second switching module 102. The sixth resistor R6 and the seventh resistor R7 form a capacitor current-limiting charging path to limit the charging speed of the capacitor when the control signal changes. They also serve as the gate pull-up resistor for the third PMOS transistor Q3, keeping the gate close to VCC when the control signal is idle to prevent false turn-on. The seventh resistor R7 provides a pull-up / pull-down path for the control port, forming a delayed charging circuit with the third capacitor C3 to pull up the other end of the third capacitor C3, facilitating capacitor discharge when the control signal is released. The third capacitor C3 isolates instantaneous changes in the control signal. When the control signal OUT_MCU changes from high to low, the gate is pulled low instantaneously because the voltage across the capacitor cannot change abruptly, creating a turn-on condition. After charging, the gate voltage recovers, forming a brief turn-on pulse. The first switching module 101 uses an RC charging / discharging and PMOS transistor control structure to drive the PMOS transistor to conduct briefly by the periodic signal changes output by the control module, transmitting a high-level power supply to the subsequent stage. When the control module malfunctions and the signal remains constant, the PMOS transistor remains off, automatically entering the preset reset path. The first switching module 101 is not limited to using an RC delay trigger structure composed of a PMOS transistor, resistor, and capacitor; it can also be implemented using the following alternative structures, as detailed below:

[0048] 1. Edge detection structure: Schmitt trigger and MOS transistor drive. The first switching module 101 can use a Schmitt trigger or digital edge detection circuit to process the OUT_MCU signal, and output its transition as a conduction signal to drive the PMOS transistor or NPN transistor to conduct.

[0049] 2. Analog comparator delay structure: The first switching module 101 may include a low-power analog comparator module for analyzing the frequency of level changes of the OUT_MCU signal within a preset time window; if no valid transition is detected within the specified time, the comparator output flips, controls the subsequent MOS transistor to turn off, thereby interrupting the power supply and realizing a reset.

[0050] As one implementation method, such as Figure 2 As shown, the second switching module 102 includes an NMOS transistor Q4, an eighth resistor R8, and a second capacitor C2. The gate of the NMOS transistor Q4, one end of the eighth resistor R8, and one end of the second capacitor C2 are connected together as the control terminal of the second switching module 102. The source of the NMOS transistor Q4, the other end of the second capacitor C2, and the other end of the eighth resistor R8 are connected together as one end of the second switching module 102. The drain of the NMOS transistor Q4 is the other end of the second switching module 102.

[0051] In this circuit, NMOS transistor Q4 performs a switching action, controlling whether to pull the gate of the third switching module 103 low. When the gate voltage is higher than the source voltage and reaches a threshold, NMOS transistor Q4 is turned on, and the third switching module 103 is turned on, providing normal power to the control module. The eighth resistor R8 and the second capacitor C2 form an RC charging and discharging circuit to prevent sudden changes in gate voltage; they also buffer voltage together with the second capacitor C2 when the control signal changes; when the control signal OUT_MCU fails, the second capacitor C2 discharges through the eighth resistor R8, causing NMOS transistor Q4 to automatically turn off and enter a power-off preparation state. The second capacitor C2 receives the turn-on pulse from the first switching module 101 and, together with the eighth resistor R8, determines the on-time of NMOS transistor Q4. The second switching module 102 can also adopt the following modified structures: 1. Single NMOS direct drive, with the gate directly connected to the output of the first switching module 101. 2. Digital edge latch structure, introducing a Schmitt trigger or digital pulse shaping circuit. 3. Dual NMOS complementary structure, using two stages of series-connected NMOS transistors to achieve signal enhancement.

[0052] As one implementation method, such as Figure 2 As shown, the third switching module 103 includes a first PMOS transistor Q1. The source of the first PMOS transistor Q1 is one end of the third switching module 103, the drain of the first PMOS transistor Q1 is the other end of the third switching module 103, and the gate of the first PMOS transistor Q1 is the control terminal of the third switching module 103.

[0053] The first PMOS transistor Q1 determines whether the control module can obtain power from the power supply voltage VCC; its conduction state determines whether the control module is in operation. When the gate voltage is pulled down to a certain level below the source voltage, the conduction condition is met, and the first PMOS transistor Q1 turns on. After conduction, the power supply voltage VCC is transmitted to the power supply terminal of the control module through the source and drain, and the control module starts or continues to work. When the gate voltage rises to near VCC, the first PMOS transistor Q1 turns off, cutting off the power supply, and the control module is powered off and reset. During normal operation, the first switch module 101 and the second switch module 102 work together to keep the first PMOS transistor Q1 continuously conducting. When the heating program is abnormal, the second switch module 102 turns off, and its gate potential is controlled by the pull-up effect caused by the voltage divider network or USB insertion. If the gate voltage is pulled high, the first PMOS transistor Q1 will enter the cut-off state, disconnecting the MCU power supply and realizing a power-off reset.

[0054] As one implementation method, such as Figure 2 As shown, the voltage divider module 104 includes a first resistor R1 and a fifth resistor R5. One end of the first resistor R1 is the third end of the voltage divider module 104. The other end of the first resistor R1 and one end of the fifth resistor R5 are connected together to form the first end of the voltage divider module 104. The other end of the fifth resistor R5 is the second end of the voltage divider module 104.

[0055] In this system, the first resistor R1 conducts part of the power supply voltage to the gate node of the first PMOS transistor Q1; together with the fifth resistor R5, it forms a standard resistor voltage divider network. When the voltage divider module 104 receives power from the fourth switch module 105, it can form a gate bias voltage; the bias voltage determines whether the first PMOS transistor Q1 is turned off. The fifth resistor R5 and the first resistor R1 divide the voltage proportionally, affecting the gate level of the first PMOS transistor Q1; the proportional design ensures that the gate-source voltage difference is greater than the conduction threshold of the first PMOS transistor Q1, ensuring that the first PMOS transistor Q1 is turned off when needed. The voltage divider module 104 can also have the following structures: 1. Adjustable voltage divider structure, where the first or fifth resistor uses a multi-turn adjustable potentiometer or digital resistor; 2. Multi-stage voltage divider network: using three or more resistors in series to achieve fine control; 3. Voltage divider network with a filter capacitor, where a small capacitor (such as 0.01μF) is connected in parallel between the first and second terminals; this can filter out power supply ripple or transient interference when the USB is plugged in, improving stability.

[0056] As one implementation method, such as Figure 2 As shown, the fourth switch module 105 includes a second PMOS transistor Q2, a second resistor R2, a third resistor R3, and a first capacitor C1. The source of the second PMOS transistor Q2, one end of the second resistor R2, and one end of the third resistor R3 are all connected to one end of the fourth switch module 105. The gate of the second PMOS transistor Q2 is connected to the other end of the third resistor R3 and one end of the first capacitor C1. The other end of the first capacitor C1 and the other end of the second resistor R2 are all connected to the control terminal of the fourth switch module 105. The drain of the second PMOS transistor Q2 is the other end of the fourth switch module 105.

[0057] The second PMOS transistor Q2 conducts when a USB device is inserted, outputting VCC to the voltage divider network. Its conduction time is controlled by an RC delay, forming a short conduction pulse. After the delay, it automatically turns off, ensuring the control module resumes power supply. The second resistor R2 is connected in series with the first capacitor C1, controlling the charging and discharging path and the charging speed after the USB device is inserted, thus affecting the conduction time. The third resistor R3 is connected to the gate of the second PMOS transistor Q2, limiting the current during the charging and discharging of the first capacitor C1; it also prevents gate voltage spikes during switch transitions, protecting the second PMOS transistor Q2. The first capacitor C1 receives voltage transients triggered by the USB device. Since the voltage across the capacitor cannot change abruptly, the gate is momentarily pulled low when the USB device is inserted, creating the conduction condition for the second PMOS transistor Q2, triggering it upon insertion. It then gradually recovers its charge, causing the second PMOS transistor Q2 to automatically turn off. The fourth switch module 105 can also adopt the following structure: 1. The third resistor R3 is omitted, and the control terminal is directly connected to the first capacitor C1 and the gate of the second PMOS transistor Q2; 2. Digital logic control structure, the second PMOS transistor Q2 is driven after the USB device is inserted and recognized by the logic gate (such as an inverter or edge detector).

[0058] As one implementation method, such as Figure 2 As shown, the fifth switch module 106 includes an NPN transistor Q5, a ninth resistor R9, and a tenth resistor R10. The collector of the NPN transistor Q5 is one end of the fifth switch module 106. The base of the NPN transistor Q5 is connected to one end of the ninth resistor R9 and one end of the tenth resistor R10. The other end of the ninth resistor R9 is the control terminal of the fifth switch module 106. The emitter of the NPN transistor Q5 and the other end of the tenth resistor R10 are connected together to form the other end of the fifth switch module 106.

[0059] In this circuit, NPN transistor Q5 acts as a switch for USB device insertion. When the VBUS voltage rises, its base receives a bias current. When Q5 turns on, its collector is pulled low, driving the fourth switch module 105 to turn on. This ensures that when a USB device is inserted, Q5 turns on, pulling down the gate of the second PMOS transistor Q2, which then turns on. The ninth resistor R9 limits the current supplied to the base of NPN transistor Q5 by the USB device to prevent overload; it forms a base bias voltage divider or current limiting network with the tenth resistor R10. The tenth resistor R10 connects the emitter of NPN transistor Q5 to ground; it also forms a base current path with the ninth resistor R9, ensuring the normal operation of NPN transistor Q5. The fifth switch module 106 can also have the following structures: 1. CMOS comparator input structure; 2. Logic level detection structure (CMOS gate circuit); 3. Optically coupled isolation structure; 4. Capacitively coupled trigger structure.

[0060] The working principle of this circuit is as follows: OUT_MCU is the signal output by the MCU. When idle, this pin always outputs a high level. When the heating program is executed, the MCU needs to continuously pull the OUT_MCU signal low during the heating cycle. Whenever the OUT_MCU signal is pulled low, because the voltage across the third capacitor C3 cannot change abruptly, the gate of the third PMOS transistor Q3 is also pulled low, causing Q3 to turn on. Once Q3 is on, it charges the second capacitor C2 through the fourth resistor R4. The function of the fourth resistor R4 is to limit the current during charging, preventing a large instantaneous charging current from damaging the third PMOS transistor Q3. When C2 is charged to a sufficiently high level, the NMOS transistor Q4 will turn on. Therefore, the GATE_Q1 signal will be pulled down to GND by the NMOS transistor Q4. If the heating program is normal, the OUT_MCU signal will be continuously pulled low; therefore, the GATE_Q1 signal remains low during the heating process.

[0061] When the heating program malfunctions, the OUT_MCU signal may remain high or low. If the OUT_MCU signal remains at a fixed level, the third PMOS transistor Q3 will be cut off. After Q3 is cut off, the second capacitor C2 will discharge through the eighth resistor R8. Therefore, after a period of time (the time depends on the parameters of the second capacitor C2 and the eighth resistor R8), the NMOS transistor Q4 will also be cut off. From the above analysis, we can see that when the heating program is running normally, the GATE_Q1 signal is always low. At this time, regardless of whether the USB device is plugged in, the first PMOS transistor Q1 will always be on, meaning VDD≈VCC, and the MCU will work normally. When the heating program is not executed or an abnormality occurs, because the third PMOS transistor Q3 and NMOS transistor Q4 are cut off, the level of the GATE_Q1 signal is determined by the voltage division of the first resistor R1 and the fifth resistor R5. Since R5 ≥ 20R1, if a USB device is plugged in for charging, the VBUS signal will be high. At this time, the NPN transistor Q5 will conduct, and the VBUS_CHK signal will change from high to low. At the instant the VBUS_CHK signal changes from high to low, because the voltage across the first capacitor C1 cannot change abruptly, therefore... The gate of the second PMOS transistor Q2 will also be momentarily pulled low, and Q2 will conduct for a period of time (this time is determined by the parameters of the first capacitor C1, the third resistor R3, and the conduction threshold voltage VGSTH of the second PMOS transistor Q2). When the second PMOS transistor Q2 is turned on, the gate voltage of the first PMOS transistor Q1 is: GATE_Q1≈VCC×R5 / (R5+R1)≈VCC. Therefore, the first PMOS transistor Q1 will be turned off at this time, and the off time of the first PMOS transistor Q1 is mainly set by the conduction time of the second PMOS transistor Q2. Because the VBUS_CHK signal only has a high-level to low-level transition once at the moment the USB device is inserted, the first PMOS transistor Q1 will be turned on again after being turned off for a period of time, thus enabling the MCU to implement a power-off reset function. This circuit can implement the heating priority function during normal program operation, and at the same time implement the USB device insertion power-off reset function when idle, program stuck, or abnormal, without requiring an additional power-on reset button.

[0062] Example 2

[0063] The second aspect of this utility model provides an HBN device, which includes the power-off reset circuit and control module described in Embodiment 1.

[0064] By applying the power-off reset circuit of this utility model to HNB appliances, even if the control module fails to stop heating due to program abnormalities, it can automatically power off and reset via USB, effectively solving safety risks and improving system stability and user experience.

[0065] The above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model, and should all be included within the protection scope of this utility model.

Claims

1. A power-off reset circuit for an HBN device, characterized in that, include: The first switch module has one end connected to the power supply voltage, and its control end receives the control signal output by the control module. The second switch module has its control terminal connected to the other end of the first switch module, and one end of its terminal is grounded. The third switch module has one end connected to the power supply voltage, the other end connected to the power supply port of the control module, and its control terminal connected to the other end of the second switch module. The voltage divider module has its first end connected to the control terminal of the third switch module and its second end grounded. The fourth switch module has one end connected to the power supply voltage and the other end connected to the third terminal of the voltage divider module. The fifth switch module has one end connected to the control terminal of the fourth switch module and the other end grounded. Its control terminal is a USB interface. When the control signal output by the control module is normal, the first switch module, the second switch module and the third switch module are all turned on, and the power supply voltage supplies power to the control module. When the control signal output by the control module is abnormal, both the first and second switch modules are disconnected. When the USB interface is connected to a USB device, the fifth switch module is turned on. The fourth switch module is turned on for a first preset time and then turned off. The voltage divider module divides the power supply voltage for a first preset time and then stops dividing the voltage. The third switch module is turned off for a first preset time and then turned on again, so that the control module can be power-off reset.

2. The power-off reset circuit as described in claim 1, characterized in that, The control signal output by the control module is normally a periodic pulse signal output by the control module when the heating program is normal.

3. The power-off reset circuit as described in claim 1, characterized in that, The abnormal control signal output by the control module is one of continuously outputting a high-level signal and a low-level signal when the heating program is abnormal.

4. The power-off reset circuit as described in claim 2 or 3, characterized in that, The first switching module includes a third PMOS transistor, a sixth resistor, a seventh resistor, and a third capacitor. The source of the third PMOS transistor, one end of the sixth resistor, and one end of the seventh resistor are all connected to one end of the first switching module. The gate of the third PMOS transistor is connected to the other end of the sixth resistor and one end of the third capacitor, respectively. The other end of the third capacitor and the other end of the seventh resistor are all connected to the control terminal of the first switching module. The drain of the third PMOS transistor is the other end of the first switching module.

5. The power-off reset circuit as described in claim 2 or 3, characterized in that, The second switching module includes an NMOS transistor, an eighth resistor, and a second capacitor. The gate of the NMOS transistor, one end of the eighth resistor, and one end of the second capacitor are connected together to form the control terminal of the second switching module. The source of the NMOS transistor, the other end of the second capacitor, and the other end of the eighth resistor are connected together to form one end of the second switching module. The drain of the NMOS transistor is the other end of the second switching module.

6. The power-off reset circuit as described in claim 2 or 3, characterized in that, The third switching module includes a first PMOS transistor, the source of which is one end of the third switching module, the drain of which is the other end of the third switching module, and the gate of which is the control terminal of the third switching module.

7. The power-off reset circuit as described in claim 2 or 3, characterized in that, The voltage divider module includes a first resistor and a fifth resistor. One end of the first resistor is the third terminal of the voltage divider module. The other end of the first resistor and one end of the fifth resistor are connected together to form the first terminal of the voltage divider module. The other end of the fifth resistor is the second terminal of the voltage divider module.

8. The power-off reset circuit as described in claim 2 or 3, characterized in that, The fourth switching module includes a second PMOS transistor, a second resistor, a third resistor, and a first capacitor. The source of the second PMOS transistor, one end of the second resistor, and one end of the third resistor are all connected to one end of the fourth switching module. The gate of the second PMOS transistor is connected to the other end of the third resistor and one end of the first capacitor. The other end of the first capacitor and the other end of the second resistor are all connected to the control terminal of the fourth switching module. The drain of the second PMOS transistor is the other end of the fourth switching module.

9. The power-off reset circuit as described in claim 2 or 3, characterized in that, The fifth switching module includes an NPN transistor, a ninth resistor, and a tenth resistor. The collector of the NPN transistor is one end of the fifth switching module. The base of the NPN transistor is connected to one end of the ninth resistor and one end of the tenth resistor, respectively. The other end of the ninth resistor is the control terminal of the fifth switching module. The emitter of the NPN transistor and the other end of the tenth resistor are connected together to form the other end of the fifth switching module.

10. An HBN device, characterized in that, The HBN device includes the power-off reset circuit and control module as described in any one of claims 1 to 9.

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