Hybrid transistor array reliability test circuit
By designing a hybrid transistor array reliability test circuit, a comprehensive reliability test is conducted on the combined load switch using NPN transistors and PMOS transistors. This solves the problem of insufficient functional testing of hybrid transistor array combinations in existing technologies, achieving efficient screening and fault observation, and improving the efficiency and accuracy of the test.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- CHINA ZHENHUA GRP YONGGUANG ELECTRONICS CO LTD STATE OWNED NO 873 FACTORY
- Filing Date
- 2025-06-14
- Publication Date
- 2026-06-19
AI Technical Summary
Existing reliability testing methods for hybrid transistor arrays do not allow for reliability testing of the combined functionality of the product array, and the testing of individual devices requires too many power supplies and auxiliary semiconductor devices, making it difficult to effectively screen out defective devices.
A functional reliability test method was adopted to conduct a comprehensive reliability test on the NPN transistor and PMOS transistor combination load switch. A hybrid transistor array reliability test circuit was designed, including a constant current source protection circuit, a short circuit indicator circuit and a working indicator circuit, to achieve simultaneous screening and fault observation of the hybrid transistor array.
It enables simultaneous screening and fault observation of hybrid transistor arrays, and has short-circuit protection and operation indication functions, which improves the efficiency and accuracy of the test and reduces the need for power supply and auxiliary devices.
Smart Images
Figure CN224383398U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of semiconductor device testing technology, and more specifically to the field of transistor array device testing technology. In particular, it relates to a hybrid transistor array reliability test circuit. Background Technology
[0002] A hybrid transistor array circuit (referred to as the product) is composed of a combination of transistor modules (single-transistor or composite-transistor) and MOSFET modules (single-transistor or composite-transistor), and is used as a load switch. A hybrid transistor array circuit composed of single transistors is shown below. Figure 1 As shown, it consists of an NPN transistor and a PMOS transistor. In circuit applications, NPN transistors and PMOS transistors are often used together as load switches. It is suitable for control signals that are high level and is often used in MCU control circuits. The MCU's IO output voltage is 3.3V. If it is used directly to drive the MOSFET, it may cause the MOSFET to be in the initial stage of the amplification region. Therefore, the MCU controls the load device by controlling the NPN transistor and then the PMOS transistor.
[0003] During the use of semiconductor devices, devices with potential defects or manufacturing flaws will fail under normal operating conditions over time and stress, affecting subsequent normal use. Therefore, targeted and accelerated aging screening is necessary through preliminary reliability electrical stress testing to eliminate potentially defective devices before use, ensuring the reliability of semiconductor devices during subsequent use. Currently, a common aging screening method for hybrid transistor devices is an independent DC power aging scheme: that is, aging at room temperature (…). Under these conditions, power P=V×I is applied to transistors and MOSFETs respectively. The power generates stress, which exposes and eliminates faulty devices, thereby achieving the purpose of screening.
[0004] Existing reliability testing methods lack the capability to perform reliability testing on the combined functionality of product arrays. Their testing methods are too simplistic, and conducting reliability tests on NPN transistors and PMOS transistors separately requires excessive power supplies and auxiliary semiconductor devices, making it difficult to observe damage during the product screening process. This invention proposes a functional reliability testing method using hybrid transistor combinations, rather than targeting individual devices. It combines NPN transistors and PMOS transistors as a load switch for functional reliability testing while ensuring the screening effectiveness achievable through independent reliability testing.
[0005] In view of this, the present invention is hereby proposed. Summary of the Invention
[0006] The technical problem to be solved by this utility model is to solve the problem that the existing technology of separate independent power aging results in too many power supplies and testing facilities, which cannot cover the use environment to completely screen out product reliability defects.
[0007] The inventive concept of this utility model is: instead of conducting reliability tests on individual devices separately, it uses a functional reliability testing method to perform comprehensive functional reliability tests on a load switch consisting of an NPN transistor and a PMOS transistor. Specifically, the concept is as follows:
[0008] (1) The two transistors in the hybrid transistor undergo power aging simultaneously to achieve the screening purpose of independent steady-state DC power aging.
[0009] (2) Combine reliability testing with actual use for screening design, and combine hybrid transistors (NPN transistors and PMOSFETs) with load switches for reliability testing.
[0010] (3) The transistor screening failure can be observed directly in the reliability test circuit and eliminated immediately. During the screening process, any transistor in the mixed transistor array that is damaged can be directly judged.
[0011] Therefore, this utility model provides a hybrid transistor array reliability test circuit, such as... Figure 2 As shown.
[0012] It includes transistor modules, MOSFET modules, voltage divider circuits, DC load feedback circuits, transistor load biasing circuits, MOSFET load biasing circuits, constant current source protection circuits, short circuit indicator circuits, and operating indicator circuits.
[0013] One end of the constant current source protection circuit is connected to the power supply VCC terminal, and the other end is connected to the positive terminal of the voltage divider circuit, the positive terminal of the transistor load bias circuit, and the positive terminal of the MOSFET load bias circuit. The short-circuit indicator circuit is connected in parallel in the positive direction across the two ends of the constant current source protection circuit, and the working indicator circuit is connected in parallel in the positive direction across the two ends of the MOSFET load bias circuit. The collector terminal of the transistor module is connected to the negative terminal of the transistor load bias circuit and the gate terminal of the MOSFET module. The base terminal of the transistor module is connected to the output terminal of the voltage divider circuit. The emitter terminal of the transistor module is connected to the positive terminal of the DC load feedback circuit. The drain terminal of the MOSFET module is connected to the negative terminal of the MOSFET load bias circuit. The source terminal of the MOSFET module is connected to the negative terminal of the voltage divider circuit, the negative terminal of the DC load feedback circuit, and the GND ground terminal.
[0014] The constant current source protection circuit only enters the constant current protection state when the test circuit or the hybrid transistor array is short-circuited.
[0015] The short-circuit indicator circuit only enters the indicating state when the constant current source protection circuit enters the constant current protection state.
[0016] The operation indicator circuit only enters the indicator state when the test circuit or MOSFET module is open-circuited or has poor contact. Beneficial effects
[0017] (1) It effectively replaces the traditional hybrid transistor independent steady-state power DC aging screening. The reliability test method of hybrid crystal array simultaneously realizes power aging screening and functional aging screening, and simulates the load switching function of the hybrid crystal array of transistor module and MOS module.
[0018] (2) The reliability test circuit of the hybrid transistor array has short circuit protection function, normal operation indication function and working circuit current detection function, which facilitates real-time monitoring of the circuit working current.
[0019] (3) The constant current source protection circuit is adopted, which makes the circuit work more efficiently and stably.
[0020] (4) Independent unit design for reliability testing of hybrid transistor arrays is carried out to facilitate the parallel batch unit reliability test circuit of hybrid transistor arrays. The reliability test equipment of hybrid transistor arrays is reasonably designed and manufactured from the perspectives of heat dissipation, wiring and various usage conditions.
[0021] This invention can be widely applied to reliability testing techniques for transistor array devices. Attached Figure Description
[0022] Figure 1 This is a schematic diagram of the principle structure of a hybrid transistor load switching circuit.
[0023] Figure 2 This is a schematic diagram of the principle of reliability testing for hybrid transistor arrays.
[0024] Figure 3 This is a schematic diagram of the circuit structure for a reliability test of a hybrid transistor array. Detailed Implementation
[0025] like Figure 1-3 As shown, taking a hybrid transistor array product composed of a single NPN transistor and a single PMOS transistor as an example, the specific implementation of the hybrid transistor array reliability test circuit is as follows:
[0026] The hybrid transistor array reliability test circuit includes an NPN transistor Q1, a PMOS transistor Q2, constant current transistors CRD1, CRD2, and CRD3, resistors R3, R4, R5, R6, and R7, and light-emitting diodes LED1 and LED2.
[0027] The positive terminals of CRD1 and CRD2 are connected to the positive power supply terminal. The negative terminal of CRD2 is connected to the positive terminal of LED1. The negative terminal of CRD1 is connected to one end of R5, one end of R4, the negative terminal of LED1, one end of R3, and the positive terminal of CDR3. The other end of R5 is connected to one end of R6 and the base of Q1. The collector of Q1 is connected to the other end of R4 and the gate of Q2. The emitter of Q1 is connected to one end of R7. The other end of R7 is connected to the other end of R6, the source of Q2, and the GND terminal. The drain of Q2 is connected to the other end of R3 and the negative terminal of LED2. The positive terminal of LED2 is connected to the negative terminal of CDR3.
[0028] The constant current transistor CRD1 constitutes a constant current source protection circuit, and the constant current of CRD1 is 30 to 100 times that of the constant current of CRD2 and CRD3.
[0029] The CRD2 and LED1 constitute a short-circuit indicator circuit.
[0030] The CRD3 and LED2 constitute a working indicator circuit.
[0031] The resistors R4 and R5 form a voltage divider circuit.
[0032] R6 forms a transistor load biasing circuit.
[0033] R7 forms a transistor DC negative feedback circuit.
[0034] R3 forms the load bias circuit for the PMOS transistor.
[0035] 1. For NPN transistors
[0036] When performing power aging reliability tests on transistors, the requirement that P=VCE×IC must be met, meaning the transistor must operate in the amplification region. Therefore, the operating current and the junction voltage difference of the transistor CE can be determined based on the transistor's electrical characteristics: amplification factor β, operating current Ic, and rated power P. Based on the determined operating current IC and transistor voltage difference VCE, the relevant test circuit can then be designed.
[0037] The amplification factor of a transistor is greatly affected by environmental factors: when the ambient temperature rises, the current amplification factor β of the transistor increases, i.e., IC (IC=βIB) increases, the voltage division of the transistor's main circuit resistor increases, and the transistor voltage drop VCE decreases; when the ambient temperature decreases, the current amplification factor β of the transistor decreases, i.e., IC decreases, the voltage division of the transistor's main circuit resistor decreases, and the transistor voltage drop VCE increases. During reliability testing, the transistor generates heat due to its work, thus the transistor's power is uncertain. To prevent the transistor's heat from causing instability in relevant dynamic electrical parameters, or even affecting the normal operation of the circuit, a voltage divider current negative feedback operating point stabilization circuit is used, consisting of resistors R4, R5, R6, and R7, with the following operating mode:
[0038] (1) The operating point of the transistor is fixed: the base voltage VB of the transistor is fixed by the voltage divider of resistors R5 and R6, which satisfies the formula .
[0039] (2) Resistor R7 is a DC negative feedback resistor. The principle of negative feedback is: the transistor's operating current In this configuration, IB is stable, and VBE is fixed at 0.7V. When the ambient temperature rises, the transistor current IC increases, i.e., IE increases, and the voltage VR5 across resistor R5 increases. Since the voltage divider between resistors R5 and R6 is fixed, i.e., VB remains unchanged, and since VB - VBE = VR5, VBE decreases. The transistor base current IB decreases, and since IC = βIB, the operating current IC decreases. Therefore, when the temperature rises, the transistor's operating current is adjusted by resistor R7, achieving a negative feedback regulation. Thus, the transistor's operating point is not affected by temperature changes at this time.
[0040] (3) Resistor R4 is a voltage divider resistor: Since the emitter voltage VE of the transistor is fixed, the operating current... For a fixed main transistor, the voltage drop VCE ≈ VCC - R4IE - VE, meaning the transistor voltage drop is determined by the voltage division value of resistor R4. At the same time, the voltage drop of resistor R4 needs to be designed in conjunction with the required transistor voltage drop VDS of the downstream PMOS transistor.
[0041] 2. For PMOS transistors
[0042] When performing power aging reliability testing on a PMOS transistor, the following condition must be met: P = VDS × ID. This is based on the electrical connection between an NPN transistor and a PMOS transistor as a load switch. Figure 2 As shown, the gate of the PMOS transistor is connected to the collector of the NPN transistor. Resistors R3 and R4 determine the operating state of the PMOS transistor. Its working principle is as follows:
[0043] (1) Resistor R4 determines the source follower working voltage of PMOS transistor: When the transistor is working in the amplification region, the voltage drop of resistor R4 causes the gate-source voltage drop VGS of PMOS transistor to be greater than the threshold voltage Vth of PMOS transistor. At this time, PMOS transistor is in the source follower working state, and its source and gate voltages differ by a threshold voltage.
[0044] (2) Resistor R3 determines the PMOS operating current: Since the voltage across resistor R4 is fixed and VR3 = VR4 - Vth, the voltage across resistor R3 is fixed. The operating current of the PMOS transistor is controlled by selecting the resistance value of resistor R3, i.e., the operating current of the PMOS transistor satisfies .
[0045] 3. For protection circuits
[0046] Considering the need for batch and repetitive reliability testing, the reliability testing equipment must be capable of repeated screening and multiple uses. When a defective product experiences a short circuit, it can cause excessive voltage drop and current in the circuit, leading to over-operation and affecting the normal operation of subsequent equipment. Therefore, a constant current transistor within a safe operating current range is added for constant current protection. When the product short-circuits, this constant current transistor operates, limiting the overall circuit current and extending the lifespan of auxiliary semiconductor devices in the equipment.
[0047] 4. For indicator circuits
[0048] To provide a more intuitive view of product reliability testing, short-circuit, open-circuit, and normal operation indicator lights were added to the circuit, achieving the desired level of observability. When any transistor inside the product experiences a short circuit and the constant current protection is activated, a red light flashes as a warning; when the product is undergoing normal reliability screening, a green light remains constantly on; and when the product experiences poor contact or an open circuit, the green light indicating normal operation turns off.
[0049] The working principle of the test circuit is as follows:
[0050] In the experimental circuit: Q1 and Q2 are low-power transistors; CRD1 has a constant current of 40mA, CRD2 has a constant current of 1mA, and CRD3 has a constant current of 1mA; R3 has a resistance of 1.4KΩ, R4 has a resistance of 1.2KΩ, R5 has a resistance of 3.9KΩ, R6 has a resistance of 270Ω, and R7 has a resistance of 82Ω; the power supply voltage of the experimental circuit is 28V. LED1 is a red LED, and LED2 is a green LED.
[0051] 1. When the transistor is working normally, the operating points are as follows:
[0052] (1) Base voltage VB: The base voltage of the transistor is fixed by the voltage divider formed by resistors R3 and R4. .
[0053] (2) Emitter voltage VE: Transistor emitter voltage VE = VB - VBE = 1.68 - 0.7 = 0.98V.
[0054] (3) Operating current IE: .
[0055] (4) Working voltage VCE: VCE=VCC-VE-VR4=26-0.98-12×1.2=10.62V.
[0056] At this point, the NPN transistor meets the power aging requirement, and its power is P=VCE×IE=10.62×12≈127mA.
[0057] When the PMOS transistor is working normally, the operating currents are as follows:
[0058] (1) PMOS transistor voltage drop VDS: VDS=VR4-Vth=12×1.2+1.6=16V.
[0059] (2) PMOS transistor operating current ID: .
[0060] At this point, the PMOS transistor meets the power aging requirement, and its power is P = VDS × ID = 16 × 8.3 = 132mW.
[0061] 2. Abnormal working status:
[0062] When the transistor is short-circuited, the VCE voltage drop is 0, and the main circuit current... As the current increases, the 40mA constant current tube enters the constant current operating region, the voltage drop across its two ends increases, and the short circuit alarm indicator light remains on.
[0063] When the transistor is open-circuited, there is no voltage difference between the gate and source of the PMOS transistor, the PMOS transistor is turned off, and the working indicator light is normally closed.
[0064] When the PMOS transistor is short-circuited, the VDS voltage drop is 0, and the current through resistor R3 is... As the current increases, the 40mA constant current tube enters the constant current operating region, the voltage drop across its two ends increases, and the short circuit alarm indicator light remains on.
[0065] When the PMOS transistor is open-circuited, the resistor R3 circuit is open, and there is no current. At this time, the indicator light is normally closed. The truth table of the reliability test circuit state in the embodiment is shown in Table 2.
[0066] Table 2 Truth Table of Reliability Test Circuit State in Example 2
[0067]
[0068] If any transistor in the hybrid transistor array experiences a short circuit or open circuit, the reliability testing equipment will not function properly. Furthermore, the indications will differ depending on whether the fault is short-circuited or open-circuited, which facilitates subsequent product failure analysis.
[0069] The voltage divider circuit can be a resistor voltage divider circuit or other voltage divider circuits.
[0070] The transistor load biasing circuit and the MOSFET load biasing circuit can be resistive load circuits or active load circuits.
[0071] The DC load feedback circuit is a resistive feedback circuit or an active feedback circuit.
[0072] The constant current source protection circuit can be a constant current tube circuit or other constant current circuits.
[0073] The short-circuit indicator circuit and the working indicator circuit can be LED display circuits or other display circuits.
[0074] Q1 can be a PNP transistor and Q2 can be an NMOS transistor; the power supply polarity of the test circuit can be changed.
[0075] Beneficial effects:
[0076] ① It effectively replaces the traditional independent steady-state power DC aging screening of hybrid transistors. The reliability testing method of hybrid crystal arrays simultaneously realizes power aging screening and functional aging screening, and simulates the load switching function of NPN transistors and PMOS transistors.
[0077] ② The reliability test circuit of the hybrid transistor array has short-circuit protection, normal operation indication and working circuit current detection functions: resistors R3 and R7 are working current resistors, which are high-precision and low-temperature drift resistors to facilitate real-time monitoring of the circuit working current.
[0078] ③ A constant current transistor is used to design the circuit for short-circuit protection instead of a fuse, avoiding the need to replace a blown fuse and making the circuit work more efficiently and stably.
[0079] ④ Independent unit design for hybrid transistor array reliability testing is carried out to facilitate the parallel connection of multiple (batch) unit hybrid transistor array reliability test circuits. The hybrid transistor array reliability test equipment is reasonably designed and manufactured from the perspectives of heat dissipation, wiring and various usage conditions.
[0080] Finally, it should be noted that the above embodiments are merely examples for clear illustration. This utility model includes, but is not limited to, the above embodiments, and it is neither necessary nor possible to exhaustively describe all implementation methods. Those skilled in the art can make other variations or modifications based on the above description. All implementation schemes that meet the requirements of this utility model are within the protection scope of this utility model.
Claims
1. A hybrid transistor array reliability test circuit, characterized in that: It includes transistor modules, MOSFET modules, voltage divider circuits, DC load feedback circuits, transistor load biasing circuits, MOSFET load biasing circuits, constant current source protection circuits, short circuit indicator circuits, and operating indicator circuits. One end of the constant current source protection circuit is connected to the power supply VCC terminal, and the other end is connected to the positive terminal of the voltage divider circuit, the positive terminal of the transistor load bias circuit, and the positive terminal of the MOSFET load bias circuit. The short-circuit indicator circuit is connected in parallel in the positive direction across the two ends of the constant current source protection circuit, and the working indicator circuit is connected in parallel in the positive direction across the two ends of the MOSFET load bias circuit. The collector terminal of the transistor module is connected to the negative terminal of the transistor load bias circuit and the gate terminal of the MOSFET module. The base terminal of the transistor module is connected to the output terminal of the voltage divider circuit. The emitter terminal of the transistor module is connected to the positive terminal of the DC load feedback circuit. The drain terminal of the MOSFET module is connected to the negative terminal of the MOSFET load bias circuit. The source terminal of the MOSFET module is connected to the negative terminal of the voltage divider circuit, the negative terminal of the DC load feedback circuit, and the GND ground terminal.
2. The hybrid transistor array reliability test circuit as described in claim 1, characterized in that: The transistor module is a composite transistor or a single transistor.
3. The hybrid transistor array reliability test circuit as described in claim 1, characterized in that: The MOS transistor module is a composite MOS transistor or a single MOS transistor.
4. The hybrid transistor array reliability test circuit as described in claim 1, characterized in that: The voltage divider circuit is a resistive voltage divider circuit or an active voltage divider circuit.
5. The hybrid transistor array reliability test circuit as described in claim 1, characterized in that: The transistor load biasing circuit and the MOSFET load biasing circuit are resistive load circuits or active load circuits.
6. The hybrid transistor array reliability test circuit as described in claim 1, characterized in that: The DC load feedback circuit is a resistive feedback circuit or an active feedback circuit.
7. The hybrid transistor array reliability test circuit as described in claim 1, characterized in that: The constant current source protection circuit is a constant current tube circuit, and the short circuit indicator circuit and the working indicator circuit are LED display circuits.
8. The hybrid transistor array reliability test circuit as described in claim 1, characterized in that: Includes NPN transistor Q1, PMOS transistor Q2, constant current transistors CRD1, CRD2, and CRD3, resistors R3, R4, R5, R6, and R7, and light-emitting diodes LED1 and LED2; The positive terminals of CRD1 and CRD2 are connected to the positive power supply terminal, the negative terminal of CRD2 is connected to the positive terminal of LED1, the negative terminal of CRD1 is connected to one end of R5, one end of R4, the negative terminal of LED1, one end of R3, and the positive terminal of CDR3, the other end of R5 is connected to one end of R6 and the base of Q1, the collector of Q1 is connected to the other end of R4 and the gate of Q2, the emitter of Q1 is connected to one end of R7, the other end of R7 is connected to the other end of R6, the source of Q2, and the GND terminal, the drain of Q2 is connected to the other end of R3 and the negative terminal of LED2, and the positive terminal of LED2 is connected to the negative terminal of CDR3. The constant current transistor CRD1 constitutes a constant current source protection circuit, and the constant current of CRD1 is 30 to 100 times that of the constant current of CRD2 and CRD3. The CRD2 and LED1 constitute a short-circuit indicator circuit; The CRD3 and LED2 constitute a working indicator circuit; The resistors R4 and R5 form a voltage divider circuit; R6 forms a transistor load biasing circuit; R7 forms a transistor DC negative feedback circuit; R3 forms the load bias circuit for the PMOS transistor.
9. The hybrid transistor array reliability test circuit as described in claim 8, characterized in that: Q1 and Q2 are low-power transistors. The constant current values of CRD1, CRD2, and CRD3 are 40mA, 1mA, and 1mA respectively. The resistance values of R3, R4, R5, R6, and R7 are 1.4KΩ, 1.2KΩ, 3.9KΩ, 270Ω, and 82Ω respectively. The power supply voltage of the test circuit is 28V. LED1 is a red LED and LED2 is a green LED.
10. The hybrid transistor array reliability test circuit as described in claim 8, characterized in that: Q1 is a PNP transistor and Q2 is an NMOS transistor.