Display device and electronic device including the same

Abstract

The disclosure provides a display device and an electronic device including the same. The display device includes a display panel, a first alignment mark in a first non-circuit region of the display panel and having a closed curve shape that surrounds at least a portion of the first non-circuit region, a display driver connected to the display panel, and a second alignment mark in a second non-circuit region of the display driver and surrounded by the second non-circuit region.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0081867, filed on June 24, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to a display device capable of improving the ability to distinguish alignment marks, and an electronic device including the display device. Background Technology

[0004] Because organic light-emitting diode (OLED) displays are self-emitting and do not require a separate light source like liquid crystal displays, their thickness and weight can be reduced. Furthermore, OLED displays are gaining attention as the next generation of displays for televisions, monitors, and portable electronic devices due to their superior characteristics, such as low power consumption, high brightness, and high response time. Utility Model Content

[0005] This disclosure provides a display device capable of improving the ability to distinguish alignment marks, and an electronic device including the display device.

[0006] According to one or more embodiments of the present disclosure, a display device is provided, the display device comprising: a display panel; a first alignment mark in a first non-circuit region of the display panel and having a closed curved shape surrounding at least a portion of the first non-circuit region; a display driver connected to the display panel; and a second alignment mark in a second non-circuit region of the display driver and surrounded by the second non-circuit region.

[0007] The first and second alignment marks may contain metal.

[0008] The first alignment mark can be located at the edge of the first non-circuit region.

[0009] The second alignment mark can be located at the center of the second non-circuit region.

[0010] The second non-circuit region can have a larger area than the first non-circuit region.

[0011] The internal region defined by the first alignment mark can have a larger area than the area of ​​the second alignment mark.

[0012] The internal region defined by the first alignment mark may have a smaller area than the area of ​​the second non-circuit region.

[0013] In the plan view, the first alignment mark can surround the insulating film of the first non-circuit region.

[0014] In the plan view, the second alignment mark can be surrounded by the insulating film of the second non-circuit region.

[0015] In a plan view, the first alignment mark can surround the second alignment mark.

[0016] In the plan view, the edge of the second non-circuit region may surround the first alignment mark.

[0017] The display device may further include a first dummy pattern in the display panel and on a different layer from the first alignment mark.

[0018] The first dummy pattern can be closer to the substrate of the display panel than the first alignment mark.

[0019] In the plan view, the first dummy pattern can be surrounded by the first alignment mark.

[0020] In the plan view, the first dummy pattern may be adjacent to the corner of the first alignment mark.

[0021] In the plan view, the first dummy pattern can be in the remainder of the inner area defined by the first alignment mark, excluding the corner of the first alignment mark.

[0022] The first alignment mark may include: an outer pattern at the edge of the first non-circuit region; and a protruding pattern protruding from the outer pattern.

[0023] The display device may further include a second dummy pattern in the display driver and on a different layer from the second alignment mark.

[0024] The second dummy pattern can be closer to the substrate of the display driver than the second alignment mark.

[0025] The display device may further include a third alignment mark in the display panel, adjacent to the first alignment mark.

[0026] The third alignment mark can be adjacent to the edge of the display driver.

[0027] The display device may further include an auxiliary alignment mark adjacent to one side of the second alignment mark in the second non-circuit region.

[0028] The first alignment mark can be quadrilateral in shape.

[0029] The second alignment mark can be cross-shaped.

[0030] According to one or more embodiments of the present disclosure, an electronic device is provided, comprising: a processor; a battery; and a display device as described above, connected to the processor and the battery.

[0031] Electronic devices may include smartphones, televisions, monitors, tablet computers, electric vehicles, mobile phones, tablet personal computers (PCs), mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, ultra-mobile PCs (UMPCs), laptop computers, billboards, Internet of Things (IoT) devices, smartwatches, watch phones, or head-mounted displays (HMDs).

[0032] The display device according to this disclosure improves the ability to distinguish alignment marks. Therefore, even when the display device is manufactured on a wafer comprising many conductive layers, the first alignment mark of the display panel and the second alignment mark of the display driver can be accurately identified by an imaging device. Thus, the alignment operation between the display panel and the display driver can be easily performed.

[0033] The effects of this disclosure are not limited to those described above, and other effects not described herein will become apparent to those skilled in the art from the following description. Attached Figure Description

[0034] The above and other aspects and features of this disclosure will become more apparent from the detailed description of embodiments thereof with reference to the accompanying drawings, in which:

[0035] Figure 1 This is a perspective view showing a display device according to one or more embodiments;

[0036] Figure 2 This is a plan view illustrating a display unit of a display device according to one or more embodiments;

[0037] Figure 3 This is a block diagram illustrating a display panel and a display driver according to one or more embodiments;

[0038] Figure 4 It is shown Figure 3 A layout diagram of one or more embodiments of the display area;

[0039] Figure 5 The diagram shows along Figure 4 A cross-sectional view of an example display panel taken by line I-I';

[0040] Figure 6 yes Figure 2 A magnified view of region A1;

[0041] Figure 7 yes Figure 6 A magnified view of region A2;

[0042] Figure 8It is only selectively shown Figure 7 A view of the display panel, first alignment mark, and pads;

[0043] Figure 9 It is only selectively shown Figure 7 A view of the display driver, second alignment mark, and terminals;

[0044] Figure 10 It is along Figure 7 A cross-sectional view taken from line II-II';

[0045] Figure 11 It is a plan view of a display panel according to one or more embodiments;

[0046] Figure 12 This is a plan view of a display driver according to one or more embodiments;

[0047] Figure 13 When Figure 11 The display panel and Figure 12 When the display drivers are connected to each other, along Figure 11 and Figure 12 A cross-sectional view taken from line III-III';

[0048] Figure 14 It is a plan view of a display panel according to one or more embodiments;

[0049] Figure 15 When Figure 14 The display panel and Figure 9 When the display drivers are connected to each other, along Figure 14 A cross-sectional view taken from line IV-IV';

[0050] Figure 16 It is a plan view of a display panel according to one or more embodiments;

[0051] Figure 17 It is a plan view of a display panel according to one or more embodiments;

[0052] Figure 18 It is a plan view of a display panel according to one or more embodiments;

[0053] Figure 19 It is a plan view of a display panel according to one or more embodiments;

[0054] Figure 20 It is a plan view of a display panel according to one or more embodiments;

[0055] Figure 21 It is a plan view of a display panel according to one or more embodiments;

[0056] Figure 22 It is a plan view of a display panel according to one or more embodiments;

[0057] Figure 23 It is a plan view of a display panel according to one or more embodiments;

[0058] Figure 24 It is a plan view of a display panel according to one or more embodiments;

[0059] Figure 25 It is a plan view of a display panel according to one or more embodiments;

[0060] Figure 26 This is a plan view of a display driver according to one or more embodiments;

[0061] Figure 27 This is a plan view of a display driver according to one or more embodiments;

[0062] Figure 28 This is a plan view of a display driver according to one or more embodiments;

[0063] Figure 29 This is a plan view of a display driver according to one or more embodiments;

[0064] Figure 30 This is a plan view of a display driver according to one or more embodiments;

[0065] Figure 31 According to one or more other embodiments Figure 2 A magnified view of region A1;

[0066] Figure 32 yes Figure 31 A magnified view of area A3;

[0067] Figures 33 to 39 This is a view illustrating a method of manufacturing a display device according to one or more embodiments;

[0068] Figure 40 This is a view illustrating a method of manufacturing a display device according to one or more embodiments;

[0069] Figure 41 This is a block diagram of an electronic device according to one embodiment; and

[0070] Figure 42 , Figure 43 and Figure 44 These are schematic diagrams of electronic devices according to various embodiments. Detailed Implementation

[0071] By referring to the detailed description of the various embodiments and the accompanying drawings, aspects of some embodiments of this disclosure and methods for implementing these aspects can be more readily understood. The described embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the aspects of this disclosure to those skilled in the art. Accordingly, redundant processes, elements, and techniques that are irrelevant or unrelated to the description of the embodiments, or that are not essential for a person of ordinary skill in the art to fully understand the aspects of this disclosure, may be omitted. Unless otherwise stated, the same reference numerals, characters, or combinations thereof denote the same elements throughout the drawings and written description, and therefore, repeated descriptions thereof may be omitted.

[0072] The described embodiments may have various modifications and may be embodied in different forms, and should not be construed as being limited to the embodiments set forth herein. The use of the words “can,” “may,” or “may not” in describing one or more embodiments corresponds to one or more embodiments of this disclosure.

[0073] Those skilled in the art will appreciate that, in view of the overall content of this disclosure, each suitable feature of the various embodiments of this disclosure may be combined in part or in whole, or combined with each other, and may be technically interlocked and operated in various suitable ways, and each embodiment may be implemented independently of each other or in combination with each other in any suitable way, unless otherwise stated or implied.

[0074] In the accompanying drawings, the relative dimensions of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In other words, this disclosure is not limited to the dimensions and thicknesses of elements in the drawings, as they are arbitrarily depicted for ease of description. Furthermore, the use of crosshairs and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless otherwise specified, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for particular materials, material properties, sizes, proportions, commonalities among the illustrated elements, and / or any other characteristics, properties, or characteristics of the elements.

[0075] Various embodiments are described herein with reference to cross-sectional diagrams as schematic illustrations of examples and / or intermediate structures. Thus, variations in the illustrated shapes will be anticipated, for example, due to manufacturing techniques and / or tolerances. Furthermore, the specific structural or functional descriptions disclosed herein are merely illustrative and intended to describe the various embodiments according to the concept of this disclosure. Therefore, the embodiments disclosed herein should not be construed as limited to the illustrated shapes of these elements, layers, or regions, but will include deviations in shape caused, for example, by manufacturing processes.

[0076] For example, an injection zone illustrated as rectangular will typically have rounded or curved features and / or a gradient of injection concentration at its edges rather than a binary variation from the injection zone to the non-injection zone. Similarly, a buried zone formed by injection may result in some injection occurring in the area between the buried zone and the surface through which the injection takes place.

[0077] For ease of explanation, spatial relative terms such as “below,” “under,” “lower,” “lower side,” “below,” “above,” “above,” “higher,” “upper side,” and “side” (e.g., as in “sidewall”) are used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). It will be understood that, in addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the figures is flipped, an element described as “below,” “under,” or “below” other elements or features will subsequently be oriented “above” that other element or feature. Thus, the example terms “below” and “below” can cover both upper and lower orientations. The device may be oriented in other ways (e.g., rotated 90 degrees or otherwise), and the spatial relative descriptors used herein should be interpreted accordingly. Similarly, when a first part is described as being arranged “on” a second part, this means that the first part is arranged above or below the second part, and not limited to being arranged above it based on the direction of gravity.

[0078] Furthermore, the term "in a plan view" means when viewing a portion of the object from above, and the term "in a schematic cross-sectional view" means when viewing a schematic cross-section obtained by vertically cutting a portion of the object from the side. The terms "overlapping" or "overlapping" mean that the first object may be above, below, or to the side of the second object, and vice versa. Additionally, the term "overlapping" can include stacking, facing or confronting, extending over, covering or partially covering, or any other suitable terminology as will be understood and appreciated by one of ordinary skill in the art. The expression "non-overlapping" can include meanings such as "separated from," "separated from," or "offset from," and any other suitable equivalent expression as will be understood and appreciated by one of ordinary skill in the art. The terms "facing" and "confronting" can mean that the first object may be directly or indirectly opposite the second object. Where a third object is located between the first and second objects, the first and second objects can be understood as indirectly opposite each other, although still facing each other.

[0079] It will be understood that when a component, layer, area, or part (e.g., device, apparatus, circuit, wiring, electrode, terminal, conductive film, etc.) is referred to as "formed on," "on," "connected to," or "(operably, functionally, or communicatively) coupled to" another component, layer, area, or part, it can be directly formed on, on, directly connected to, or coupled to that other component, layer, area, or part, or indirectly formed on, on, indirectly connected to, or coupled to that other component, layer, area, or part, such that one or more intermediate components, layers, areas, or parts may exist. Furthermore, this can be collectively referred to as direct or indirect coupling or connection, and integral or non-integral coupling or connection. For example, when a layer, area, or part is referred to as "electrically connected" or "electrically coupled" to another layer, area, or part, it can be directly electrically connected or coupled to that other layer, area, or part, or one or more intermediate layers, areas, or parts may exist. One or more intermediary components may include switches, transistors, resistors, inductors, capacitors, and / or diodes, etc. Accordingly, the connections are not limited to those illustrated in the accompanying drawings or described in the detailed description, and may also include other types of connections. In describing embodiments, the term "connection" indicates an electrical connection unless explicitly described as a direct connection, and "direct connection / direct coupling" or "directly on" means that one component is directly connected to or coupled to another component or is directly on another component without any intermediary components.

[0080] Furthermore, in this specification, when a portion of a layer, film, region, or plate is formed on another portion, the forming direction is not limited to the upward direction, but includes forming the portion on a side surface or in the downward direction. Conversely, when a portion of a layer, film, region, or plate is formed "below" another portion, this includes not only the case where the portion is "directly" "below" the other portion, but also the case where there is another portion between the two portions. Similarly, other expressions describing the relationship between components, such as "between," "directly between," or "adjacent to," and "directly adjacent to," can be interpreted similarly. It will be understood that when an element or layer is referred to as "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there may be one or more intervening elements or layers.

[0081] For the purposes of this disclosure, when expressions such as “at least one of…”, “any one of…”, or “one or more of…” follow the list of elements, they modify the entire list of elements and do not modify any individual element in the list. For example, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as any combination of only X, only Y, only Z, two or more of X, Y, and Z (such as, for example, XYZ, XY, YZ, and XZ) or any variations thereof. Similarly, the expression “at least one of A and B” can include A, B, or A and B. As used herein, “or” generally means “and / or”, and the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, the expression “A and / or B” can include A, B, or A and B. Similarly, when expressions such as “at least one of…”, “a plurality of…”, “one of…”, and other prepositional phrases follow or precede the list of elements, they modify the entire list of elements and do not modify any individual element in the list. Unless otherwise stated, when “C to D” is used, it means above C and below D.

[0082] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, areas, layers, and / or segments, these elements, components, areas, layers, and / or segments should not be limited by these terms. These terms do not correspond to a specific order, position, or priority, and are used only to distinguish one element, component, area, region, layer, segment, or part from another. Therefore, the first element, component, area, layer, or segment described below may be referred to as a second element, component, area, layer, or segment without departing from the spirit and scope of this disclosure. Describing an element as a “first” element may not require or imply the existence of a second element or other elements. The terms “first,” “second,” etc., may also be used herein to distinguish different categories or sets of elements. For the sake of brevity, the terms “first,” “second,” etc., may respectively represent “first class (or first set),” “second class (or second set),” etc.

[0083] In the examples, the x-axis, y-axis, and / or z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction, and / or the third direction.

[0084] The terminology used herein is for the purpose of describing embodiments only and is not intended to limit this disclosure. As used herein, the singular form “a” is intended to include the plural form as well as the plural form, unless the context clearly indicates otherwise. It will be further understood that, when used in this specification, the terms “comprising,” “having,” “including,” and variations thereof specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0085] When one or more embodiments can be implemented differently, a particular process sequence can be performed differently than the described sequence. For example, two consecutively described processes can be performed substantially simultaneously or in the reverse order of their description.

[0086] As used herein, the terms “substantially,” “about,” “approximately,” and similar terms are used as terms of approximation and not as terms of degree, and are intended to explain the inherent bias in a measured or calculated value as would be recognized by one of ordinary skill in the art. For example, “substantially” can include a range of + / - 5% for the corresponding value. Taking into account the measurement in question and the error associated with the measurement of a particular quantity (i.e., limitations of the measurement system), “about” or “approximately” as used herein includes the stated value and means within an acceptable range of deviation for that particular value as determined by one of ordinary skill in the art. For example, “about” can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5% of the stated value. Further, the use of “may” when describing embodiments of this disclosure refers to “one or more embodiments of this disclosure.” Additionally, the expression “identical” can mean “substantially identical.” In other words, the expression “identical” can include a range that is tolerable by one of ordinary skill in the art. Other expressions may also omit the expression “substantially.”

[0087] In some embodiments, well-known structures and arrangements may be described in the accompanying drawings with respect to one or more functional blocks (e.g., block diagrams), units, and / or modules to avoid unnecessarily obscuring various embodiments. Those skilled in the art will understand that such blocks, units, and / or modules are physically implemented by logic circuitry, individual components, microprocessors, hardwired circuitry, memory elements, wire connectors, and other electronic circuitry. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units, and / or modules implemented by microprocessors or other similar hardware can be programmed and controlled using software to perform the various functions discussed herein, and optionally can be driven by firmware and / or software. Furthermore, each block, unit, and / or module may be implemented by dedicated hardware or a combination of dedicated hardware performing some functions and processors performing functions different from those of the dedicated hardware (e.g., one or more programmable microprocessors and associated circuitry). Additionally, in some embodiments, blocks, units, and / or modules may be physically separated into two or more interacting individual blocks, units, and / or modules without departing from the scope of this disclosure. Furthermore, in some embodiments, blocks, units, and / or modules may be physically combined into more complex blocks, units, and / or modules without departing from the scope of this disclosure.

[0088] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms (such as those defined in common dictionaries) shall be interpreted as having the same meaning as they have in the relevant field and / or the context of this specification, and shall not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0089] Figure 1 This is a perspective view showing a display device according to one or more embodiments.

[0090] refer to Figure 1 The display device 10 can be applied to portable electronic devices such as mobile phones, smartphones, tablet computers, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation systems, or ultra-mobile PCs (UMPCs). For example, the display device 10 can be used as a display unit in televisions, laptops, monitors, billboards, or Internet of Things (IoT) devices. As another example, the display device 10 can be applied to wearable devices such as smartwatches, smartwatch phones, glasses displays, or head-mounted displays (HMDs).

[0091] The display device 10 can have a planar shape similar to a quadrilateral. For example, the display device 10 can have a planar shape similar to a rectangle having a short side in the first direction DR1 and a long side in the second direction DR2. The corner where the short side in the first direction DR1 and the long side in the second direction DR2 intersect can be a right angle or rounded with a corresponding curvature. The planar shape of the display device 10 is not limited to a quadrilateral shape, and can be formed in a shape similar to other polygonal shapes, circular shapes, or elliptical shapes.

[0092] The display device 10 may include a display panel 100, a display driver 200, a circuit board 300, a touch driver 400, and a power supply unit 500.

[0093] Display panel 100 may include a main area MA and a sub-area SBA. The main area MA may include a display area DA containing pixels of the displayed image and a non-display area NDA surrounding the display area DA. The display area DA may emit light from multiple emission areas or multiple aperture areas. For example, display panel 100 may include pixel circuitry containing switching elements, a pixel defining film defining the emission area or aperture area, and self-emissive elements.

[0094] For example, a self-emissive element may include at least one of an organic light-emitting diode (LED) containing an organic light-emitting layer, a quantum dot LED containing a quantum dot light-emitting layer, an inorganic LED containing an inorganic semiconductor, and a micro LED, but is not limited thereto.

[0095] The non-display area NDA can be the area outside the display area DA. The non-display area NDA can be defined as the edge area of ​​the main area MA of the display panel 100. In one or more embodiments, the non-display area NDA may include a gate driver that supplies gate signals to the gate lines and a fan-out line that connects the display driver 200 to the display area DA.

[0096] The secondary SBA can extend from one side of the primary MA. The secondary SBA can include a flexible material that can be bent, folded, or rolled. For example, when the secondary SBA is bent, it can overlap the primary MA in the thickness direction (e.g., third direction DR3). The secondary SBA can include a display driver 200 and pads connected to the circuit board 300. Alternatively, the secondary SBA can be omitted, and the display driver 200 and pads can be located in the non-display area NDA.

[0097] The display driver 200 can output signals and voltages for driving the display panel 100. The display driver 200 can supply data voltage to the data line DL (see...). Figure 2The display driver 200 can supply power voltage to the power lines and can supply gate control signals to the gate driver. The display driver 200 can be formed as an integrated circuit (IC) and mounted on the display panel 100 by a chip-on-glass (COG) method, a chip-on-plastic (COP) method, or an ultrasonic bonding method. For example, the display driver 200 can be located in a sub-region SBA and can overlap with the main region MA in the thickness direction (e.g., third direction DR3) by bending the sub-region SBA. As another example, the display driver 200 can be mounted on a circuit board 300.

[0098] Circuit board 300 can be attached to pads of display panel 100 using an anisotropic conductive film (ACF). Leads of circuit board 300 can be electrically connected to pads of display panel 100. Circuit board 300 can be a flexible printed circuit board, a rigid printed circuit board, or a flexible film such as chip-on-film.

[0099] The touch driver 400 can be mounted on the circuit board 300.

[0100] Power supply unit 500 may be located on circuit board 300 to supply power voltage to display driver 200 and display panel 100 (as used herein, "located on" can mean "above" or "below"). Power supply unit 500 may generate drive voltage to supply it to drive voltage line VDL (see [link to relevant documentation]). Figure 2 It can generate a common voltage to supply to a common electrode shared by the light-emitting elements of multiple pixels. For example, the driving voltage can be a high potential voltage used to drive the light-emitting elements, and the common voltage can be a low potential voltage used to drive the light-emitting elements.

[0101] Figure 2 This is a plan view illustrating a display unit of a display device according to one or more embodiments. Figure 3 This is a block diagram illustrating a display panel and a display driver according to one or more embodiments.

[0102] refer to Figure 2 and Figure 3 The display panel 100 may include a display area DA and a non-display area NDA.

[0103] The display area DA may include multiple pixels PX and multiple signal transmission lines connected to the multiple pixels PX. Here, the multiple signal transmission lines may include multiple gate lines GL, multiple emitter lines EML, multiple data lines DL, and fan-out lines FL connected to the lines mentioned above.

[0104] Each of the multiple pixels PX can be connected to a gate line GL, a data line DL, an emitter line EML, a drive voltage line VDL, and a common voltage line. Each pixel PX may include at least one transistor, a light-emitting element, and a capacitor.

[0105] Each gate line GL can extend along a first direction DR1 and can be spaced apart from each other along a second direction DR2 that intersects the first direction DR1. The gate lines GL can be arranged along the second direction DR2. The gate lines GL can sequentially supply gate signals to multiple pixels PX.

[0106] Each of the transmit lines EML can extend along a first direction DR1 and can be spaced apart from each other along a second direction DR2. The transmit lines EML can be arranged along the second direction DR2. The transmit lines EML can sequentially supply transmit signals to multiple pixels PX.

[0107] Data lines DL can each extend along the second direction DR2 and can be spaced apart from each other along the first direction DR1. Data lines DL can be arranged along the first direction DR1. Data lines DL can supply data voltage to multiple pixels PX. The data voltage determines the brightness of each pixel PX.

[0108] The driving voltage lines VDL can each extend along the second direction DR2 and can be spaced apart from each other along the first direction DR1. The driving voltage lines VDL can be arranged along the first direction DR1. The driving voltage lines VDL can supply driving voltage to multiple pixels PX. The driving voltage can be a high potential voltage used to drive the light-emitting elements of the pixels PX.

[0109] The non-display area NDA may surround the display area DA. The non-display area NDA may include a gate driver 610, a transmit control driver 620, a fan-out line FL, a first gate control line GSL1, and a second gate control line GSL2.

[0110] The fan-out line FL can extend from the display driver 200 to the display area DA. The fan-out line FL can supply the data voltage received from the display driver 200 to multiple data lines DL.

[0111] The first gate control line GSL1 can extend from the display driver 200 to the gate driver 610. The first gate control line GSL1 can supply the gate control signal GCS received from the display driver 200 to the gate driver 610.

[0112] The second gate control line GSL2 can extend from the display driver 200 to the transmit control driver 620. The second gate control line GSL2 can supply the transmit control signal ECS received from the display driver 200 to the transmit control driver 620.

[0113] The sub-area SBA can extend from one side of the non-display area NDA. The sub-area SBA may include a display driver 200 and pads. The pads can be electrically connected to the display driver 200 and the circuit board 300 via an anisotropic conductive film (ACF).

[0114] The display driver 200 may include a timing controller 210 and a data driver 220. The timing controller 210 can receive digital video data signals DATA and timing signals from the circuit board 300. Based on the timing signals, the timing controller 210 can generate a data control signal (DCS) for controlling the operating timing of the data driver 220, a gate control signal (GCS) for controlling the operating timing of the gate driver 610, and a transmit control signal (ECS) for controlling the operating timing of the transmit control driver 620. The timing controller 210 can supply the gate control signal GCS to the gate driver 610 via a first gate control line (GSL1). The timing controller 210 can supply the transmit control signal (ECS) to the transmit control driver 620 via a second gate control line (GSL2). The timing controller 210 can also supply the digital video data signal DATA and the data control signal DCS to the data driver 220.

[0115] Data driver 220 converts digital video data signals DATA into analog data voltages, which can be supplied to data lines DL via fan-out lines FL. Gate driver 610's gate signal selects the pixel PX to which the data voltage is to be supplied, and the selected pixel PX can receive the data voltage via the data lines DL.

[0116] The power supply unit 500 may be located on the circuit board 300 to supply power voltage to the display driver 200 and the display panel 100. The power supply unit 500 may generate a driving voltage to supply to the driving voltage line VDL, and may generate a common voltage to supply to a common electrode shared by the light-emitting elements of multiple pixels PX.

[0117] The gate driver 610 may be located on one side of the display area DA or on one side of the non-display area NDA. The transmit control driver 620 may be located on the other side of the display area DA or on the other side of the non-display area NDA. However, this disclosure is not limited thereto. As another example, the gate driver 610 and the transmit control driver 620 may be located on either side of the non-display area NDA.

[0118] Gate driver 610 may include multiple transistors for generating a gate signal based on a gate control signal GCS. Emitter control driver 620 may include multiple transistors for generating an emit signal based on an emit control signal ECS. For example, the transistors of gate driver 610 and emitter control driver 620 may be formed on the same layer as the transistors of each pixel PX in pixel PX. Gate driver 610 may supply a gate signal to gate line GL, and emitter control driver 620 may supply an emit signal to emit control line EML.

[0119] Figure 4 It is shown Figure 3 A layout diagram of one or more embodiments of the display area.

[0120] refer to Figure 4 Each unit pixel may include a first emission region EA1 as the emission region of the first pixel PX1, a second emission region EA2 as the emission region of the second pixel PX2, and a third emission region EA3 as the emission region of the third pixel PX3. In other words, a unit pixel may include a unit emission region UEA, and the unit emission region UEA may include the first emission region EA1, the second emission region EA2, and the third emission region EA3 described above.

[0121] refer to Figure 4 Each of the plurality of pixels PX may include a first emission region EA1 as the emission region of the first pixel PX1, a second emission region EA2 as the emission region of the second pixel PX2, and a third emission region EA3 as the emission region of the third pixel PX3.

[0122] In the plan view, each of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may have a polygonal shape, a circular shape, an elliptical shape, or an atypical shape.

[0123] The maximum length of the third transmission region EA3 in the first direction DR1 can be less than the maximum length of the second transmission region EA2 in the first direction DR1 and the maximum length of the first transmission region EA1 in the first direction DR1. The maximum length of the second transmission region EA2 in the first direction DR1 and the maximum length of the first transmission region EA1 in the first direction DR1 can be substantially the same.

[0124] The maximum length of the third transmission region EA3 in the second direction DR2 can be greater than the maximum length of the second transmission region EA2 in the second direction DR2 and the maximum length of the first transmission region EA1 in the second direction DR2. The maximum length of the first transmission region EA1 in the second direction DR2 can be greater than the maximum length of the second transmission region EA2 in the second direction DR2.

[0125] like Figure 4 As shown, in each of the plurality of pixels PX, the third emission region EA3 and the second emission region EA2 can be adjacent to each other in the first direction DR1. Further, the first emission region EA1 and the third emission region EA3 can be adjacent to each other in the first direction DR1. Additionally, the second emission region EA2 and the first emission region EA1 can be adjacent to each other in the second direction DR2. The areas of the first emission region EA1, the second emission region EA2, and the third emission region EA3 can be different.

[0126] The first emission region EA1 can emit light of a first color, the second emission region EA2 can emit light of a second color, and the third emission region EA3 can emit light of a third color. Here, the first color light can be light in the blue band, the second color light can be light in the green band, and the third color light can be light in the red band. For example, the blue band can be a band of light whose main peak wavelength is in the range of approximately 370 nm to approximately 460 nm, the green band can be a band of light whose main peak wavelength is in the range of approximately 480 nm to approximately 560 nm, and the red band can be a band of light whose main peak wavelength is in the range of approximately 600 nm to approximately 750 nm.

[0127] Figure 5 The diagram shows along Figure 4 A cross-sectional view of an example display panel taken by line I-I'.

[0128] refer to Figure 5 The display panel 100 may include a semiconductor backplane SBP, a light-emitting element backplane EBP, a display element layer EMTL, a packaging layer TFE, an optical layer OPL, a cover layer CVL, and a polarizing plate POL.

[0129] The semiconductor backplane (SBP) may include a semiconductor substrate (SSUB) containing multiple pixel transistors (PTRs), multiple semiconductor insulating films covering the multiple pixel transistors (PTRs), and multiple contact terminals (CTEs) electrically connected to the multiple pixel transistors (PTRs).

[0130] The semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB can be a wafer or substrate doped with a first type of impurity. Multiple well regions WA can be located on the top surface of the semiconductor substrate SSUB. The multiple well regions WA can be regions doped with a second type of impurity. The second type of impurity can be different from the first type of impurity mentioned above. For example, when the first type of impurity is a p-type impurity, the second type of impurity can be an n-type impurity. Alternatively, when the first type of impurity is an n-type impurity, the second type of impurity can be a p-type impurity.

[0131] Each of the multiple well regions WA includes a source region SA corresponding to the source electrode of the pixel transistor PTR, a drain region DA corresponding to its drain electrode, and a channel region CH located between the source region SA and the drain region DA.

[0132] The lower insulating film (BINS) can be located between the gate electrode GE and the well region WA. The side insulating film (SINS) can be located on the side surface of the gate electrode GE. The side insulating film (SINS) can be located on the lower insulating film (BINS).

[0133] Each of the source region SA and the drain region DA can be a region doped with type I impurities. The gate electrode GE of the pixel transistor PTR can overlap with the well region WA on the third-direction DR3. The channel region CH can overlap with the gate electrode GE on the third-direction DR3. The source region SA can be located on one side of the gate electrode GE, and the drain region DA can be located on the other side of the gate electrode GE.

[0134] Each of the plurality of well regions WA further includes a first low-concentration impurity region LDD1 located between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 located between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 may be a region having a lower impurity concentration than the source region SA due to the lower insulating film BINS. The second low-concentration impurity region LDD2 may be a region having a lower impurity concentration than the drain region DA due to the lower insulating film BINS. The distance between the source region SA and the drain region DA may be increased due to the presence of the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2. Therefore, the length of the channel region CH in each of the pixel transistors PTRs can be increased, thereby reducing or preventing punch-through and hot carrier phenomena that may be caused by short channels.

[0135] The first semiconductor insulating film SINS1 can be located on the semiconductor substrate SSUB. The first semiconductor insulating film SINS1 can be made of silicon carbonitride (SiCN) or silicon oxide (SiO2). x It can be formed by inorganic membranes, but this disclosure is not limited thereto.

[0136] The second semiconductor insulating film SINS2 can be located on the first semiconductor insulating film SINS1. The second semiconductor insulating film SINS2 can be made of silicon oxide (SiO2). x It can be formed by inorganic membranes, but this disclosure is not limited thereto.

[0137] Multiple contact terminals (CTEs) can be located on the second semiconductor insulating film (SINS2). Each of the multiple contact terminals (CTEs) can be connected to any one of the gate electrode (GE), source region (SA), and drain region (DA) of each pixel transistor (PTR) through a hole penetrating the first semiconductor insulating film (SINS1) and the second semiconductor insulating film (SINS2). The multiple contact terminals (CTEs) can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any of them.

[0138] The third semiconductor insulating film (SINS3) can be located on the side surface of each of the plurality of contact terminals (CTEs). The top surface of each of the plurality of contact terminals (CTEs) can be exposed and not covered by the third semiconductor insulating film (SINS3). The third semiconductor insulating film (SINS3) can be made of silicon oxide (SiO2). x It can be formed by inorganic membranes, but this disclosure is not limited thereto.

[0139] The semiconductor substrate SSUB can be replaced by a glass substrate or a polymer resin (such as polyimide) substrate. In this case, the thin-film transistor can be located on the glass substrate or the polymer resin substrate. The glass substrate can be a rigid substrate that cannot be bent, and the polymer resin substrate can be a flexible substrate that can be bent or flexed.

[0140] The backplane EBP of the light-emitting element includes multiple conductive layers ML1 to ML8, multiple through holes VA1 to VA9, and multiple insulating films INS1 to INS9.

[0141] The first to eighth conductive layers ML1 to ML8 can be used to connect multiple contact terminals CTEs exposed from the semiconductor backplane SBP to realize the circuitry of a pixel (e.g., a first pixel PX1). For example, multiple pixel transistors PTRs can be formed in the semiconductor backplane SBP, and the connection between the multiple pixel transistors PTRs and the capacitor of the pixel PX can be implemented through the first to eighth conductive layers ML1 to ML8. Further, the pixel transistors PTRs can include driving transistors for driving light-emitting elements, and the connection between the drain region corresponding to the drain electrode of the driving transistor and the first electrode of the light-emitting element can also be implemented through the first to eighth conductive layers ML1 to ML8. Here, the first to eighth conductive layers ML1 to ML8 can be made of, for example, a material containing metal.

[0142] The first insulating film INS1 may be located on the semiconductor backplane SBP. Each of the first vias VA1 may penetrate the first insulating film INS1 and may be connected to a contact terminal CTE exposed from the semiconductor backplane SBP. Each of the first conductive layers ML1 may be located on the first insulating film INS1 and may be connected to the first via VA1.

[0143] The second insulating film INS2 may be located on the first insulating film INS1 and the first conductive layer ML1. Each of the second vias VA2 may penetrate the second insulating film INS2 and may be connected to the exposed first conductive layer ML1. Each of the second conductive layers ML2 may be located on the second insulating film INS2 and may be connected to the second via VA2.

[0144] The third insulating film INS3 may be located on the second insulating film INS2 and the second conductive layer ML2. Each of the third vias VA3 may penetrate the third insulating film INS3 and may be connected to the exposed second conductive layer ML2. Each of the third conductive layers ML3 may be located on the third insulating film INS3 and may be connected to the third via VA3.

[0145] The fourth insulating film INS4 may be located on the third insulating film INS3 and the third conductive layer ML3. Each of the fourth vias VA4 may penetrate the fourth insulating film INS4 and may be connected to the exposed third conductive layer ML3. Each of the fourth conductive layers ML4 may be located on the fourth insulating film INS4 and may be connected to the fourth via VA4.

[0146] The fifth insulating film INS5 may be located on the fourth insulating film INS4 and the fourth conductive layer ML4. Each of the fifth vias VA5 may penetrate the fifth insulating film INS5 and may be connected to the exposed fourth conductive layer ML4. Each of the fifth conductive layers ML5 may be located on the fifth insulating film INS5 and may be connected to the fifth via VA5.

[0147] The sixth insulating film INS6 may be located on the fifth insulating film INS5 and the fifth conductive layer ML5. Each of the sixth vias VA6 may penetrate the sixth insulating film INS6 and may be connected to the exposed fifth conductive layer ML5. Each of the sixth conductive layers ML6 may be located on the sixth insulating film INS6 and may be connected to the sixth via VA6.

[0148] The seventh insulating film INS7 may be located on the sixth insulating film INS6 and the sixth conductive layer ML6. Each of the seventh vias VA7 may penetrate the seventh insulating film INS7 and may be connected to the exposed sixth conductive layer ML6. Each of the seventh conductive layers ML7 may be located on the seventh insulating film INS7 and may be connected to the seventh via VA7.

[0149] The eighth insulating film INS8 may be located on the seventh insulating film INS7 and the seventh conductive layer ML7. Each of the eighth vias VA8 may penetrate the eighth insulating film INS8 and may be connected to the exposed seventh conductive layer ML7. Each of the eighth conductive layers ML8 may be located on the eighth insulating film INS8 and may be connected to the eighth via VA8.

[0150] The first to eighth conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8 can be formed from substantially the same material. The first to eighth conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8 can be formed from any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any of them. The first to eighth insulating films INS1 to INS8 can be made from substantially the same material. The first to eighth insulating films INS1 to INS8 can be made from silicon oxide (SiO2). x It can be formed by inorganic membranes, but this disclosure is not limited thereto.

[0151] The thicknesses of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be greater than the thicknesses of the first through-hole VA1, the second through-hole VA2, the third through-hole VA3, the fourth through-hole VA4, the fifth through-hole VA5, and the sixth through-hole VA6, respectively. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be substantially the same. For example, the thickness of the first conductive layer ML1 can be approximately... The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be approximately... The thickness of each of the following through holes can be approximated: first through hole VA1, second through hole VA2, third through hole VA3, fourth through hole VA4, fifth through hole VA5, and sixth through hole VA6.

[0152]

[0153] The thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be greater than the thickness of each of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6. The thickness of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be greater than the thickness of the seventh via VA7 and the eighth via VA8, respectively. The thickness of each of the seventh via VA7 and the eighth via VA8 can be greater than the thickness of each of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6. The thickness of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be substantially the same. For example, the thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be approximately... The thickness of each of the seventh through hole VA7 and the eighth through hole VA8 can be approximately

[0154] The ninth insulating film INS9 can be located on the eighth insulating film INS8 and the eighth conductive layer ML8. The ninth insulating film INS9 can be made of silicon oxide (SiO2). x It can be formed by inorganic membranes, but this disclosure is not limited thereto.

[0155] Each of the ninth vias VA9 can penetrate the ninth insulating film INS9 and connect to the exposed eighth conductive layer ML8. The ninth vias VA9 can be formed from any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any of them. The thickness of the ninth via VA9 can be approximately...

[0156] The display element layer EMTL can be located on the light-emitting element backplane EBP. The display element layer EMTL may include light-emitting elements, each including a first electrode AND, an emission stack ES, and a second electrode CAT, a reflective electrode layer RL, a tenth insulating film INS10 and an eleventh insulating film INS11, and a tenth via VA10. The display element layer EMTL may also include a pixel defining film PDL and multiple trenches TRC.

[0157] The reflective electrode layer RL can be located on the ninth insulating film INS9. The reflective electrode layer RL can include at least one reflective electrode RL1, RL2, RL3, and RL4. For example, the reflective electrode layer RL can include a first reflective electrode RL1, a second reflective electrode RL2, a third reflective electrode RL3, and a fourth reflective electrode RL4, such as... Figure 5 As shown in the image.

[0158] Each of the first reflective electrodes RL1 may be located on the ninth insulating film INS9 and may be connected to the ninth through-hole VA9. The first reflective electrodes RL1 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any of them. For example, the first reflective electrodes RL1 may include titanium nitride (TiN).

[0159] Each of the second reflective electrodes RL2 may be located on a corresponding first reflective electrode RL1. The second reflective electrode RL2 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of them. For example, the second reflective electrode RL2 may include aluminum (Al).

[0160] Each of the third reflective electrodes RL3 may be located on the corresponding second reflective electrode RL2. The third reflective electrode RL3 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any of them. For example, the third reflective electrode RL3 may include titanium nitride (TiN).

[0161] Each of the fourth reflective electrodes RL4 may be located on the corresponding third reflective electrode RL3. The fourth reflective electrode RL4 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any of them. For example, the fourth reflective electrode RL4 may include titanium (Ti).

[0162] Because the second reflective electrode RL2 is used to substantially reflect light from the light-emitting element, its thickness can be greater than the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4. For example, the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4 can be approximately... Furthermore, the thickness of the second reflective electrode RL2 can be approximately...

[0163] The tenth insulating film INS10 can be located on the ninth insulating film INS9. The tenth insulating film INS10 can be located between horizontally adjacent reflective electrode layers RL. The tenth insulating film INS10 can be located on the reflective electrode layer RL in the third pixel PX3. The tenth insulating film INS10 can be made of silicon oxide (SiO2). x It can be formed by inorganic membranes, but this disclosure is not limited thereto.

[0164] The eleventh insulating film INS11 can be located on the tenth insulating film INS10 and the reflective electrode layer RL. The eleventh insulating film INS11 can be made of silicon oxide (SiO2). x The tenth insulating film INS10 and the eleventh insulating film INS11 may be optical auxiliary layers through which light emitted from the light-emitting element and reflected by the reflective electrode layer RL passes.

[0165] To match the resonant distance of light emitted from the light-emitting elements of at least one of the first pixel PX1, the second pixel PX2, and the third pixel PX3, in some embodiments, the tenth insulating film INS10 and the eleventh insulating film INS11 may not be located below the first electrode AND of the first pixel PX1. The first electrode AND of the first pixel PX1 may be located directly on the reflective electrode layer RL. The eleventh insulating film INS11 may be located below the first electrode AND of the second pixel PX2. The tenth insulating film INS10 and the eleventh insulating film INS11 may be located below the first electrode AND of the third pixel PX3. Alternatively, the thickness of the eleventh insulating film INS11 in the first pixel PX1, the second pixel PX2, and the third pixel PX3 may be adjusted to adjust the resonant distance.

[0166] In summary, the distance between the first electrode AND and the reflective electrode layer RL can be different in the first pixel PX1, the second pixel PX2, and the third pixel PX3. To adjust the distance from the reflective electrode layer RL to the second electrode CAT according to the main peak wavelength of the light emitted from each of the first pixel PX1, the second pixel PX2, and the third pixel PX3, the presence or absence of the tenth insulating film INS10 and the eleventh insulating film INS11 can be set in each of the first pixel PX1, the second pixel PX2, and the third pixel PX3. For example, Figure 5The figure shows that in the third pixel PX3, the distance between the first electrode AND and the reflective electrode layer RL is greater than the distance between the first electrode AND and the reflective electrode layer RL in the second pixel PX2, and also greater than the distance between the first electrode AND and the reflective electrode layer RL in the first pixel PX1. Furthermore, the distance between the first electrode AND and the reflective electrode layer RL in the second pixel PX2 is greater than the distance between the first electrode AND and the reflective electrode layer RL in the first pixel PX1, but this disclosure is not limited thereto.

[0167] Furthermore, although the tenth insulating film INS10 and the eleventh insulating film INS11 are illustrated in one or more embodiments, a twelfth insulating film may be added below the first electrode AND of the first pixel PX1 in one or more embodiments. In this case, the eleventh insulating film INS11 and the twelfth insulating film may be located below the first electrode AND of the second pixel PX2, and the tenth insulating film INS10, the eleventh insulating film INS11, and the twelfth insulating film may be located below the first electrode AND of the third pixel PX3.

[0168] Each of the tenth vias VA10 can penetrate the tenth insulating film INS10 and / or the eleventh insulating film INS11 in the second pixel PX2 and the third pixel PX3, and can be connected to the exposed reflective electrode layer RL. The tenth via VA10 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any of them. The thickness of the tenth via VA10 in the second pixel PX2 can be less than the thickness of the tenth via VA10 in the third pixel PX3.

[0169] The first electrode AND of each of the light-emitting elements may be located on the tenth insulating film INS10 and connected to the tenth via VA10. The first electrode AND of each of the light-emitting elements may be connected to the drain region DA or source region SA of the pixel transistor PTR via the tenth via VA10, the first to fourth reflective electrodes RL1 to RL4, the first to ninth vias VA1 to VA9, the first to eighth conductive layers ML1 to ML8, and the contact terminal CTE. The first electrode AND of each of the light-emitting elements may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any of them. For example, the first electrode AND of each of the light-emitting elements may be titanium nitride (TiN).

[0170] The pixel-defining film (PDL) can be located on a portion of the first electrode AND of each of the light-emitting elements. The PDL can cover the edge of the first electrode AND of each of the light-emitting elements. The PDL can be used to separate the first emission region EA1, the second emission region EA2, and the third emission region EA3.

[0171] The first emitting region EA1 can be defined as the region in which a first electrode AND, an emitting stack ES, and a second electrode CAT are sequentially stacked in a first pixel PX1 to emit light. The second emitting region EA2 can be defined as the region in which a first electrode AND, an emitting stack ES, and a second electrode CAT are sequentially stacked in a second pixel PX2 to emit light. The third emitting region EA3 can be defined as the region in which a first electrode AND, an emitting stack ES, and a second electrode CAT are sequentially stacked in a third pixel PX3 to emit light.

[0172] The pixel-defining film (PDL) may include a first pixel-defining film (PDL1), a second pixel-defining film (PDL2), and a third pixel-defining film (PDL3). The first pixel-defining film (PDL1) may be located on the edge of the first electrode AND of each of the light-emitting elements, the second pixel-defining film (PDL2) may be located on the first pixel-defining film (PDL1), and the third pixel-defining film (PDL3) may be located on the second pixel-defining film (PDL2). The first pixel-defining film (PDL1), the second pixel-defining film (PDL2), and the third pixel-defining film (PDL3) may be made of silicon oxide (SiO2). x The first pixel-defining film PDL1, the second pixel-defining film PDL2, and the third pixel-defining film PDL3 may each have approximately [amount missing]. The thickness.

[0173] When the first pixel-defining film PDL1, the second pixel-defining film PDL2, and the third pixel-defining film PDL3 are formed into a single pixel-defining film, the height of this single pixel-defining film increases, making the first encapsulating inorganic film TFE1 potentially cut due to step coverage. Step coverage refers to the ratio of the degree of coating on the inclined portion of the film to the degree of coating on the flat portion. The lower the step coverage, the greater the likelihood that the film will be cut at the inclined portion.

[0174] Therefore, to reduce or prevent the possibility of the first encapsulated inorganic film TFE1 being cut due to step coverage, the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 can have a cross-sectional structure with stepped portions. For example, the width of the first pixel defining film PDL1 can be greater than the width of the second pixel defining film PDL2 and the width of the third pixel defining film PDL3, and the width of the second pixel defining film PDL2 can be greater than the width of the third pixel defining film PDL3. The width of the first pixel defining film PDL1 refers to the horizontal length of the first pixel defining film PDL1 defined in the first direction DR1 and / or the second direction DR2.

[0175] Each of the multiple trench TRCs can penetrate the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3. Furthermore, each of the multiple trench TRCs can penetrate the eleventh insulating film INS11. The tenth insulating film INS10 can be partially recessed at each of the multiple trench TRCs.

[0176] At least one trench TRC can be located between adjacent pixels PX1, PX2, and PX3. Although Figure 5 The figure shows two trench TRCs located between adjacent pixels PX1, PX2 and PX3, but this disclosure is not limited thereto.

[0177] An ES (Emitting Stack) can include multiple stacking layers. Figure 5 The figure illustrates a transmitter stack ES with a three-layer cascaded structure including a first stacking layer IL1, a second stacking layer IL2, and a third stacking layer IL3, but this disclosure is not limited thereto. For example, the transmitter stack ES may have a two-layer cascaded structure including two intermediate layers.

[0178] In a three-layer cascaded structure, the emission stack ES can have a cascaded structure comprising multiple stacked layers IL1, IL2, and IL3 that emit different colors of light. For example, the emission stack ES may include a first stacked layer IL1 that emits light of a first color, a second stacked layer IL2 that emits light of a third color, and a third stacked layer IL3 that emits light of a second color. The first stacked layer IL1, the second stacked layer IL2, and the third stacked layer IL3 can be stacked sequentially.

[0179] The first stacked layer IL1 may have a structure in which a first hole transport layer, a first organic light-emitting layer emitting light of a first color, and a first electron transport layer are sequentially stacked. The second stacked layer IL2 may have a structure in which a second hole transport layer, a second organic light-emitting layer emitting light of a third color, and a second electron transport layer are sequentially stacked. The third stacked layer IL3 may have a structure in which a third hole transport layer, a third organic light-emitting layer emitting light of a second color, and a third electron transport layer are sequentially stacked.

[0180] A first charge-generating layer for supplying charge to the second stacked layer IL2 and electrons to the first stacked layer IL1 may be located between the first stacked layer IL1 and the second stacked layer IL2. The first charge-generating layer may include an N-type charge-generating layer for supplying electrons to the first stacked layer IL1 and a P-type charge-generating layer for supplying holes to the second stacked layer IL2. The N-type charge-generating layer may contain a dopant of metallic material.

[0181] A second charge generation layer for supplying charge to the third stacked layer IL3 and electrons to the second stacked layer IL2 may be located between the second stacked layer IL2 and the third stacked layer IL3. The second charge generation layer may include an N-type charge generation layer for supplying electrons to the second stacked layer IL2 and a P-type charge generation layer for supplying holes to the third stacked layer IL3.

[0182] The first stacked layer IL1 can be located on the first electrode AND and the pixel defining film PDL, and can be located on the bottom surface of each trench TRC. Due to the trench TRC, the first stacked layer IL1 may be cut between adjacent pixels PX1, PX2, and PX3. The second stacked layer IL2 can be located on the first stacked layer IL1. Due to the trench TRC, the second stacked layer IL2 may be cut between adjacent pixels PX1, PX2, and PX3. An empty cavity ESS or empty space can be located between the first stacked layer IL1 and the second stacked layer IL2. The third stacked layer IL3 can be located on the second stacked layer IL2. The third stacked layer IL3 is not cut by the trench TRC and can cover the second stacked layer IL2 in each of the trench TRCs. That is, in the three-layer cascaded structure, each of the plurality of trench TRCs can be a structure for cutting the first stacked layer IL1 and the second stacked layer IL2, the first charge generation layer, and the second charge generation layer of the display element layer EMTL between adjacent pixels PX1, PX2, and PX3. Furthermore, in the double-layer series structure, each of the trench TRCs can be a structure used to cut off the charge generation layer located between the lower intermediate layer and the upper intermediate layer, as well as the lower intermediate layer.

[0183] To stably cut the first stacked layer IL1 and the second stacked layer IL2 of the display element layer EMTL between adjacent pixels PX1, PX2, and PX3, the height of each of the plurality of trench TRCs can be greater than the height of the pixel defining film PDL. The height of each of the plurality of trench TRCs refers to the length of each of the plurality of trench TRCs on the third-direction DR3. The height of the pixel defining film PDL refers to the length of the pixel defining film PDL on the third-direction DR3. To cut the first stacked layer IL1 and the second stacked layer IL2 of the display element layer EMTL between adjacent pixels PX1, PX2, and PX3, an alternative structure can exist to replace the trench TRCs. For example, instead of trench TRCs, an inverted conical partition wall can be located on the pixel defining film PDL.

[0184] The number of stacked layers IL1, IL2, and IL3 that emit different light is not limited to Figure 5 The quantities shown are as described. For example, the emitter stack ES may include two intermediate layers. In this case, one of the two intermediate layers may be substantially identical to the first stack layer IL1, and the other intermediate layer may include a second hole transport layer, a second organic light-emitting layer, a third organic light-emitting layer, and a second electron transport layer. In this case, a charge-generating layer for supplying electrons to one intermediate layer and charge to the other intermediate layer may be located between the two intermediate layers.

[0185] also, Figure 5 The diagram shows that the first stacked layer IL1, the second stacked layer IL2, and the third stacked layer IL3 are all located within the first emission region EA1, the second emission region EA2, and the third emission region EA3, but this disclosure is not limited thereto. For example, the first stacked layer IL1 may be located within the first emission region EA1 and may be omitted from the second emission region EA2 and the third emission region EA3. Furthermore, the second stacked layer IL2 may be located within the second emission region EA2 and may be omitted from the first emission region EA1 and the third emission region EA3. Further, the third stacked layer IL3 may be located within the third emission region EA3 and may be omitted from the first emission region EA1 and the second emission region EA2. In this case, the first color filter CF1, the second color filter CF2, and the third color filter CF3 of the optical layer OPL may be omitted.

[0186] The second electrode CAT can be located on the third stacked layer IL3. The second electrode CAT can be located on the third stacked layer IL3 in each of the multiple trench TRCs. The second electrode CAT can be formed of a transparent conductive material (TCO) (such as light-transmitting ITO or IZO) or a semi-transmitting conductive material (such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag). When the second electrode CAT is formed of a semi-transmitting conductive material, the luminous efficiency can be improved in each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 due to the microcavity effect.

[0187] The encapsulation layer TFE can be located on the display element layer EMTL. The encapsulation layer TFE may include at least one inorganic film TFE1 and TFE2 to reduce or prevent oxygen or moisture from penetrating into the display element layer EMTL. For example, the encapsulation layer TFE may include a first encapsulation inorganic film TFE1 and a second encapsulation inorganic film TFE2.

[0188] The first encapsulating inorganic film TFE1 can be located on the second electrode CAT. The first encapsulating inorganic film TFE1 can be formed in which silicon nitride (SiN) is alternately stacked. x ), silicon oxynitride (SiO) x N y ) and silicon dioxide (SiO) x The first encapsulated inorganic film, TFE1, is formed using a chemical vapor deposition (CVD) process.

[0189] The second encapsulating inorganic film TFE2 can be located on top of the first encapsulating inorganic film TFE1. The second encapsulating inorganic film TFE2 can be made of titanium oxide (TiO2). x ) or aluminum oxide (AlO x The second encapsulation inorganic film TFE2 can be formed by atomic layer deposition (ALD). The thickness of the second encapsulation inorganic film TFE2 can be less than the thickness of the first encapsulation inorganic film TFE1.

[0190] According to one or more embodiments, the packaging substrate ENC (see...) Figure 37 and Figure 38 This can be further located on the TFE encapsulation layer. For example, the ENC encapsulation substrate can be located between the TFE encapsulation layer and the APL organic film. The ENC encapsulation substrate can include glass.

[0191] Organic film APL can be a layer used to increase the interfacial adhesion between the encapsulation layer TFE and the optical layer OPL. Organic film APL can be an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin.

[0192] The optical layer OPL includes multiple color filters CF1, CF2, and CF3, multiple lenses LNS, and a filler layer FIL. The multiple color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be located on the organic film APL.

[0193] The first color filter CF1 may overlap with the first emission region EA1 of the first pixel PX1. The first color filter CF1 may transmit light of a first color (e.g., light in the blue band). The blue band may be from about 370 nm to about 460 nm. Therefore, the first color filter CF1 may transmit light of the first color emitted from the first emission region EA1.

[0194] The second color filter CF2 can overlap with the second emission region EA2 of the second pixel PX2. The second color filter CF2 can transmit light of a second color (e.g., light in the green band). The green band can be from about 480 nm to about 560 nm. Therefore, the second color filter CF2 can transmit light of the second color emitted from the second emission region EA2.

[0195] The third color filter CF3 can overlap with the third emission region EA3 of the third pixel PX3. The third color filter CF3 can transmit light of a third color (e.g., light in the red band). The red band can be from about 600 nm to about 750 nm. Therefore, the third color filter CF3 can transmit light of the third color emitted from the third emission region EA3.

[0196] Multiple lenses LNS can be located on the first color filter CF1, the second color filter CF2, and the third color filter CF3, respectively. Each of the multiple lenses LNS can be a structure for increasing the ratio of light guided to the front of the display device 10. Each of the multiple lenses LNS can have a cross-sectional shape that convexes in the upward direction.

[0197] The filler layer (FIL) can be located on multiple lens lenses (LNS). The filler layer (FIL) can have a refractive index (e.g., a predetermined refractive index) such that light travels in a third direction (DR3) at the interface between the filler layer (FIL) and the multiple lens lenses (LNS). Further, the filler layer (FIL) can be a planarization layer. The filler layer (FIL) can be an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0198] The cover layer CVL can be located on the filler layer FIL. The cover layer CVL can be a glass substrate or a polymer resin. When the cover layer CVL is a glass substrate, it can be attached to the filler layer FIL. In this case, the filler layer FIL can be used to bond the cover layer CVL. When the cover layer CVL is a glass substrate, it can be used as an encapsulation substrate. When the cover layer CVL is a polymer resin, it can be directly coated onto the filler layer FIL.

[0199] The polarizer POL can be located on one surface of the CVL cover layer. The polarizer POL can be a structure used to reduce or prevent visibility degradation caused by reflection of external light. The polarizer POL can include a linear polarizer and a phase retardation film. For example, the phase retardation film can be a λ / 4 plate (quarter-wave plate), but this disclosure is not limited thereto. However, the polarizer POL can be omitted when the visibility degradation caused by reflection of external light is sufficiently overcome by the first color filter CF1, the second color filter CF2, and the third color filter CF3.

[0200] Figure 6 yes Figure 2 A magnified view of area A1.

[0201] like Figure 6 As shown, a first alignment mark AM1 may be located at the display panel 100, and a second alignment mark AM2 may be located at the display driver 200. For example, two first alignment marks AM1 may be located at corresponding edges of the display panel 100, and two second alignment marks AM2 may be located at corresponding edges of the display driver 200. The first alignment marks AM1 may be located at the display panel 100 facing each other in the first direction DR1, and the second alignment marks AM2 may be located at the display driver 200 facing each other in the first direction DR1.

[0202] Alignment between the display panel 100 and the display driver 200 can be performed using a first alignment mark AM1 and a second alignment mark AM2. In this case, the display panel 100 and the display driver 200 can be determined to be aligned when the distance between the first alignment mark AM1 and the second alignment mark AM2 meets the tolerance. For example, the display panel 100 and the display driver 200 can be determined to be aligned when the center portions of the first alignment mark AM1 and the second alignment mark AM2 overlap each other.

[0203] Figure 7 yes Figure 6 A magnified view of region A2. Figure 8 It is only selectively shown Figure 7 A view of the display panel 100, the first alignment mark AM1, and the pad PD. Figure 9 It is selectively displayed. Figure 7 The view of the display driver 200, the second alignment mark AM2, and the terminal TM, and Figure 10 It is along Figure 7 The cross-sectional view taken from line II-II'.

[0204] like Figure 7 and Figure 8 As shown, the display panel 100 (or the semiconductor substrate SSUB of the display panel 100) may include a first circuit region CA1 (or a first patterned region) in which the first circuit patterns described above (such as pixel transistors PTR, conductive layers ML1 to ML8, vias VA1 to VA10, reflective electrode layers RL, first electrodes AND, emitter stacks ES, and second electrodes CAT) are positioned, and may also include a first non-circuit region NCA1 (or a first non-patterned region) in which the first circuit patterns described above are not positioned. In other words, at least one of the first circuit patterns described above and an insulating film (e.g., first to eleventh insulating films INS1 to INS11) may be located in the first circuit region CA1 of the display panel 100, and the insulating film may be located in the first non-circuit region NCA1 of the display panel 100. According to one or more embodiments, in Figure 8 In the plan view shown, the first non-circuit region NCA1 of the display panel 100 may have a quadrilateral shape. However, the shape of the first non-circuit region NCA1 of the display panel 100 is not limited to this, and it may have various shapes.

[0205] like Figure 7 and Figure 8 As shown, the first alignment mark AM1 may be located in the sub-area SBA (or pad area) mentioned on the front of the display panel 100 (see, for example, see...). Figure 1 or Figure 6 In, for example, the first alignment mark AM1 may be located in the first non-circuit region NCA1 of the display panel 100 in the sub-region SBA. According to one or more embodiments, in Figure 8 In the plan view shown, the first alignment mark AM1 may be located at the edge of the first non-circuit region NCA1. In the plan view, the first alignment mark AM1 (e.g., the inner surface of the first alignment mark AM1) may have a closed curve shape within the first non-circuit region NCA1, enclosing a portion of the first non-circuit region NCA1. According to one or more embodiments, the outer surface of the first alignment mark AM1 may substantially enclose the first non-circuit region NCA1. In other words, the outer surface of the first alignment mark AM1 may define the first non-circuit region NCA1. The first alignment mark AM1 may have a quadrilateral annular shape, as shown in... Figure 7 and Figure 8The example shown is an example of this. However, the shape of the first alignment mark AM1 is not limited to this, and it can have various shapes. For example, the insulating film can be located in the area surrounded by the first alignment mark AM1. For example, in the plan view, the ninth insulating film INS9 can be partially located in the area surrounded by the first alignment mark AM1.

[0206] The first alignment mark AM1 can be made of a material containing metal. For example, the first alignment mark AM1 can be made of the same material as any of the first to eighth conductive layers ML1 to ML8 described above. According to one or more embodiments, the first alignment mark AM1 can be located on the eighth insulating film INS8, such as... Figure 10 As shown in the diagram. For example, the first alignment mark AM1 can be made of the same material as the eighth conductive layer ML8.

[0207] The pads PD of the display panel 100 may be located in the first circuit region CA1 of the display panel 100. For example, the pads PD may be located in the first circuit region CA1 of the sub-region SBA (or pad region) of the display panel 100. In this case, multiple pads PD may be arranged close to the first alignment mark AM1. According to one or more embodiments, the encapsulation layer TFE is not located in the sub-region SBA (or pad region) where the pads PD of the display panel 100 are located. The pads PD may be exposed to the outside through through-holes in the insulating film (e.g., the ninth insulating film INS9).

[0208] like Figure 7 and Figure 9 As shown, the display driver 200 (or the substrate SUB of the display driver 200) may include a second circuit region CA2 (or second patterned region) in which a second circuit pattern (such as a transistor, conductive layer, and via) is positioned, and a second non-circuit region NCA2 (or second non-patterned region) in which the second circuit pattern described above is not positioned. In other words, at least one of the second circuit patterns described above, and insulating films ISL1, ISL2, and ISL3 (see...) Figure 10 The insulating films ISL1, ISL2, and ISL3 may be located in the second circuit region CA2 of the display driver 200, and may be located in the second non-circuit region NCA2 of the display driver 200. According to one or more embodiments, in Figure 9 In the plan view shown, the second non-circuit region NCA2 of the display driver 200 can have a quadrilateral shape. However, the second non-circuit region NCA2 of the display driver 200 is not limited to this and can have various shapes.

[0209] like Figure 7 and Figure 9As shown, the display driver 200 may include a second alignment mark AM2. For example, the second alignment mark AM2 may be located in a second non-circuit region NCA2 of the display driver 200. According to one or more embodiments, in Figure 9 In the plan view shown, the second alignment mark AM2 may be located at the center of the second non-circuit region NCA2. For example, in the plan view, the second alignment mark AM2 may occupy at least a portion of the center of the second non-circuit region NCA2. The second alignment mark AM2 may have a cross-shaped shape, as shown in... Figure 7 and Figure 9 The example shown. However, the shape of the second alignment mark AM2 is not limited to this, and it can have various shapes.

[0210] exist Figure 9 In the plan view shown, the second alignment mark AM2 can be surrounded by the insulating film of the display driver 200. For example, in the plan view, the second alignment mark AM2 can be surrounded by the third insulating film ISL3 of the display driver 200.

[0211] The second alignment mark AM2 can be made of a metallic material. For example, the second alignment mark AM2 can be made of the same material as any of the conductive layers of the display driver 200. According to one or more embodiments, the second alignment mark AM2 can be located on the second insulating film ISL2, such as... Figure 10 As shown in the diagram. For example, the second alignment mark AM2 can be made of the same material as the conductive layer of the display driver 200 located on the second insulating film ISL2 in the second circuit region CA2.

[0212] According to one or more embodiments, the auxiliary alignment mark AXM may be further located at the display driver 200. For example, as Figure 7 and Figure 9 As shown, the auxiliary alignment mark AXM can be located in the second non-circuit region NCA2, adjacent to the first alignment mark AM1. The auxiliary alignment mark AXM can have a quadrilateral shape, as shown in... Figure 7 and Figure 9 The example shown is an example of this. However, the shape of the auxiliary alignment mark AXM is not limited to this, and it can have various shapes in other embodiments. Figure 7 and Figure 9As shown, when the first alignment mark AM1 has a symmetrical shape in both the vertical and horizontal directions, the auxiliary alignment mark AXM can be positioned close to any part of the first alignment mark AM1, thereby eliminating the symmetry of the first alignment mark AM1. Accordingly, the orientation of the first alignment mark AM1 can be easily detected, and therefore, the orientation of the display driver 200 can be easily detected. The auxiliary alignment mark AXM can be omitted.

[0213] The terminals TM (e.g., bumps) of the display driver 200 may be located in the second circuit region CA2 of the display driver 200. In this case, multiple terminals TM may be arranged close to the second alignment mark AM2. Figure 10 As shown, the terminals TM of the display driver 200 can protrude to the outside through through-holes in the insulating film (e.g., the third insulating film ISL3). The terminals TM of the display driver 200 can overlap with the pads PD of the display panel 100, respectively. The terminals TM of the display driver 200 can be connected to the pads PD of the display panel 100, respectively. For example, the terminals TM of the display driver 200 and the pads PD of the display panel 100 can be electrically connected to each other through an anisotropic conductive film located between them.

[0214] According to one or more embodiments, in Figure 7 In the plan view shown, the area surrounded and defined by the first alignment mark AM1 (hereinafter referred to as the inner area of ​​the first alignment mark AM1) can have a larger area than the area of ​​the second alignment mark AM2. For example, the area of ​​the inner area of ​​the first alignment mark AM1 can be larger than the area of ​​the second alignment mark AM2. According to one or more embodiments, when the auxiliary alignment mark AXM described above is further located at the display driver 200, in Figure 7 In the plan view shown, the inner region of the first alignment mark AM1 can have a larger area than the areas of the second alignment mark AM2 and the auxiliary alignment mark AXM. For example, the area of ​​the inner region of the first alignment mark AM1 can be greater than the sum of the areas of the second alignment mark AM2 and the auxiliary alignment mark AXM.

[0215] According to one or more embodiments, in Figure 7In the plan view shown, the first alignment mark AM1 may surround the second alignment mark AM2. For example, in the plan view, the second alignment mark AM2 may be located within the inner area of ​​the first alignment mark AM1. According to one or more embodiments, when the auxiliary alignment mark AXM described above is further located at the display driver 200, in the plan view, the first alignment mark AM1 may surround the second alignment mark AM2 and the auxiliary alignment mark AXM. For example, in the plan view, the second alignment mark AM2 and the auxiliary alignment mark AXM may be located within the inner area of ​​the first alignment mark AM1.

[0216] According to one or more embodiments, in Figure 7 In the plan view shown, the second non-circuitous region NCA2 of the display driver 200 may have an area larger than the area of ​​the first non-circuitous region NCA1 of the display panel 100. In other words, the area of ​​the second non-circuitous region NCA2 may be larger than the area of ​​the first non-circuitous region NCA1. In the plan view, the edge of the second non-circuitous region NCA2 may surround the first non-circuitous region NCA1. For example, the entire first non-circuitous region NCA1 may overlap with the second non-circuitous region NCA2. For example, the inner area defined by the first alignment mark AM1 may have an area smaller than the area of ​​the second non-circuitous region NCA2.

[0217] Figure 11 This is a plan view of the display panel 100 according to one or more embodiments. Figure 12 This is a plan view of a display driver 200 according to one or more embodiments, and Figure 13 When Figure 11 Display panel 100 and Figure 12 When the display drivers 200 are connected to each other, along Figure 11 and Figure 12 The cross-sectional view taken from line III-III'.

[0218] Figures 11 to 13 The display device and the one described above Figure 8 and Figure 9 The difference of the display device is that it further includes a first dummy pattern DM1 and a second dummy pattern DM2, and this difference will be mainly described below.

[0219] like Figure 11 and Figure 13 As shown, the first dummy pattern DM1 may be located in the first non-circuit region NCA1 of the display panel 100. Figure 11 In the plan view shown, the first dummy pattern DM1 can be surrounded by the first alignment mark AM1. For example, the first dummy pattern DM1 can be located within the inner area of ​​the first alignment mark AM1.

[0220] The first dummy pattern DM1 can be arranged in a matrix along the first direction DR1 and the second direction DR2. The gaps between adjacent first dummy patterns DM1 can be the same.

[0221] The first dummy pattern DM1 can have the same shape. For example, in a plan view, each of the first dummy patterns DM1 can have a quadrilateral shape. However, the shape of the first dummy pattern DM1 is not limited to this, and it can have various shapes.

[0222] The first dummy pattern DM1 can be made of a material containing metal. For example, the first dummy pattern DM1 can be made of the same material as any of the first to eighth conductive layers ML1 to ML8 described above. According to one or more embodiments, the first dummy pattern DM1 can be located on the first insulating film INS1, such as... Figure 13 As shown in the diagram. For example, the first dummy pattern DM1 can be made of the same material as the first conductive layer ML1.

[0223] According to one or more embodiments, the first dummy pattern DM1 and the first alignment mark AM1 may be located on different layers. For example, the first dummy pattern DM1 may be positioned closer to the substrate (e.g., semiconductor substrate SSUB) than the first alignment mark AM1. As an example, the distance between the first dummy pattern DM1 and the semiconductor backplane SBP (e.g., semiconductor substrate SSUB) may be smaller than the distance between the first alignment mark AM1 and the semiconductor backplane SBP (e.g., semiconductor substrate SSUB).

[0224] The first dummy pattern DM1 can reduce or minimize the step portion between the insulating film of the first circuit region CA1 (e.g., the second to ninth insulating films INS2 to INS9) and the insulating film of the first non-circuit region NCA1 (e.g., the second to ninth insulating films INS2 to INS9). For example, since the first non-circuit region NCA1 does not include the first circuit pattern of the first circuit region CA1, the insulating film of the first non-circuit region NCA1 can have a lower height than the insulating film of the first circuit region CA1, and the first dummy pattern DM1 described above can be located in the first non-circuit region NCA1 to reduce or minimize the step portion between the insulating film of the first circuit region CA1 and the insulating film of the first non-circuit region NCA1. Accordingly, the step portion between the first alignment mark AM1 located above the first dummy pattern DM1 and the adjacent conductive layer (e.g., the eighth conductive layer ML8) of the first alignment mark AM1 can be reduced or minimized.

[0225] Simultaneously, the first dummy pattern DM1 can overlap with the first alignment mark AM1. For example, in Figure 13In this process, the first dummy pattern DM1 can be further positioned between the first alignment mark AM1 and the first insulating film INS1, such that the first dummy pattern DM1 and the first alignment mark AM1 overlap each other.

[0226] like Figure 12 and Figure 13 As shown, the second dummy pattern DM2 can be located in the second non-circuit region NCA2 of the display driver 200. Figure 12 In the plan view shown, the second dummy pattern DM2 can be surrounded by the second non-circuit region NCA2.

[0227] The second dummy pattern DM2 can be arranged in a matrix along the first direction DR1 and the second direction DR2. The gaps between adjacent second dummy patterns DM2 can be the same.

[0228] The second dummy pattern DM2 can have the same shape. For example, in a plan view, each of the second dummy patterns DM2 can be a quadrilateral. However, the shape of the second dummy pattern DM2 is not limited to this, and it can have various shapes.

[0229] The second dummy pattern DM2 can be made of a material containing metal. For example, the second dummy pattern DM2 can be made of the same material as any of the conductive layers of the display driver 200. According to one or more embodiments, the second dummy pattern DM2 can be located on the first insulating film ISL1, such as... Figure 13 As shown in the figure. For example, the second dummy pattern DM2 can be made of the same material as the conductive layer on the first insulating film ISL1 of the display driver 200.

[0230] According to one or more embodiments, the second dummy pattern DM2 and the second alignment mark AM2 may be located on different layers. For example, the second dummy pattern DM2 may be positioned closer to the substrate SUB of the display driver 200 than the second alignment mark AM2. As an example, the distance between the second dummy pattern DM2 and the substrate SUB may be smaller than the distance between the second alignment mark AM2 and the substrate SUB.

[0231] The second dummy pattern DM2 can reduce or minimize the step portion between the insulating film of the second circuit region CA2 (e.g., the second insulating film ISL2 and the third insulating film ISL3) and the insulating film of the second non-circuit region NCA2 (e.g., the second insulating film ISL2 and the third insulating film ISL3). For example, since the second non-circuit region NCA2 does not include the second circuit pattern of the second circuit region CA2, the insulating film of the second non-circuit region NCA2 can have a lower height than the insulating film of the second circuit region CA2, and the second dummy pattern DM2 described above can be located in the second non-circuit region NCA2 to reduce or minimize the step portion between the insulating film of the second circuit region CA2 and the insulating film of the second non-circuit region NCA2. Accordingly, the step portion between the second alignment mark AM2 located above the second dummy pattern DM2 and the adjacent conductive layer of the second alignment mark AM2 (e.g., the conductive layer on the first insulating film ISL1) can be reduced or minimized.

[0232] Simultaneously, the second dummy pattern DM2 can overlap with the second alignment mark AM2. For example, in Figure 13 In this process, the second dummy pattern DM2 can be further located between the second alignment mark AM2 and the first insulating film ISL1, such that the second dummy pattern DM2 and the second alignment mark AM2 overlap each other.

[0233] Figure 14 This is a plan view of a display panel 100 according to one or more embodiments, and Figure 15 When Figure 14 Display panel 100 and Figure 9 When the display drivers 200 are connected to each other, along Figure 14 The cross-sectional view taken from line IV-IV'.

[0234] Figure 14 and Figure 15 The display device and the one described above Figure 8 and Figure 10 The difference in the display device lies in the shape of the first alignment mark AM1, and this difference will be mainly described below.

[0235] like Figure 14 and Figure 15 As shown, the first alignment mark AM1 of the display panel 100 may include an outer pattern Ma and a raised pattern Mb.

[0236] Because the outer pattern Ma is the same as the first alignment mark AM1 described above, the description of the outer pattern Ma will refer to the description above. Figure 8 The description of the first alignment mark AM1.

[0237] The protruding pattern Mb can protrude from the inner surface of the outer pattern Ma. For example, protruding patterns Mb protruding from two surfaces of the outer pattern Ma that face each other in the first direction DR1 can protrude towards each other from the center portion of the respective surfaces so that they face each other in the first direction DR1. Furthermore, protruding patterns Mb protruding from two surfaces of the outer pattern Ma that face each other in the second direction DR2 can protrude towards each other from the center portion of the respective surfaces so that they face each other in the second direction DR2.

[0238] In the plan view, the protruding pattern Mb may not overlap with the second alignment mark AM2 and the auxiliary alignment mark AXM.

[0239] The outer pattern Ma and the protruding pattern Mb can be formed integrally with each other.

[0240] The outer pattern Ma and the raised pattern Mb can be made of the same material. The outer pattern Ma and the raised pattern Mb can be made of the same material as the eighth conductive layer ML8, as in... Figure 15 The example shown.

[0241] When the outer pattern Ma and the protruding pattern Mb are made of different materials, the outer pattern Ma and the protruding pattern Mb can be located in different layers. For example, the outer pattern Ma can be made of the same material as the eighth conductive layer ML8, and the protruding pattern Mb can be made of the same material as the seventh conductive layer ML7.

[0242] Figure 16 This is a plan view of a display panel 100 according to one or more embodiments.

[0243] Figure 16 The display panel 100 is the same as described above. Figure 14 and Figure 15 The difference of the display panel 100 is that it further includes a first dummy pattern DM1, and this difference will be mainly described below.

[0244] like Figure 16 As shown, the display panel 100 according to one or more embodiments may include a first alignment mark AM1 and a first dummy pattern DM1. Here, the first alignment mark AM1 may include the outer pattern Ma and the protruding pattern Mb described above.

[0245] because Figure 16 The first dummy pattern DM1 is the same as described above. Figure 11 and Figure 13 The first dummy pattern DM1 is the same, so for Figure 16 The description of the first dummy pattern DM1 will refer to the description of the first dummy pattern DM1. Figure 11 and Figure 13 Description of the first dummy pattern DM1.

[0246] Figure 17 This is a plan view of a display panel 100 according to one or more embodiments.

[0247] Figure 17 The display panel 100 is positioned in the same location as described above for the first dummy pattern DM1. Figure 11 The display panel 100 is different, and this difference will be mainly described below.

[0248] exist Figure 17 In the plan view shown, the first dummy pattern DM1 can be positioned near each corner of the first alignment mark AM1 within the inner area of ​​the first alignment mark AM1. For example, the first dummy pattern DM1 may not be located in the center portion of the inner area of ​​the first alignment mark AM1.

[0249] Figure 18 This is a plan view of a display panel 100 according to one or more embodiments.

[0250] Figure 18 The display panel 100 is positioned in the same location as described above for the first dummy pattern DM1. Figure 11 The display panel 100 is different, and this difference will be mainly described below.

[0251] exist Figure 18 In the plan view shown, the first dummy pattern DM1 may be located in the area inside the first alignment mark AM1, except for each corner of the first alignment mark AM1.

[0252] Figure 19 This is a plan view of a display panel 100 according to one or more embodiments.

[0253] Figure 19 The display panel 100 is positioned in the same location as described above for the first dummy pattern DM1. Figure 16 The display panel 100 is different, and this difference will be mainly described below.

[0254] exist Figure 19 In the plan view shown, the first dummy pattern DM1 can be positioned near each corner of the first alignment mark AM1 within the inner area of ​​the first alignment mark AM1. For example, the first dummy pattern DM1 may not be located in the center portion of the inner area of ​​the first alignment mark AM1.

[0255] Figure 20 This is a plan view of a display panel 100 according to one or more embodiments.

[0256] Figure 20The display panel 100 is positioned in the same location as described above for the first dummy pattern DM1. Figure 16 The display panel 100 is different, and this difference will be mainly described below.

[0257] exist Figure 20 In the plan view shown, the first dummy pattern DM1 may be located in the area inside the first alignment mark AM1, except for each corner of the first alignment mark AM1.

[0258] Figure 21 This is a plan view of a display panel 100 according to one or more embodiments.

[0259] Figure 21 The display panel 100 is in the shape of the first alignment mark AM1 as described above. Figure 8 The display panel 100 is different, and this difference will be mainly described below.

[0260] exist Figure 21 In the plan view shown, the first alignment mark AM1 may have a triangular shape. For example, in the plan view, the first alignment mark AM1 may have a closed curve shape that surrounds a portion of the first non-circuit region NCA1, and this closed curve may form a triangular shape.

[0261] Furthermore, in Figure 21 In the plan view shown, the first non-circuit region NCA1 can have a triangular shape.

[0262] Figure 22 This is a plan view of a display panel 100 according to one or more embodiments.

[0263] Figure 22 The display panel 100 is in the shape of the first alignment mark AM1 as described above. Figure 8 The display panel 100 is different, and this difference will be mainly described below.

[0264] exist Figure 22 In the plan view shown, the first alignment mark AM1 may have a trapezoidal (or inverted trapezoidal) shape. For example, in the plan view, the first alignment mark AM1 may have a closed curve shape that surrounds a portion of the first non-circuit region NCA1, and this closed curve may form a trapezoidal (or inverted trapezoidal) shape.

[0265] Furthermore, in Figure 22 In the plan view shown, the first non-circuit region NCA1 may have a trapezoidal (or inverted trapezoidal) shape.

[0266] Figure 23 This is a plan view of a display panel 100 according to one or more embodiments.

[0267] Figure 23 The display panel 100 is in the shape of the first alignment mark AM1 as described above. Figure 8 The display panel 100 is different, and this difference will be mainly described below.

[0268] exist Figure 23 In the plan view shown, the first alignment mark AM1 may have a circular shape. For example, in the plan view, the first alignment mark AM1 may have a closed curve shape that surrounds a portion of the first non-circuit region NCA1, and this closed curve may form a circular shape.

[0269] Furthermore, in Figure 23 In the plan view shown, the first non-circuit region NCA1 may have a circular shape.

[0270] Figure 24 This is a plan view of a display panel 100 according to one or more embodiments.

[0271] Figure 24 The display panel 100 is in the shape of the first alignment mark AM1 as described above. Figure 8 The display panel 100 is different, and this difference will be mainly described below.

[0272] exist Figure 24 In the plan view shown, the first alignment mark AM1 may have a rhombus shape. For example, in the plan view, the first alignment mark AM1 may have a closed curve shape that surrounds a portion of the first non-circuit region NCA1, and this closed curve may form a rhombus shape.

[0273] Furthermore, in Figure 24 In the plan view shown, the first non-circuit region NCA1 can have a rhombus shape.

[0274] Figure 25 This is a plan view of a display panel 100 according to one or more embodiments.

[0275] Figure 25 The display panel 100 is in the shape of the first alignment mark AM1 as described above. Figure 8 The display panel 100 is different, and this difference will be mainly described below.

[0276] exist Figure 25 In the plan view shown, the first alignment mark AM1 may have a pentagonal shape. For example, in the plan view, the first alignment mark AM1 may have a closed curve shape that surrounds a portion of the first non-circuit region NCA1, and this closed curve may form a pentagonal shape.

[0277] Furthermore, in Figure 25 In the plan view shown, the first non-circuit region NCA1 can have a pentagonal shape.

[0278] Figure 26 This is a plan view of a display driver 200 according to one or more embodiments.

[0279] Figure 26 The display driver 200 is in the shape of the second alignment mark AM2 as described above. Figure 9 The display driver 200 is different, and this difference will be mainly described below.

[0280] exist Figure 26 In the plan view shown, the second alignment mark AM2 may have a triangular shape.

[0281] at the same time, Figure 26 The display driver 200 may further include the components described above. Figure 9 The auxiliary alignment mark AXM.

[0282] Figure 27 This is a plan view of a display driver 200 according to one or more embodiments.

[0283] Figure 27 The display driver 200 is in the shape of the second alignment mark AM2 as described above. Figure 9 The display driver 200 is different, and this difference will be mainly described below.

[0284] exist Figure 27 In the plan view shown, the second alignment mark AM2 can have a right-angled triangle shape.

[0285] at the same time, Figure 27 The display driver 200 may further include the components described above. Figure 9 The auxiliary alignment mark AXM.

[0286] Figure 28 This is a plan view of a display driver 200 according to one or more embodiments.

[0287] Figure 28 The display driver 200 is in the shape of the second alignment mark AM2 as described above. Figure 9 The display driver 200 is different, and this difference will be mainly described below.

[0288] exist Figure 28 In the plan view shown, the second alignment mark AM2 may have an arrow shape.

[0289] at the same time, Figure 28The display driver 200 may further include the components described above. Figure 9 The auxiliary alignment mark AXM.

[0290] Figure 29 This is a plan view of a display driver 200 according to one or more embodiments.

[0291] Figure 29 The display driver 200 is in the shape of the second alignment mark AM2 as described above. Figure 9 The display driver 200 is different, and this difference will be mainly described below.

[0292] exist Figure 29 In the plan view shown, the second alignment mark AM2 may have a circular shape.

[0293] at the same time, Figure 29 The display driver 200 may further include the components described above. Figure 9 The auxiliary alignment mark AXM.

[0294] Figure 30 This is a plan view of a display driver 200 according to one or more embodiments.

[0295] Figure 30 The display driver 200 is in the shape of the second alignment mark AM2 as described above. Figure 9 The display driver 200 is different, and this difference will be mainly described below.

[0296] exist Figure 30 In the plan view shown, the second alignment mark AM2 can have a quadrilateral shape.

[0297] at the same time, Figure 30 The display driver 200 may further include the components described above. Figure 9 The auxiliary alignment mark AXM.

[0298] According to one or more embodiments, the display panel 100 may have Figure 8 as well as Figures 21 to 25 Any one of the first alignment marks AM1 shown, and the display driver 200 may have Figure 9 as well as Figures 26 to 30 Any one of the second alignment marks AM2 shown.

[0299] Figure 31 According to one or more other embodiments Figure 2 A magnified view of region A1, and Figure 32 yes Figure 31 A magnified view of region A3.

[0300] Figure 31 Display device and Figure 6 The difference in the display device is that it further includes a third alignment mark AM3. The following description will focus primarily on this difference.

[0301] The display device of one or more embodiments may further include a third alignment mark AM3, such as Figure 31 and Figure 32 As shown in the image.

[0302] The third alignment mark AM3 may be located in the sub-area SBA (or pad area) of the display panel 100. For example, when multiple third alignment marks AM3 are provided, one third alignment mark AM3 may be located between one edge of the display driver 200 and one edge of the display panel 100, and another third alignment mark AM3 may be located between another edge of the display driver 200 and another edge of the display panel 100.

[0303] The third alignment mark AM3 can be positioned adjacent to the first alignment mark AM1. For example, when multiple third alignment marks AM3 are provided, one third alignment mark AM3 can be positioned adjacent to the first alignment mark AM1 that overlaps with one edge of the display driver 200, and another third alignment mark AM3 can be positioned adjacent to the first alignment mark AM1 that overlaps with another edge of the display driver 200.

[0304] Alignment between the display panel 100 and the display driver 200 can be performed using a first alignment mark AM1, a second alignment mark AM2, and a third alignment mark AM3. In this case, the alignment state between the display panel 100 and the display driver 200 can be determined based on the distance between the third alignment mark AM3 of the display panel 100 and the second alignment mark AM2 of the display driver 200. For example, when the distance between one edge of the third alignment mark AM3 and the center portion of the second alignment mark AM2 meets the tolerance, it can be determined that the display panel 100 and the display driver 200 are aligned with each other.

[0305] Figures 33 to 39 This is a view illustrating a method of manufacturing a display device according to one or more embodiments.

[0306] First, such as Figure 33As shown, the first alignment mark AM1 of the display panel 100 can be imaged by the imaging device 800. For example, when the display panel 100 includes two first alignment marks AM1, each first alignment mark AM1 can be imaged sequentially. Here, the imaging device 800 can be, for example, a camera. According to one or more embodiments, the imaging device 800 can be above the top surface of the display panel 100 (e.g., the surface away from the semiconductor substrate SSUB) and can image the first alignment mark AM1 of the display panel 100. However, this disclosure is not limited to this, and for example, the imaging device 800 can be below the bottom surface of the display panel 100 (e.g., the bottom surface of the semiconductor substrate SSUB) and can image the first alignment mark AM1 of the display panel 100.

[0307] Next, as Figure 34 As shown, the coordinates of the center portion CP1 of the first alignment mark AM1 can be calculated. For example, the coordinates of the center portion CP1 of the first alignment mark AM1 located on one side of the display panel 100 and the coordinates of the center portion CP1 of the first alignment mark AM1 located on the other side of the display panel 100 can be calculated. Next, the coordinates of the midpoint of the line segment connecting the center portions CP1 of the first alignment mark AM1 located on one side of the display panel 100 and the center portions CP1 of the first alignment mark AM1 located on the other side of the display panel 100 can be calculated. In other words, the coordinates of the center portion of the imaginary line segment connecting the center portions CP1 of the first alignment marks AM1 can be calculated (hereinafter referred to as the first coordinates).

[0308] Next, as Figure 35 As shown, the second alignment mark AM2 of the display driver 200 can be imaged by the imaging device 800. For example, when the display driver 200 includes two second alignment marks AM2, each second alignment mark AM2 can be imaged sequentially. In this case, the auxiliary alignment mark AXM can also be imaged together. According to one or more embodiments, the imaging device 800 can be located on or below the bottom surface of the display driver 200 (e.g., the bottom surface of the substrate SUB) and can image the second alignment mark AM2 of the display driver 200. However, this disclosure is not limited thereto, and the imaging device 800 can be located on or above the top surface of the display driver 200 (e.g., the surface away from the substrate SUB) and can image the second alignment mark AM2 of the display driver 200.

[0309] Next, as Figure 36As shown, the coordinates of the center portion CP2 of the second alignment mark AM2 can be calculated. For example, the coordinates of the center portion CP2 of the second alignment mark AM2 located on one side of the display driver 200 and the coordinates of the center portion CP2 of the second alignment mark AM2 located on the other side of the display driver 200 can be calculated. Next, the coordinates of the midpoint of the line segment connecting the center portions CP2 of the second alignment mark AM2 located on one side of the display driver 200 and the center portions CP2 of the second alignment mark AM2 located on the other side of the display driver 200 can be calculated. In other words, the coordinates of the center portion of the imaginary line segment connecting the center portions CP2 of the second alignment marks AM2 can be calculated (hereinafter referred to as the second coordinates).

[0310] Next, as Figure 37 As shown, the display driver 200 and the display panel 100 can be aligned with each other based on the first and second coordinates described above, and the bonding process between the display driver 200 and the display panel 100 can be performed while the display driver 200 and the display panel 100 are aligned. For example, the display driver 200 can be positioned on the display panel 100 in the aligned state, and the display driver 200 and the display panel 100 can be physically and electrically connected to each other via the bonding device 900. The anisotropic conductive film described above can be located between the display driver 200 and the display panel 100.

[0311] The engagement device 900 may include a head 910 and a support portion 920.

[0312] The head 910 of the bonding device 900 can press the display driver 200 from the top side. Accordingly, the display driver 200 and the display panel 100 can be physically and electrically connected to each other through anisotropic conductive films.

[0313] The support portion 920 of the bonding device 900 can support the display panel 100 from the lower side. For example, the support portion 920 can support the bottom surface of the semiconductor substrate SSUB of the display panel 100.

[0314] According to one or more embodiments, such as Figure 37 As shown, the display panel 100 may further include a packaging substrate ENC, and as described above Figure 5 The components between the optical layer OPL and the semiconductor substrate SSUB can be located between the packaging substrate ENC and the semiconductor substrate SSUB.

[0315] Next, as Figure 38As shown, a process for checking the alignment status between the display driver 200 and the display panel 100 can be performed. For example, after positioning the imaging device 850 below the display panel 100, the imaging device 850 can image the first alignment mark AM1 and the second alignment mark AM2 together in the overlapping area of ​​the display panel 100 and the display driver 200. Here, the imaging device 850 can be, for example, a short-wavelength infrared (SWIR) camera.

[0316] After that, as Figure 39 As shown, when the center portion CP1 of the first alignment mark AM1 and the center portion CP2 of the second alignment mark AM2 do not coincide, the display driver 200 can move in at least one of the following directions: a first direction DR1, the opposite direction of the first direction DR1 (hereinafter referred to as the first opposite direction), a second direction DR2, and the opposite direction of the second direction DR2 (hereinafter referred to as the second opposite direction), so that the display driver 200 and the display panel 100 can be aligned with each other. For example, as Figure 39 As shown, when the center portion CP1 of the first alignment mark AM1 (or the coordinates of the center portion CP1 of the first alignment mark AM1) and the center portion CP2 of the second alignment mark AM2 (or the coordinates of the center portion CP2 of the second alignment mark AM2) do not coincide, the display driver 200 can be moved ΔX in a first opposite direction by means of the device, and subsequently, it can be moved further ΔY in a second opposite direction. Accordingly, the center portion CP1 of the first alignment mark AM1 and the center portion CP2 of the second alignment mark AM2 coincide, and therefore, the display driver 200 and the display panel 100 can be aligned with each other.

[0317] Figure 40 This is a view illustrating a method of manufacturing a display device according to one or more embodiments.

[0318] As in Figure 40 In the example shown, the head 910 of the engagement device 900 can hold the display driver 200.

[0319] The imaging device 850 can image the first alignment mark AM1 of the display panel 100 and the second alignment mark AM2 of the display driver 200 from the lower side of the display panel 100. The imaging device 850 detects in real time whether the first alignment mark AM1 and the second alignment mark AM2 overlap, and can move the joining device 900 (e.g., the head 910 of the joining device 900) in at least one of the first direction DR1, the first reverse direction, the second direction DR2, and the second reverse direction based on the detection result. For example, the joining device 900 is moved such that the center portion CP1 of the first alignment mark AM1 and the center portion CP2 of the second alignment mark AM2 overlap, thereby aligning (e.g., preliminary alignment) the display driver 200 and the display panel 100 before they are joined together. After initial alignment, the head 910 of the engagement device 900 can be lowered in the direction toward the display panel 100 (e.g., the opposite direction of the third direction DR3 (hereinafter referred to as the third opposite direction)), and then the display driver 200 can be pressed, thereby initially engaging the display driver 200 and the display panel 100.

[0320] According to one or more embodiments, the first alignment mark AM1 of the display panel 100 is made of metal, and the first alignment mark AM1 has a shape that surrounds an insulating film made of non-metallic material, thereby improving the ability to distinguish (or identify) the first alignment mark AM1.

[0321] According to one or more embodiments, the second alignment mark AM2 of the display driver 200 is made of metal, and the second alignment mark AM2 has a shape surrounded by an insulating film made of a non-metallic material, thereby improving the ability to distinguish the second alignment mark AM2.

[0322] According to one or more embodiments, an insulating film surrounded by a first alignment mark AM1 overlaps with a second alignment mark AM2 made of a metallic material, and an insulating film surrounding the second alignment mark AM2 overlaps with the first alignment mark AM1 made of a metallic material, thereby improving the ability to distinguish the first alignment mark AM1 and the second alignment mark AM2 on the display panel 100 and the display driver 200 that are joined together.

[0323] Accordingly, even when manufacturing the display device 10 on a wafer comprising a plurality of conductive layers ML1 to ML8, the ability to distinguish the first alignment mark AM1 and the second alignment mark AM2 can be improved. Therefore, the first alignment mark AM1 of the display panel 100 and the second alignment mark AM2 of the display driver 200 can be accurately identified by the imaging device 850.

[0324] The display device according to this embodiment can be applied to various electronic devices. An electronic device according to one embodiment includes the display device described above, and may further include modules or devices with additional functions in addition to the display device.

[0325] Figure 41 This is a block diagram of an electronic device according to one embodiment. (Reference) Figure 41 According to one embodiment, the electronic device 50 may include a display module 11, a processor 12, a memory 13, and a power module 14. The electronic device 50 may further include an input module 15, an output module 16, and / or a communication module 17.

[0326] Electronic device 50 can output various information in image form through display module 11. When processor 12 executes an application stored in memory 13, the image information provided by the application can be provided to the user through display module 11. Power module 14 may include a power supply module such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power supply module to generate the power required for the operation of electronic device 50. Input module 15 can provide input information to processor 12 and / or display module 11. Output module 16 can receive information other than images (such as sound, touch, and light) transmitted from processor 12 and provide this information to the user. Communication module 17 is responsible for transmitting and receiving information between electronic device 50 and external devices, and may include receiving unit and transmitting unit.

[0327] At least one of the components of the electronic device 50 described above may be included in the display device according to the embodiments described above. Furthermore, some individual modules that are functionally included in a single module may be included in the display device, while other individual modules may be provided separately from the display device. For example, the display device includes a display module 11, and the processor 12, memory 13, and power module 14 may be provided within the electronic device 50 in the form of other devices besides the display device.

[0328] Figure 42 , Figure 43 and Figure 44 These are schematic diagrams of electronic devices according to various embodiments. Figures 42 to 44 The figures illustrate examples of various electronic devices to which a display device according to an embodiment is applied.

[0329] Figure 42 The illustration shows a smartphone 10_1a, a tablet PC 10_1b, a laptop computer 10_1c, a television 10_1d, and a desktop monitor 10_1e as examples of electronic devices.

[0330] In addition to the display module 11, the smartphone 10_1a may also include a communication module 17 and an input module 15, such as a touch sensor. The smartphone 10_1a can process information received through the communication module 17 or input through the input module 15, and display the information through the display module 11 of the display device.

[0331] In the case of tablet PC 10_1b, laptop computer 10_1c, television 10_1d, and desktop monitor 10_1e, they are similar to smartphone 10_1 and also include display module 11 and input module 15, and in some cases may additionally include communication module 17.

[0332] Figure 43 An example of an electronic device including a display module is shown that is applied to a wearable electronic device. The wearable electronic device may be smart glasses 10_2a, a head-mounted display 10_2b, a smartwatch 10_2c, etc.

[0333] The smart glasses 10_2a and the head-mounted display 10_2b may include a display module that emits a display image and a reflector that reflects the emitted display image and provides it to the user's eyes, thereby providing the user with a virtual reality image or an augmented reality image.

[0334] The smartwatch 10_2c includes a biometric sensor as an input device, and the biometric information identified by the biometric sensor can be provided to the user through a display module. Figure 44 The illustration shows an application of an electronic device, including a display module, to a vehicle. For example, the electronic device 10_3 can be applied to the vehicle's dashboard, central instrument panel, etc., or it can be applied to a CID (Central Information Display) placed on the vehicle's dashboard or an interior mirror display that replaces the side mirrors.

[0335] Those skilled in the art to which this disclosure pertains will understand that this disclosure may be implemented in other forms without altering any aspects thereof. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. It should be understood that the scope of this disclosure is defined by the claims rather than the detailed description described above, and all modifications and alterations derived from the claims and their equivalents fall within the scope of this disclosure.

Claims

1. A display device, comprising: Display panel; A first alignment mark is located in a first non-circuit area of ​​the display panel and has a closed curve shape that surrounds at least a portion of the first non-circuit area. The display driver is connected to the display panel; as well as The second alignment mark is located in and surrounded by the second non-circuit region of the display driver. Wherein, the second alignment mark is not in contact with the first alignment mark and the metal in the first non-circuit region.

2. The display device according to claim 1, wherein The first alignment mark and the second alignment mark are made of metal. Wherein, the first alignment mark is located at the edge of the first non-circuit region, and The second alignment mark is located at the center of the second non-circuit region.

3. The display device according to claim 1, wherein The second non-circuit region has a larger area than the first non-circuit region.

4. The display device according to claim 1, wherein, The internal region defined by the first alignment mark has an area larger than that of the second alignment mark.

5. The display device according to claim 1, wherein, The internal region defined by the first alignment mark has a smaller area than the area of ​​the second non-circuit region.

6. The display device according to claim 1, wherein, In the plan view, the first alignment mark surrounds the insulating film of the first non-circuit region.

7. The display device according to claim 1, wherein, In the plan view, the second alignment mark is surrounded by the insulating film of the second non-circuit region.

8. The display device according to claim 1, wherein, In the plan view, the first alignment mark surrounds the second alignment mark.

9. The display device according to claim 1, wherein, In the plan view, the edge of the second non-circuit region surrounds the first alignment mark.

10. The display device according to claim 1, further comprising: The first dummy pattern is in the display panel and is on a different layer from the first alignment mark.

11. The display device according to claim 10, wherein, The first dummy pattern is closer to the substrate of the display panel than the first alignment mark.

12. The display device according to claim 10, wherein, In the plan view, the first dummy pattern is surrounded by the first alignment mark.

13. The display device according to claim 10, wherein, In the plan view, the first dummy pattern is adjacent to the corner of the first alignment mark.

14. The display device according to claim 10, wherein, In the plan view, the first dummy pattern is in the remainder of the inner area defined by the first alignment mark, excluding the corner of the first alignment mark.

15. The display device according to claim 1, wherein, The first alignment mark includes: The outer pattern is located at the edge of the first non-circuit region; and The prominent pattern stands out from the outer pattern.

16. The display device according to claim 1, further comprising: The second dummy pattern is in the display driver and is located on a different layer from the second alignment mark. The second dummy pattern is closer to the substrate of the display driver than the second alignment mark.

17. The display device according to claim 1, further comprising: A third alignment mark is located on the display panel, adjacent to the first alignment mark. The third alignment mark is adjacent to the edge of the display driver.

18. The display device according to claim 1, further comprising: An auxiliary alignment mark is located in the second non-circuit region, adjacent to one side of the second alignment mark.

19. The display device according to claim 1, wherein, The first alignment mark has a quadrilateral shape, and The second alignment mark has a cross shape.

20. An electronic device comprising: processor; Battery; as well as The display device according to any one of claims 1 to 19 is connected to the processor and the battery.

Images