A data bus switching circuit
By controlling the data bus flipping through the DBI calculation circuit and mask generation circuit, the power loss problem during continuous data transmission in dynamic random access memory is solved, achieving more efficient data transmission.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- ZHEJIANG LIJI ELECTRONICS CO LTD
- Filing Date
- 2025-08-18
- Publication Date
- 2026-06-30
AI Technical Summary
In existing technologies for dynamic random access memory, unnecessary data bus flips cannot be avoided during continuous large-scale data transfers, leading to increased power consumption.
The DBI calculation circuit and DBI mask generation circuit calculate the data flip signal and generate the mask signal to control the enabling of data bus flips and reduce unnecessary flips.
It effectively reduces power loss during data transmission and improves the energy efficiency of data transmission.
Smart Images
Figure CN224437189U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of semiconductor memory design technology, and in particular relates to a data bus switching circuit. Background Technology
[0002] Starting with the fourth generation of Double Data Rate Synchronous Dynamic Random Access Memory (DDR4), Data Bus Inversion (DBI) was added to Dynamic Random Access Memory (DRAM). When the number of 0s or 1s in a byte is greater than a preset value, the 0s and 1s are flipped to reduce dynamic power consumption.
[0003] DBI (Distributed Bidirectional Interchange) reduces power consumption to some extent by keeping more signals in a high-level (or low-level, depending on the circuit design) state by toggling data on the bus. This feature also helps improve signal integrity, with fewer signals switching states and less noise on the signal lines, thus improving signal quality and transmission stability.
[0004] However, since the data flip signal needs to be based on the previous data, and subsequent data needs to be flipped a large number of times, the existing technology cannot avoid such a large number of continuous flips, which increases the power loss during data transmission. Utility Model Content
[0005] The purpose of this invention is to address the above-mentioned problems by providing a data bus switching circuit that controls whether to enable data bus switching when continuously transmitting large amounts of data, thereby reducing unnecessary switching and thus reducing power loss during data transmission.
[0006] To achieve the above objectives, the technical solution adopted by this utility model is as follows:
[0007] A data bus switching circuit, comprising:
[0008] The DBI calculation circuit is used to calculate the data flip signal corresponding to the current input data, and consists of a register, a comparator, and an arithmetic circuit.
[0009] The DBI mask generation circuit consists of an accumulation circuit and a comparison circuit. The input terminal of the accumulation circuit is connected to the output terminal of the DBI calculation circuit, and the output terminal of the accumulation circuit is connected to the input terminal of the comparison circuit.
[0010] The data processing circuit includes a DBI processing circuit and a data flipping circuit, wherein the DBI processing circuit is connected to the output of the comparison circuit and the output of the DBI calculation circuit.
[0011] The output of the register is connected to the input of the comparator. The register is used to buffer and output the previous data and the corresponding data toggle signal to the comparator.
[0012] The comparator is used to generate a corresponding data flip signal and input it to the arithmetic circuit.
[0013] The arithmetic circuit includes an AND gate connected to the comparator and an XOR gate connected to the output of the AND gate;
[0014] The other input of the XOR gate receives the current input data.
[0015] The input of the AND gate is connected to the output of the comparator, and the output of the AND gate is connected to the adder in the accumulator circuit.
[0016] The accumulation circuit includes an adder and a register connected to the output of the adder;
[0017] The adder is used to calculate the number of data points in the input data that need to be flipped, and the register is connected to the comparison circuit.
[0018] The comparison circuit includes a comparator, the input of which is connected to the output of the register, and the output of which is connected to the data processing circuit.
[0019] The DBI processing circuit includes a first NOT gate connected to the comparison circuit and a first AND gate connected to the DBI calculation circuit.
[0020] The input terminal of the first NOT gate is connected to the output terminal of the comparator in the comparison circuit, and the output terminal of the first NOT gate is connected to the input terminal of the first AND gate.
[0021] The other input of the first AND gate is connected to the output of the AND gate in the DBI calculation circuit.
[0022] The data flipping circuit includes:
[0023] The second NOT gate is connected to the output of the first AND gate;
[0024] And a second AND gate, the input of which is connected to the output of the second NOT gate and the output of the XOR gate in the DBI calculation circuit.
[0025] The beneficial effects of this utility model are:
[0026] This application provides a data bus switching circuit that controls whether to enable data bus switching when continuously transmitting large amounts of data, thereby reducing unnecessary switching and thus reducing power loss during data transmission.
[0027] To make the above and other objects, features and advantages of this utility model more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description
[0028] To more clearly illustrate the technical solutions in the specific embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0029] Figure 1 This is a schematic diagram of a data bus flipping circuit provided in Embodiment 1 of this application.
[0030] Figure 2 This is a schematic diagram of the DBI calculation circuit provided in Embodiment 1 of this application.
[0031] Figure 3 This is a schematic diagram of parallel data provided for Embodiment 1 of this application.
[0032] Figure 4 This is a schematic diagram of the output results provided in Embodiment 1 of this application.
[0033] Figure 5 This is a comparison chart of the number of data flips provided in Embodiment 1 of this application with the existing DBI scheme. Detailed Implementation
[0034] The foregoing and other technical contents, features, and effects of this utility model will be clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front, or back, are only for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the scope of this utility model.
[0035] Example 1
[0036] like Figure 1 As shown, a data bus switching circuit includes:
[0037] The DBI calculation circuit calculates the data inversion signal corresponding to the current input data based on the previous data and the data inversion signal corresponding to the previous data.
[0038] The DBI mask generation circuit receives the input data flip signal, calculates the number of data that need to be flipped in the input data based on the data flip signal, compares the number of data that need to be flipped with a preset value, and outputs the corresponding mask signal.
[0039] The data processing circuit processes the data to be transmitted based on the mask signal. If the mask signal is valid, the data to be transmitted is not flipped; if the mask signal is invalid, the data to be transmitted is either flipped or not flipped according to the data flip signal.
[0040] Among them, such as Figure 1 As shown, the DBI mask generation circuit includes: an accumulation circuit for calculating the number of data to be flipped in the input data, and a comparison circuit for comparing the number of data to be flipped with a preset value.
[0041] Specifically, the process by which the DBI calculation circuit calculates the data inversion signal corresponding to the current input data includes:
[0042] The current input data is compared with the previous data to determine the number of bits that need to be flipped in the current input data. Based on the number of bits that need to be flipped in the current input data and the data flip signal corresponding to the previous data, the data flip signal corresponding to the current input data is determined.
[0043] Typically, we use 8-bit DQ (data lines) as a group and calculate a corresponding data toggle signal. In the DQ transmission used in this application, if the data to be transmitted now is the same as the data we transmitted last time, for example, both are 00000010, then we do not need to toggle the 8-bit data lines when transmitting the current data, which is the most power-saving case. The fewer the number of toggles, the more power-saving it is.
[0044] Examples are given below:
[0045] The current input data is compared with the previous data. For example, if the current input data is 11101110 (represented as the first to eighth bits from left to right), and the previous data is 00000010, the previous DBI (data inversion signal is 0) is compared bit by bit in both data sets. The first bit, which was 0 in the previous data set, is 1 in the current data set. This means that if we transmit the current data without any processing, the first data line needs to be inverted.
[0046] The first digit: from 0 to 1, needs to be flipped;
[0047] The second digit: from 0 to 1, needs to be flipped;
[0048] The third digit: from 0 to 1, needs to be flipped;
[0049] The fourth digit: from 0 to 0, no flipping required;
[0050] The fifth digit: from 0 to 1, needs to be flipped;
[0051] The sixth digit: from 0 to 1, needs to be flipped;
[0052] The seventh digit: from 1 to 1, no flipping required;
[0053] The eighth digit: from 0 to 0, no flipping required;
[0054] In summary, a total of five flips are required. Assuming our comparator preset value is 4, since 5 > 4 (compared by the comparator), the corresponding data flip signal is set to 1.
[0055] Figure 2 The diagram shown is a schematic of the DBI calculation circuit provided in Embodiment 1 of this application.
[0056] like Figure 2 As shown, the DBI calculation circuit includes: a register, a comparator, and an arithmetic circuit;
[0057] The previous data and its corresponding data toggle signal are input to the register, buffered by the register, and then output to the comparator.
[0058] The comparator compares the current input data with the previous data to determine the number of bits that need to be flipped in the current input data, decides whether to flip, and generates the corresponding data flip signal.
[0059] The comparator inputs the data inversion signal to the arithmetic circuit. The input data is input to the arithmetic circuit in parallel and performs logical operations with the data inversion signal to convert it into the corresponding sequence data, which is then output to the data processing circuit as the data to be transmitted.
[0060] The arithmetic circuit inputs the current input data and the corresponding data toggle signal to the register.
[0061] Specifically, if the number of bits that need to be flipped in the current input data is greater than 1 / 2 of the total number of bits, then flipping is required and the data flip signal output is 1; otherwise, no flipping is required and the data flip signal output is 0.
[0062] like Figure 1 As shown, the accumulator circuit receives the data flip signal corresponding to the input data, performs addition on the number of data that need to be flipped in the input data, and outputs the accumulation result to the comparator circuit.
[0063] Specifically, the accumulator circuit includes an adder and a register connected to the output of the adder.
[0064] like Figure 1As shown, the comparison circuit includes a comparator, which compares the accumulated result with a preset value and outputs a corresponding mask signal. If the number of data to be flipped is greater than the preset value, the corresponding output mask signal is 1, and the mask signal is valid; otherwise, the corresponding output mask signal is 0, and the mask signal is invalid.
[0065] Specifically, taking eight-bit data as an example, the DRAM core (input data) inputs eight bits of data (the data to be transmitted is usually represented by DQ). The 9 in device ① represents the nine bits of input data, including eight DQ bits and one DBI bit. The function of device ① is to hold the data from the previous moment (it is the preprocessing for DBI calculation). These nine bits of data are sent to device ② (comparator). The other set of input data of device ② (that is, the line above) represents the nine bits of input data (at this moment). The comparator compares the data at this moment with the data at the previous moment to determine whether there are more than 4 bits of different data, and then generates the corresponding DBI value. Device ② (comparator) generates the corresponding DBI value and inputs it to device ③ (AND gate). It enters device ④ (XOR gate) through device ③ (AND gate) and performs an XOR logic operation with the eight-bit DQ input at the other input terminal of device ④ (XOR gate). The DQ that has been toggled or not toggled according to the DBI is then sent out.
[0066] like Figure 2 As shown, writing 8 indicates DQ, and writing 9 indicates eight-bit DQ and one-bit DBI. This means that there are 8 or 9 identical devices. When DQ and DBI are sent out, there is another branch, which sends the data at this moment back and compares it with the data at the next moment.
[0067] like Figure 1 As shown, the DBI calculation circuit outputs the data to be transmitted and the data inversion signal, which enters the data processing circuit. The comparison circuit outputs the mask signal, which enters the data processing circuit.
[0068] Figure 3 The diagram shown is a parallel data schematic provided in Embodiment 1 of this application. The input data is input to the DBI calculation circuit in the form of parallel data, and converted into corresponding sequence data as data to be transmitted and output to the data processing circuit.
[0069] Data from external devices to memory needs to be converted from parallel data to sequential data. The usual practice for DBI is to process the sequential data after converting it from parallel data to sequential data, and then output the DBI. The technical solution of this application processes the data after converting it from parallel data.
[0070] like Figure 1 As shown, the data processing circuit includes a DBI processing circuit and a data flipping circuit;
[0071] The DBI processing circuit processes the data inversion signal based on the mask signal and outputs the processing result to the data inversion circuit.
[0072] The data flipping circuit processes the data to be transmitted based on the processing results.
[0073] Specifically, if the mask signal is valid, the processing result is 0, and the data to be transmitted is output directly without being flipped;
[0074] If the mask signal is invalid, the data flipping circuit will either flip the data to be transmitted or not flip it, depending on the data flipping signal.
[0075] like Figure 4 As shown, the calculated DBI value represents the data flip signal corresponding to the input data. The output data is determined based on the DBI value and the DBI mask. If the DBI mask is invalid, the data is flipped or not flipped according to the calculated DBI value. If the DBI mask is valid, the calculated DBI value is ignored, the original data is output, and the final output DBI value is set to no flipping.
[0076] like Figure 5 As shown, taking 8-bit data as an example, if the previous data (denoted as data 0) is 1111_1100, and the data from 1 to n is 0000_0001; if data 0 is transmitted as 1111_1110, then data from 1 to n will all be flipped to 1111_1110 for transmission; Figure 5 (a) represents an existing DBI scheme, such as Figure 5 (b) represents the DBI scheme of this application. Figure 5 The orange portion in (a) represents the data flipping action performed by the existing DBI scheme. The more consecutive flips are performed, the greater the power loss caused by the flipping. Therefore, the DBI scheme of this application can effectively reduce the power loss during data transmission.
[0077] Specifically, taking 8-bit data as an example, if the previous data (denoted as the 0th data) is 1111_1100, and the data from the 1st to the nth data is 0000_0001; the data inversion signal corresponding to the current input data is calculated based on the previous data and the data inversion signal corresponding to the previous data.
[0078] The DBI mask generation circuit receives the input data flip signal and calculates the number of data that need to be flipped in the input data based on the data flip signal (using an accumulator to accumulate the number of flips). It then compares the number of data that need to be flipped with a preset value. If the number of flips is greater than the preset value, it outputs the corresponding mask signal (the DBI value is fed into the accumulator. If the result output by the accumulator is greater than the preset value in the comparator, the corresponding DBI mask 1 is output. If the result added by the adder is less than the preset value, the corresponding DBI mask 0 is output. This application outputs the corresponding DBI mask 1).
[0079] The mask signal 1 is input to the data processing circuit for processing (the mask signal 1 is a valid mask signal and does not flip the data to be transmitted). Finally, the first to nth data are transmitted directly as 0000_0001 without flipping.
[0080] like Figure 5 As shown in (a), if according to Figure 5 In the DBI scheme of (a), starting from the second data, each data needs to be flipped 8 times, and the DBI port flips once.
[0081] like Figure 5 As shown in (b), if according to Figure 5 In the DBI scheme of (b), the second data is not flipped. (At this time, the data transfer process between the previous and current data cannot be omitted; it only refers to the fact that when transferring the second data, there is no...) Figure 5 The DBI scheme in (a) is power-saving. The DBI port (the final output DBI) is not flipped, and the DBI port is not flipped afterward. In this case, the longer the data link, the more power-saving it is (the power saving in this application is the power required for flipping the original data into the data to be transmitted. The fewer the flips, the more power-saving it is. That is, this application saves the power required for data flipping in the existing DBI scheme).
[0082] Although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.
[0083] The detailed descriptions listed above are merely specific descriptions of feasible implementations of this utility model, and are not intended to limit the scope of protection of this utility model. All equivalent implementations or modifications made without departing from the spirit of this utility model should be included within the scope of protection of this utility model.
Claims
1. A data bus switching circuit, characterized in that, include: The DBI calculation circuit is used to calculate the data flip signal corresponding to the current input data, and consists of a register, a comparator, and an arithmetic circuit. The DBI mask generation circuit consists of an accumulation circuit and a comparison circuit. The input terminal of the accumulation circuit is connected to the output terminal of the DBI calculation circuit, and the output terminal of the accumulation circuit is connected to the input terminal of the comparison circuit. The data processing circuit includes a DBI processing circuit and a data flipping circuit, wherein the DBI processing circuit is connected to the output of the comparison circuit and the output of the DBI calculation circuit.
2. The data bus switching circuit according to claim 1, characterized in that, The output of the register is connected to the input of the comparator. The register is used to buffer and output the previous data and the corresponding data toggle signal to the comparator.
3. A data bus switching circuit according to claim 2, characterized in that, The comparator is used to generate a corresponding data flip signal and input it to the arithmetic circuit.
4. A data bus switching circuit according to claim 3, characterized in that, The arithmetic circuit includes an AND gate connected to the comparator and an XOR gate connected to the output of the AND gate; The other input of the XOR gate receives the current input data.
5. A data bus switching circuit according to claim 4, characterized in that, The input of the AND gate is connected to the output of the comparator, and the output of the AND gate is connected to the adder in the accumulator circuit.
6. A data bus switching circuit according to claim 1, characterized in that, The accumulation circuit includes an adder and a register connected to the output of the adder; The adder is used to calculate the number of data points in the input data that need to be flipped, and the register is connected to the comparison circuit.
7. A data bus switching circuit according to claim 6, characterized in that, The comparison circuit includes a comparator, the input of which is connected to the output of the register, and the output of which is connected to the data processing circuit.
8. A data bus switching circuit according to claim 1, characterized in that, The DBI processing circuit includes a first NOT gate connected to the comparison circuit and a first AND gate connected to the DBI calculation circuit.
9. A data bus switching circuit according to claim 8, characterized in that, The input terminal of the first NOT gate is connected to the output terminal of the comparator in the comparison circuit, and the output terminal of the first NOT gate is connected to the input terminal of the first AND gate. The other input of the first AND gate is connected to the output of the AND gate in the DBI calculation circuit.
10. A data bus switching circuit according to claim 9, characterized in that, The data flipping circuit includes: The second NOT gate is connected to the output of the first AND gate; And a second AND gate, the input of which is connected to the output of the second NOT gate and the output of the XOR gate in the DBI calculation circuit.