Detachable test device and chip test system

Abstract

This invention provides a detachable testing device and a chip testing system. The detachable testing device includes an interface testing board and a signal processing board. The interface testing board includes a first control module, a first differential signal interface, and at least one interface module. The signal processing board includes a second control module, a second differential signal interface, and at least one third differential signal interface. The D+ and D- pins of the second differential signal interface are directly connected to the corresponding D+ and D- pins of the third differential signal interface. The performance of the second control module is superior to that of the first control module. The interface testing board and the signal processing board can work independently or in combination. This invention not only achieves comprehensive coverage of testing requirements but also features simple wiring, ease of use, and low cost.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor testing, and in particular to a detachable testing device and a chip testing system. Background Technology

[0002] With the rapid development and increasing maturity of the semiconductor industry, the requirements for chip testing systems are becoming increasingly stringent. Taking the testing of the MIPI (Mobile Industry Processor Interface) protocol, commonly used in the RFFE (RF Front End Interface) field, as an example, the testing equipment needs to meet the following requirements: (1) It should be able to send and detect MIPI waveforms at a rate of 52MHz; (2) The connection between the testing equipment and the chip under test should ideally be less than 15cm; (3) It should be able to change parameters such as voltage and frequency of the test waveform; (4) It should be able to analyze waveform voltage with nanosecond-level accuracy; (5) It should be able to perform high and low temperature tests; and (6) The testing time should be as short as possible. However, due to limitations such as cost and technology, it is usually difficult for testing equipment to meet all of the above requirements simultaneously. In reality, it is necessary to use multiple testing equipment to make trade-offs in test indicators for different test items, which has one or more drawbacks such as difficulty in fully covering test requirements, complex wiring, and inconvenience of use.

[0003] It should be noted that the information disclosed in the background section of this utility model is intended only to enhance the understanding of the general background of this utility model, and should not be regarded as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Utility Model Content

[0004] The purpose of this invention is to address one or more of the problems in existing technologies, such as the need for multiple testing devices to perform different test items in communication protocol testing, which makes it difficult to fully cover test requirements, complex wiring, and inconvenient to use. This invention provides a detachable testing device and chip testing system that can not only achieve comprehensive coverage of test requirements, but also has simple wiring, is easy to use, and has a low cost.

[0005] To achieve the above objectives, this utility model provides the following technical solution: a detachable testing device that tests the device under test using a first test signal. The detachable testing device includes an interface test board and a signal processing board. The interface test board includes a first control module, a first differential signal interface, and at least one interface module. The signal processing board includes a second control module, a second differential signal interface, and at least one third differential signal interface. The D+ and D- pins of the second differential signal interface are directly connected to the D+ and D- pins of the third differential signal interface. The performance of the second control module is superior to that of the first control module.

[0006] When the interface test board operates independently, the first differential signal interface is coupled to the host computer, the interface module is coupled to the device under test (DUT), and the first control module works with the host computer to test the DUT. When the signal processing board operates independently, the second differential signal interface is coupled to the host computer, the third differential signal interface is coupled to the DUT, and the second control module works with the host computer to test the DUT. When the interface test board and the signal processing board operate together, the second differential signal interface is coupled to the host computer, the third differential signal interface is connected to the first differential signal interface, the interface module is coupled to the DUT, and the first and second control modules work with the host computer to test the DUT.

[0007] Optionally, the first test signal includes a MIPI signal.

[0008] Optionally, both the first differential signal interface and the third differential signal interface are full-function 24-pin Type-C interfaces, and the second differential signal interface is a 16-pin Type-C interface.

[0009] Optionally, the interface test board further includes a first communication module; the D+ and D- pins of the first differential signal interface are correspondingly coupled to the D+ and D- pins of the first communication module, the TX pin and SUB&CC pin of the first differential signal interface are coupled to the first control module, the RX pin and TX pin of the first differential signal interface are correspondingly coupled to the TX pin and RX pin of the interface module, the first control module is coupled to the interface module, and the interface module is configured to provide a first test signal to the device under test.

[0010] Optionally, when the interface test board operates independently, the first control module is configured to encode a test signal according to the test instructions from the host computer to obtain a preliminary test signal, and to detect the first test signal and feed back the obtained first detection result to the host computer. The interface module is configured to obtain the first test signal according to the preliminary test signal and send the first test signal to the device under test. When the interface test board and the signal processing board work together, the signal processing board is configured to configure the test parameters of the interface test board according to the test instructions from the host computer, and is also configured to generate a second test signal according to the test instructions, and send the second test signal to the interface module of the interface test board in the form of a differential signal. The interface module is configured to convert the second test signal of the differential signal into a single-ended signal to obtain the first test signal, and to detect the first test signal according to the test instructions from the host computer to obtain a second detection result. It is also configured to return the second detection result to the signal processing board in the form of a differential signal.

[0011] Optionally, the interface test board further includes a first power supply module electrically connected to the first control module, the first communication module, and the interface module. The first power supply module is coupled to the VBUS pin of the first differential signal interface and is configured to convert the received first input voltage into the first power supply voltage required by the first control module, the first communication module, and the interface module, respectively.

[0012] Optionally, the interface module further includes a programmable control chip, and the first power supply module further includes a first programmable power supply electrically connected to the programmable control chip; the programmable control chip is configured to generate the first test signal according to the test instructions of the host computer and to test the device under test; the first programmable power supply is configured to convert the first input voltage into a second power supply voltage required by the programmable control chip.

[0013] Optionally, the signal processing board further includes a second communication module electrically connected to the second control module. The D+ and D- pins of the second differential signal interface are also correspondingly coupled to the D+ and D- pins of the second communication module. The SUB&CC, RX, and TX pins of the second control module are correspondingly coupled to the SUB&CC, TX, and RX pins of the third differential signal interface. The second control module is coupled to the third differential signal interface.

[0014] Optionally, when the signal processing board works alone, the second control module is configured to encode the test signal according to the test instructions from the host computer, convert the differential signal to a single-ended signal to obtain the first test signal, and detect the first test signal and feed back the obtained third detection result to the host computer; when the signal processing board works in conjunction with the interface test board, the second control module is configured to configure the test parameters of the interface test board according to the test instructions from the host computer and generate a second test signal according to the test instructions, send the second test signal to the interface module of the interface test board in the form of a differential signal, analyze the second detection result returned by the interface test board, and return the analyzed fourth detection result to the host computer.

[0015] Optionally, the signal processing board further includes a second power supply module electrically connected to the second control module and the second communication module. The power supply module is coupled to the VBUS pin of the second differential signal interface. The second power supply module is configured to convert the received second input voltage into a third power supply voltage required by the second control module and the second communication module, respectively.

[0016] Optionally, the second power supply further includes a second programmable power supply, and the second power supply module is also coupled to a power supply. The second programmable power supply is configured to convert the third input voltage of the power supply into a fourth power supply voltage; the fourth power supply voltage is greater than the third power supply voltage.

[0017] Optionally, the performance of the second control module is superior to that of the first control module in the following ways: when the interface test board works independently, the accuracy of the first test signal used by the first control module in conjunction with the host computer to test the device under test is less than or equal to 5ns; when the signal processing board works alone, or when the interface test board works in conjunction with the signal processing board, the accuracy of the first test signal used by the second control module in conjunction with the host computer, or when the first control module and the second control module in conjunction with the host computer to test the device under test, is at the ps level.

[0018] To achieve the above objectives, the present invention also provides a chip testing system, which includes the detachable testing device described in any of the above claims.

[0019] Compared with the prior art, the detachable testing device and chip testing system provided by this utility model have the following advantages:

[0020] The detachable testing device provided by this utility model includes an interface test board and a signal processing board. The interface test board includes a first control module, and the signal processing board includes a second control module. The interface test board and the signal processing board can work independently to test the device under test (DUT), or they can work together to test the DUT, thereby meeting different testing needs. The performance of the second control module of the signal processing board is superior to that of the first control module of the interface test board, which results in higher testing accuracy for the signal processing board and lower cost and smaller size for the interface test board. Furthermore, the interface test board includes an interface module, which allows the low-cost interface test board to have richer interface resources and good high and low temperature resistance. Therefore, by employing this invention, a low-cost interface test board can be used alone to meet testing needs with lower precision requirements. This is not only cost-effective, simple to connect, and easy to use, but also provides abundant interface resources to meet the high and low temperature testing needs of various devices under test (DUTs). Furthermore, a signal processing board with higher testing precision can be used alone to meet testing needs with higher precision requirements but lower temperature requirements, also offering the advantages of simple wiring and ease of use. Even further, by combining the interface test board and the signal processing board, complex testing of various DUTs with high testing precision and high temperature / temperature requirements can be achieved. Moreover, since the D+ and D- pins of the second differential signal interface are directly connected to the D+ and D- pins of the third differential signal interface, the combination of the interface test board and the signal processing board for DUT testing also offers the advantages of simple wiring and ease of use. In summary, this invention not only comprehensively covers testing needs but also offers simple wiring, ease of use, and low cost.

[0021] Since the chip testing system provided by this utility model belongs to the same inventive concept as the detachable testing device provided by this utility model, the chip testing system provided by this utility model has at least all the advantages of the detachable testing device provided by this utility model. For details on the beneficial effects of the chip testing system provided by this utility model, please refer to the above description of the beneficial effects of the detachable testing device provided by this utility model, which will not be repeated here. Attached Figure Description

[0022] Figure 1 A schematic diagram of the block structure of the detachable testing device provided in this embodiment of the utility model;

[0023] Figure 2 A schematic diagram of the interface test board of the detachable test device provided in one embodiment of the present utility model;

[0024] Figure 3A schematic diagram of the signal processing board of a detachable testing device provided in one embodiment of the present invention;

[0025] Figure 4a This is a wiring diagram for when the interface test board is used alone.

[0026] Figure 4b This is a schematic diagram of test signal conversion for one specific example when the interface test board is used alone;

[0027] Figure 5a This is a wiring diagram for when the signal processing board is used alone.

[0028] Figure 5b This is a schematic diagram of test signal conversion for one specific example when the signal processing board is used alone;

[0029] Figure 6a This is a wiring diagram for when the signal processing board and the interface test board are used together.

[0030] Figure 6b This is a schematic diagram of test signal conversion, representing one specific example of the combined use of a signal processing board and an interface test board.

[0031] The accompanying figure is labeled as follows:

[0032] Interface test board-100, first control module-110, first differential signal interface-120, interface module-130, programmable chip-131, first communication module-140, first power module-150, first programmable power supply-151;

[0033] Signal processing board-200, second control module-210, second differential signal interface-220, third differential signal interface-230, second communication module-240, second power supply module-250, second programmable power supply-251;

[0034] Host computer-300, Device under test-400. Detailed Implementation

[0035] The following detailed description, in conjunction with the accompanying drawings, further illustrates the detachable testing device and chip testing system proposed in this utility model. The advantages and features of this utility model will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, intended only to facilitate and clearly illustrate the purpose of the embodiments of this utility model. Please refer to the drawings to make the objectives, features, and advantages of this utility model more apparent and understandable. It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes and to enable those skilled in the art to understand and read them, and are not intended to limit the implementation conditions of this utility model. Any modifications to the structure, changes in proportions, or adjustments to the size, provided they produce the same or similar effects and achieve the same purpose as this utility model, should still fall within the scope of the technical content disclosed in this utility model. Specific design features of this utility model disclosed herein, including, for example, specific dimensions, orientations, positions, and shapes, will be determined in part by the specific application and usage environment. Furthermore, in the embodiments described below, the same reference numerals are sometimes used across different figures to denote the same parts or parts having the same function, and their repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0036] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. The singular forms “a,” “an,” and “the” include plural objects. The term “or” is generally used to mean “and / or,” the term “several” is generally used to mean “at least one,” and the term “at least two” is generally used to mean “two or more.” Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0037] It should be understood that when a component is described as "connected," "connected to," or "coupled" to other components, it may be directly connected to other components, or there may be intermediary components. Conversely, when a component is described as "directly connected," "directly connected to," or "directly coupled" to other components, there are no intermediary components.

[0038] The core idea of ​​this utility model is to provide a detachable testing device and chip testing system. This utility model can not only achieve comprehensive coverage of testing needs, but also has simple wiring, is easy to use and has low cost.

[0039] To achieve the above-mentioned idea, one embodiment of this utility model provides a detachable testing device, which tests the device under test using a first test signal. For example, please refer to... Figure 1 As shown in Figure 6, Figure 1 This is a schematic diagram of the block structure of the detachable testing device provided in this embodiment. Figure 2 This is a schematic diagram of the interface test board of a detachable testing device provided in one embodiment of the present invention. Figure 3 This is a schematic diagram of the signal processing board of a detachable testing device provided in one embodiment of the present invention. Figure 4a This is a wiring diagram for when the interface test board is used alone. Figure 5a This is a wiring diagram for when the signal processing board is used alone. Figure 6a This is a wiring diagram showing the connection when the signal processing board and interface test board are used together. Figure 1 , Figure 2 and Figure 3 It can be seen that the detachable testing device includes an interface testing board 100 and a signal processing board 200. The interface testing board 100 includes a first control module 110, a first differential signal interface 120, and at least one interface module 130. The signal processing board 200 includes a second control module 210, a second differential signal interface 220, and at least one third differential signal interface 230. The D+ & D- pins (i.e., D+ and D- pins, differential pin pairs for transmitting bidirectional data signals) of the second differential signal interface 220 are directly connected to the D+ & D- pins (i.e., D+ and D- pins, differential pin pairs for transmitting bidirectional data signals) of the third differential signal interface 230. The performance of the second control module 210 is better than that of the first control module 110. Furthermore, combined with... Figure 1 , Figure 4a , Figure 5a and Figure 6aIt can be seen that when the interface test board 100 works independently, the first differential signal interface 120 is coupled to the host computer 300, the interface module 130 is coupled to the device under test 400, and the first control module 110 works with the host computer 300 to test the device under test 400; when the signal processing board 200 works independently, the second differential signal interface 220 is coupled to the host computer 300, the third differential signal interface 230 is coupled to the device under test 400, and the second control module 210 works with the host computer 300 to test the device under test 400; when the interface test board 100 and the signal processing board 200 work together, the second differential signal interface 220 ( Figure 6a (Not shown in the diagram, but illustrated with a 16-pin Type C connector) is coupled to the host computer 300. The third differential signal interface 230 is connected to the first differential signal interface 120. The interface module 130 is coupled to the device under test 400. The first control module 110 and the second control module 210 work together with the host computer 300 to test the device under test 400.

[0040] The detachable testing device provided by this utility model includes an interface test board 100 and a signal processing board 200. The interface test board 100 includes a first control module 110, and the signal processing board 200 includes a second control module 210. The interface test board 100 and the signal processing board 200 can work independently to test the device under test 400, or they can work together to test the device under test 400, thereby meeting different testing needs. The performance of the second control module 210 of the signal processing board 200 is better than that of the first control module 110 of the interface test board 100, thereby giving the signal processing board 200 higher testing accuracy and the interface test board 100 lower cost and smaller size. Furthermore, the interface test board 100 includes an interface module 130, thereby giving the low-cost interface test board 100 richer interface resources and good high and low temperature resistance. Therefore, by employing this invention, the low-precision testing requirements can be met by using the low-cost interface test board 100 alone. This not only offers low cost, simple wiring, and ease of use, but also, through its abundant interface resources, can meet the high and low temperature testing needs of various devices under test (DUTs) 400. Furthermore, the higher-precision signal processing board 200 can be used alone to meet the testing needs with higher precision but lower temperature requirements, also offering the advantages of simple wiring and ease of use. Even further, by combining the interface test board 100 and the signal processing board 200, complex testing of various DUTs 400 with high precision and high temperature / temperature requirements can be achieved. Moreover, since the D+ and D- pins of the second differential signal interface 220 are directly connected to the D+ and D- pins of the third differential signal interface 230, the combination of the interface test board 100 and the signal processing board 200 for testing the DUTs 400 also offers the advantages of simple wiring and ease of use. In summary, this invention not only achieves comprehensive coverage of testing needs but also offers simple wiring, ease of use, and low cost.

[0041] Exemplary examples, in some of the exemplary embodiments, include a MIPI (Mobile Industry Processor Interface) signal. Since MIPI signals are widely used in fields such as multi-camera and stacked-screen display control in smartphones and tablets, cameras in automotive electronics, audio and video transmission, wireless connectivity, in-vehicle networks, wearable devices, and the Internet of Things, the detachable test equipment provided by this invention can be applied to various types of devices under test that support MIPI signals, exhibiting good versatility.

[0042] It should be noted that those skilled in the art should understand that the use of a MIPI signal as the first test signal in this document is merely an illustrative example of a preferred embodiment and not a limitation thereof. This invention does not impose any limitations on the specific type of the first test signal; the specific type of the first test signal is related to the signal types that the first control module 110, the second control module 210, and the interface module 130 can process. For example, in some other embodiments, the first test signal may also be, but is not limited to, an HDMI (High Definition Multimedia Interface) signal and a DP (Display Port) signal. For ease of understanding, unless otherwise specified, the first test signal in this document is always exemplified as a MIPI signal.

[0043] It should also be noted that, although Figure 1 and Figure 2 The Sino-Israeli interface test board 100 has one interface module 130 as an example, but this utility model does not limit the number of interface modules 130 of the interface test board 100. The number of interface modules 130 can also be two, three or more. When there is more than one interface module 130, the first control module 110 can use a time-division control method to test the device under test 400 connected to each interface module 130. Multiple interface modules 130 can effectively expand the signal bandwidth. Similarly, although Figure 1 and Figure 3 The signal processing board 200 has one example of a third differential signal interface 230. However, this invention does not limit the number of third differential signal interfaces 230 on the signal processing board 200. The number of third differential signal interfaces 230 can also be two, three or more. When there is more than one third differential signal interface 230, when the signal processing board 200 works alone, the second control module 210 can use time-division control to test the device under test 400 connected to each interface module 130. When the interface test board 100 and the signal processing board 200 work together, the second control module 210 can use time-division control to control the interface test board 100 connected to each interface module 130. More interface test boards 100 can be connected through multiple third differential signal interfaces 230, thereby effectively improving test efficiency.

[0044] It should be understood that this utility model does not impose excessive limitations on the host computer 300. The host computer 300 can be a terminal device, which can be a user equipment (UE), mobile device, user terminal, terminal, handheld device, computing device, or vehicle-mounted device, etc. For example, some terminals include, but are not limited to, mobile phones, tablet computers, laptops, PDAs, and mobile internet devices (MIDs). Furthermore, this utility model does not limit the device under test 400. For example, the device under test 400 can be, but is not limited to, a chip under test and a circuit under test.

[0045] Preferably, in some exemplary embodiments, the performance of the second control module 210 is superior to that of the first control module 110 in the following ways: when the interface test board 100 works independently, the accuracy of the first test signal used by the first control module 110 in conjunction with the host computer 300 to test the device under test 400 is less than or equal to 5 ns (nanoseconds); when the signal processing board 200 works alone, or when the interface test board 100 and the signal processing board 200 work together, the accuracy of the first test signal used by the second control module 210 in conjunction with the host computer 300, or by the first control module 110 and the second control module 210 in conjunction with the host computer 300 to test the device under test 400, is on the order of ps (picoseconds, 1 nanosecond = 1000 picoseconds). The performance of the first control module 110 of the interface test board 100 of the detachable test device provided by this utility model is much lower than that of the second control module 210 of the signal processing board 200. Therefore, the test requirements of most devices under test 400 can be met by using the low-cost interface test board 100 alone. The test requirements of devices under test 400 with high test signal requirements but low test temperature requirements can be met by using the higher precision signal processing board 200 alone. The complex test requirements with high test accuracy and high test temperature requirements can be met by using the interface test board 100 and the signal processing board 200 in combination. This not only makes it easy to use, but also achieves comprehensive coverage of test requirements while having a low cost.

[0046] It should be noted that those skilled in the art should understand that when the interface test board 100 operates independently, the accuracy of the first test signal corresponds to the main frequency of the first control module 110. For example, if the main frequency of the first control module 110 is less than 200MHz, then the accuracy of the first signal is less than or equal to 5ns. It should be understood that 5ns and ps levels are merely illustrative and not limiting. When implementing this invention, the first control module 110 and the second control module 210 should be configured reasonably according to actual needs.

[0047] To facilitate reading and understanding, the following sections will first describe the first differential signal interface 120 of the interface test board 100, the second differential signal interface 220 and the third differential signal interface 230 of the signal processing board 200. Then, the various modules of the interface test board 100, such as the first control module 110 and the interface module 130, as well as the working modes of the interface test board 100, will be explained. Finally, the various modules of the signal processing board 200, such as the second control module 210, as well as the working modes of the signal processing board 200, will be explained.

[0048] For example, please continue to see Figure 2 and Figure 3 ,like Figure 2 and Figure 3 As shown, in some exemplary embodiments, the first differential signal interface 120 and the third differential signal interface 230 are both full-function 24-pin Type-C interfaces, while the second differential signal interface 220 is a 16-pin Type-C interface. Therefore, the design of the first differential signal interface 120 and the third differential signal interface 230 using full-function 24-pin Type-C interfaces, and the second differential signal interface 220 using a 16-pin Type-C interface, fully utilizes the advantage of Type-C's reversible plug-in capability, making the wiring simple and easy to use, while also effectively ensuring stable signal transmission by leveraging Type-C's high-speed transmission and high-current output capabilities.

[0049] It should be noted that this utility model does not impose any restrictions on the specific implementation of the first differential signal interface 120, the second differential signal interface 220, and the third differential signal interface 230. For example, in other embodiments, the first differential signal interface 120, the second differential signal interface 220, and the third differential signal interface 230 may also be other differential interfaces besides the Type-C interface, including but not limited to USB, RS485, and RS232.

[0050] For example, please continue to see Figure 2 ,like Figure 2As shown, in some exemplary embodiments, the interface test board 100 further includes a first communication module 140; the D+ & D- pins (i.e., D+ and D- pins, differential pin pairs for transmitting bidirectional data signals) of the first differential signal interface 120 are correspondingly coupled to the D+ & D- pins (i.e., D+ and D- pins, differential pin pairs for transmitting bidirectional data signals) of the first communication module 140; the TX pin (transmit data pin) and SUB & CC pins (auxiliary channel pin and configuration pin) of the first differential signal interface 120 are coupled to the first control module 110; the RX pin (receive data pin) and TX pin (transmit data pin) of the first differential signal interface 120 are correspondingly coupled to the TX pin (transmit data pin) and RX pin (receive data pin) of the interface module 130; the first control module 110 is coupled to the interface module 130; and the interface module 130 is configured to provide a first test signal to the device under test 400.

[0051] Therefore, through the first communication module 140, the D+ and D- signals can be converted into internal communication bus signals of the interface test board 100, thereby realizing communication between the host computer 300 and the first control module 110, as well as the transmission of differential signals between the signal processing board 200 and the first control module 110.

[0052] It should be noted that, please refer to... Figure 4a , and see Figure 2 In some exemplary embodiments, communication signals are transmitted between the host computer 300, the D+ & D- pins of the first differential signal interface 120, the first communication module 140, and the first control module 110; auxiliary control information and configuration information are transmitted between the first differential signal interface 120 and the first control module 110; control signals are transmitted between the first control module 110 and the interface module 130; differential input and detection results of the first test signal are transmitted between the interface module 130 and the first differential signal interface 120; and the first test signal is transmitted between the interface module 130 and the device under test 400.

[0053] For example, in some exemplary embodiments, the first control module 110 is configured to control the interface module 130 (such as the programmable chip 131 in the interface module 130 below) according to the test commands of the host computer 300 to perform operations such as changing voltage, detecting current, and changing load; the first control module 110 is also used to directly transmit and receive MIPI waveforms using the internal main frequency and input / output interface (IO interface) according to the test commands of the host computer 300, and the first control module 110 is also coupled to the SUB&CC pin of the first differential signal interface 120 to assist communication.

[0054] For example, in some exemplary embodiments, the interface module 130 is configured to convert the received differential signal of the first differential signal interface 120 (e.g., the signal transmitted by the TX1 & TX2 pins) into information parameters in the first test signal (e.g., SCLK & SDATA in the MIPI signal). The voltage and drive capability of the first test signal (e.g., the MIPI signal) can be set by the host computer 300 through test instructions. The interface module 130 is also used to detect the high and low levels of the first test signal (e.g., the SCLK & SDATA of the MIPI signal) according to the judgment criteria specified by the host computer 300 in the test instructions, and transmit the detection result to the differential signal pins (e.g., the TX1 & TX2 pins) of the first differential signal interface 120 in the form of differential signals.

[0055] As previously mentioned, the interface test board 100 can be directly connected to the host computer 300 and operate independently. For example, please refer to [link to example]. Figure 4a ,like Figure 4a As shown, in some exemplary embodiments, when the interface test board 100 operates independently, the first control module 110 is configured to encode a preliminary test signal according to the test instructions from the host computer 300, detect the first test signal, and feed back the first detection result to the host computer 300. The interface module 130 is configured to obtain the first test signal based on the preliminary test signal and send the first test signal (e.g., a MIPI signal) to the device under test 400. Therefore, by using the interface test board 100 to operate independently, it is possible to meet the testing scenarios where high accuracy requirements are not high and high and low temperature resistance is required at a relatively low cost.

[0056] For example, please see Figure 4b , Figure 4b This is a schematic diagram of test signal conversion for one specific example when the interface test board 100 is used alone. Figure 4b Using MIPI signals as an example, from Figure 4b It can be seen that the interface test board 100 transmits and receives MIPI waveforms according to the test commands from the host computer 300, and converts the received differential signals ( Figure 4b The diagram shows the cmd frame from 300 corresponding to D+ and D-, which is converted into the first test signal. Figure 4b (Illustrated with the test frame corresponding to MIPI) After that, the first test signal is output to the device under test 400, and finally the test result is output in the form of a differential signal ( Figure 4b (The diagram shows the cmd frame from 100 corresponding to D+& / D-) and transmits it to the host computer 300.

[0057] As previously mentioned, the interface test board 100 can also be used in combination with the signal processing board 200. For an example, please refer to... Figure 6a ,like Figure 6a As shown, in some exemplary embodiments, when the interface test board 100 and the signal processing board 200 work together, the signal processing board 200 is configured to configure the test parameters of the interface test board 100 according to the test instructions of the host computer 300, and is also configured to generate a second test signal according to the test instructions, and send the second test signal to the interface module 130 of the interface test board 100 in the form of a differential signal. The interface module 130 is configured to convert the differential signal of the second test signal into a single-ended signal to obtain the first test signal, and to detect the first test signal according to the test instructions of the host computer 300 to obtain a second detection result, and is also configured to return the second detection result to the signal processing board 200 in the form of a differential signal. Thus, by using the combined operation mode of the interface test board 100 and the signal processing board 200, complex tests of various devices under test 400 with high test accuracy requirements and high and low temperature requirements can be achieved.

[0058] It should be noted that for more detailed information on the combined testing of the interface test board 100 and the signal processing board 200, please refer to the relevant instructions on the combined use of the signal processing board 200 and the interface test board 100 below. To avoid redundancy, these instructions will not be elaborated here.

[0059] For example, please continue to see Figure 2 ,like Figure 2 As shown, in some exemplary embodiments, the interface test board 100 further includes a first power module 150 electrically connected to the first control module 110, the first communication module 140, and the interface module 130. The first power module 150 is coupled to the VBUS pin of the first differential signal interface 120 and is configured to convert the received first input voltage (provided by the VBUS pin of the first differential signal interface 120) into the first supply voltage required by the first control module 110, the first communication module 140, and the interface module 130, respectively. Thus, the inclusion of the first power module 150 in the interface test board 100 simplifies the wiring of the detachable test device provided by this invention and makes it easier to use.

[0060] For example, please continue to see Figure 2 ,like Figure 2As shown, in some exemplary embodiments, the interface module 130 further includes a programmable controller chip 131, and the first power module 150 further includes a first programmable power supply 151 electrically connected to the programmable controller chip 131. The programmable controller chip 131 is configured to generate the first test signal according to the test instructions from the host computer 300 and to test the device under test 400. The first programmable power supply 151 is configured to convert the first input voltage into a second supply voltage required by the programmable controller chip 131. Thus, the first programmable power supply 151 can effectively meet the high-precision requirements of the programmable controller chip 131 for the supply voltage.

[0061] It should be noted that those skilled in the art should understand that the present invention does not impose excessive limitations on the specific values ​​of the first input voltage, the first supply voltage, and the second supply voltage. For example, the first input voltage can be, but is not limited to, 5V, 9V, 12V, 15V, and 20V, etc., and the first and second supply voltages can be, but are not limited to, 5V, 3.3V, VIO (Voltage Input / Output, used to set the logic levels of the input and output pins of the programmable controller chip 131), and -5V, etc.

[0062] For example, please continue to see Figure 3 ,like Figure 3 As shown, in some exemplary embodiments, the signal processing board 200 further includes a second communication module 240 electrically connected to the second control module 210. The D+ & D- pins (i.e., the D+ and D- pins, differential pin pairs for transmitting bidirectional data signals) of the second differential signal interface 220 are also correspondingly coupled to the D+ & D- pins (i.e., the D+ and D- pins, differential pin pairs for transmitting bidirectional data signals) of the second communication module 240. The SUB & CC pins (auxiliary channel pins and configuration pins), RX pins (receive data pins), and TX pins (transmit data pins) of the second control module 210 are correspondingly coupled to the SUB & CC pins, TX pins, and RX pins of the third differential signal interface 230. The second control module 210 is coupled to the third differential signal interface 230.

[0063] Therefore, through the second communication module 240, the D+ and D- signals can be converted into internal communication bus signals of the signal processing board 200, thereby realizing communication between the host computer 300 and the second control module 210, and further realizing communication between the host computer 300 and the third differential signal interface 230.

[0064] It should be noted that, as Figure 2As shown, in some exemplary embodiments, communication signals are transmitted between the host computer 300, the D+ & D- pins of the second differential signal interface 220, the second communication module 240, and the second control module 210, and the differential input of the first test signal and the detection result are transmitted between the second control module 210 and the third differential signal interface 230.

[0065] Exemplary, in some exemplary embodiments, the second control module 210 is configured to edit a first test signal (e.g., a MIPI signal) with picosecond precision according to test instructions from the host computer 300 and output it as a differential signal through the third differential signal interface 230. The second control module 210 is also used to analyze the second detection result returned by the third differential signal interface 230 with picosecond precision, and to determine whether the waveform on the test signal (e.g., MIPI signal) bus of the interface test board 100 conforms to the relevant test protocol (e.g., the MIPI protocol). Further, as mentioned above, the SUB&CC pins of the third differential signal interface 230 are also connected to the second control module 210 to assist communication with the interface test board 100. In addition, the second control module 210 can also output the waveform of the first test signal (e.g., the MIPI signal) directly as a single-ended signal to the test signal bus (e.g., the MIPI bus) of the signal processing board 200 according to commands from the host computer 300.

[0066] As previously mentioned, the signal processing board 200 can be directly connected to the host computer 300 and operate independently. For example, please refer to [link to example]. Figure 5a ,like Figure 5a As shown, in some exemplary embodiments, when the signal processing board 200 operates independently, the second control module 210 is configured to encode the test signal according to the test instructions from the host computer 300, perform differential signal to single-ended signal processing to obtain the first test signal, and detect the first test signal and feed back the obtained third detection result to the host computer 300. Thus, by using the signal processing board 200, which offers higher testing accuracy, it is possible to meet testing requirements that demand high accuracy but have lower temperature requirements, while also possessing the advantages of simple wiring and ease of use.

[0067] For example, please see Figure 5b , Figure 5b This is a schematic diagram of test signal conversion, representing one specific example when the signal processing board is used alone. Figure 5b Using MIPI signals as an example, from Figure 5b It can be seen that the signal processing board 200 transmits and receives MIPI waveforms according to the test commands from the host computer 300, and processes the received differential signals ( Figure 5b The diagram shows the cmd frame from 300 corresponding to D+ and D-, which is converted into the first test signal. Figure 5b (Illustrated with the test frame corresponding to MIPI) After that, the first test signal is output to the device under test 400, and finally the test result is output in the form of a differential signal ( Figure 5b (The diagram shows the cmd frame from 200 corresponding to D+& / D-) and transmits it to the host computer 300.

[0068] As previously mentioned, the interface test board 100 can also be used in combination with the signal processing board 200. For example, please refer to... Figure 6a ,like Figure 6a As shown, in some exemplary embodiments, when the signal processing board 200 and the interface test board 100 work together, the second control module 210 is configured to configure the test parameters of the interface test board 100 according to the test instructions from the host computer 300, generate a second test signal according to the test instructions, and send the second test signal to the interface module 130 of the interface test board 100 in the form of a differential signal. It also analyzes the second detection result returned by the interface test board 100 and returns the obtained fourth detection result to the host computer 300. Thus, by using the combined operation of the interface test board 100 and the signal processing board 200, complex tests of various devices under test 400 with high testing accuracy requirements and high / low temperature requirements can be achieved.

[0069] Preferably, when the signal processing board 200 and the interface test board 100 are used in combination, the host computer 300 can simultaneously control the signal processing board 200 and the interface test board 100 through the data signal D+ & D- pins; the transmission and reception of the first test signal (e.g., MIPI waveform) are transmitted through the differential data lines TX & RX of the third differential signal interface 230 (e.g., 24-pin Type C) and the first differential signal interface 120 (e.g., 24-pin Type C) to ensure the integrity of the waveform timing information as much as possible; the signal processing board 200 and the interface test board 100 communicate with each other through the SUB & CC data lines of the third differential signal interface 230 (e.g., 24-pin Type C) and the first differential signal interface 120 (e.g., 24-pin Type C).

[0070] For example, please see Figure 6b , Figure 6b This is a schematic diagram of test signal conversion, representing one specific example of a signal processing board and interface test board used in combination. Figure 6b Using MIPI signals as an example, from Figure 6b It can be seen that the signal processing board 200 transmits and receives MIPI waveforms according to the test commands from the host computer 300. The MIPI waveforms are transmitted through the differential data lines of the signal processing board 200. Figure 6bThe signal (Tx from 200, corresponding to the test wave tx diff) is transmitted to the interface test board 100. The interface test board 100 converts the received differential signal into the first test signal. Figure 6b (The test frame corresponding to MIPI is shown in the diagram) and then output to the device under test 400. The test signal waveform is then output in differential form ( Figure 6b The test result (shown as Tx from100 corresponding to check resultrx diff) is transmitted to the signal processing board 200. Finally, the signal processing board 200 converts the test result into a differential signal. Figure 6b (The diagram shows the cmd frame from 200 corresponding to D+& / D-) and transmits it to the host computer 300.

[0071] For example, please continue to see Figure 3 ,like Figure 3 As shown, in some exemplary embodiments, the signal processing board 200 further includes a second power supply module 250 electrically connected to the second control module 210 and the second communication module 240. The power supply module is coupled to the VBUS pin of the second differential signal interface 220. The second power supply module 250 is configured to convert the received second input voltage into a third supply voltage required by the second control module 210 and the second communication module 240, respectively. Therefore, including the second power supply module 250 in the signal processing board 200 simplifies the wiring of the detachable test device provided by this invention and makes it easier to use.

[0072] For example, please continue to see Figure 3 ,like Figure 3 As shown, in some exemplary embodiments, the second power module 250 further includes a second programmable power supply 251, and the second power module 250 is also coupled to a power supply (…). Figure 3 (Not shown in the image), the second programmable power supply 251 is configured to convert the third input voltage (e.g., 12V) of the power supply into a fourth supply voltage; the fourth supply voltage is greater than the third supply voltage. Thus, the power supply provides a foundation for the second programmable power supply 251 to output higher power or higher voltage.

[0073] It should be noted that those skilled in the art will understand that this invention does not impose excessive limitations on the specific values ​​of the second input voltage, the third supply voltage, and the fourth supply voltage. For more detailed information, please refer to the above descriptions regarding the first input voltage, the first supply voltage, and the second supply voltage; these will not be repeated here.

[0074] Based on the same inventive concept, another embodiment of this utility model provides a chip testing system, which includes the detachable testing device described in any of the above embodiments. Since the chip testing system provided by this utility model belongs to the same inventive concept as the detachable testing device provided by this utility model, the chip testing system provided by this utility model possesses at least all the advantages of the detachable testing device provided by this utility model. For detailed information on the beneficial effects of the chip testing system provided by this utility model, please refer to the above description of the beneficial effects of the detachable testing device provided by this utility model, which will not be repeated here.

[0075] In addition to the detachable testing device, the chip testing system may also include a host computer, an oscilloscope, and a multimeter. The host computer can set test commands, and the oscilloscope and multimeter can be used to observe the electrical parameters of the chip under test (e.g., DC current, DC voltage, AC current, AC voltage, resistance, and audio level). For example, the oscilloscope can be used to view the output waveform of the chip under test, and by comparing it with a standard waveform or based on experience, it can be determined whether the chip under test has a problem. For more detailed information about the chip testing system, please refer to the technical adaptations related to chip testing known to those skilled in the art; due to space limitations, they will not be elaborated upon here.

[0076] The detachable testing device provided by this utility model includes an interface test board and a signal processing board. The interface test board includes a first control module, and the signal processing board includes a second control module. The interface test board and the signal processing board can work independently to test the device under test (DUT), or they can work together to test the DUT, thereby meeting different testing needs. The performance of the second control module of the signal processing board is superior to that of the first control module of the interface test board, which results in higher testing accuracy for the signal processing board and lower cost and smaller size for the interface test board. Furthermore, the interface test board includes an interface module, which allows the low-cost interface test board to have richer interface resources and good high and low temperature resistance. Therefore, by employing this invention, a low-cost interface test board can be used alone to meet testing needs with lower precision requirements. This is not only cost-effective, simple to connect, and easy to use, but also provides abundant interface resources to meet the high and low temperature testing needs of various devices under test (DUTs). Furthermore, a signal processing board with higher testing precision can be used alone to meet testing needs with higher precision requirements but lower temperature requirements, also offering the advantages of simple wiring and ease of use. Even further, by combining the interface test board and the signal processing board, complex testing of various DUTs with high testing precision and high temperature / temperature requirements can be achieved. Moreover, since the D+ and D- pins of the second differential signal interface are directly connected to the D+ and D- pins of the third differential signal interface, the combination of the interface test board and the signal processing board for DUT testing also offers the advantages of simple wiring and ease of use. In summary, this invention not only comprehensively covers testing needs but also offers simple wiring, ease of use, and low cost.

[0077] In addition, the functional modules in the various embodiments of this article can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0078] The above description is merely a preferred embodiment of the detachable testing device and chip testing system provided by this utility model, and is not intended to limit the scope of this utility model in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of this utility model. Obviously, those skilled in the art can make various modifications and variations to this utility model without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of this utility model and its equivalents, this utility model also intends to include these modifications and variations.

Claims

1. A dismountable testing device, characterized in that, The detachable test device tests the device under test using a first test signal. The detachable test device includes an interface test board and a signal processing board. The interface test board includes a first control module, a first differential signal interface, and at least one interface module. The signal processing board includes a second control module, a second differential signal interface, and at least one third differential signal interface. The D+ and D- pins of the second differential signal interface are directly connected to the D+ and D- pins of the third differential signal interface. The performance of the second control module is better than that of the first control module. When the interface test board operates independently, the first differential signal interface is coupled to the host computer, the interface module is coupled to the device under test (DUT), and the first control module works with the host computer to test the DUT. When the signal processing board operates independently, the second differential signal interface is coupled to the host computer, the third differential signal interface is coupled to the DUT, and the second control module works with the host computer to test the DUT. When the interface test board and the signal processing board operate together, the second differential signal interface is coupled to the host computer, the third differential signal interface is connected to the first differential signal interface, the interface module is coupled to the DUT, and the first and second control modules work with the host computer to test the DUT.

2. The detachable test device according to claim 1, characterized in that The first test signal includes the MIPI signal.

3. The detachable test device according to claim 1, characterized in that, Both the first differential signal interface and the third differential signal interface are full-function 24-pin Type-C interfaces, while the second differential signal interface is a 16-pin Type-C interface.

4. The detachable test device according to claim 1, characterized in that, The interface test board further includes a first communication module; the D+ and D- pins of the first differential signal interface are correspondingly coupled to the D+ and D- pins of the first communication module, the TX pin and SUB & CC pin of the first differential signal interface are coupled to the first control module, the RX pin and TX pin of the first differential signal interface are correspondingly coupled to the TX pin and RX pin of the interface module, the first control module is coupled to the interface module, and the interface module is configured to provide a first test signal to the device under test.

5. The detachable test device according to claim 4, characterized in that When the interface test board operates independently, the first control module is configured to encode a preliminary test signal according to the test instructions from the host computer, detect the first test signal, and feed back the first detection result to the host computer. The interface module is configured to obtain the first test signal based on the preliminary test signal and send the first test signal to the device under test. When the interface test board and the signal processing board work together, the signal processing board is configured to configure the test parameters of the interface test board according to the test instructions from the host computer, and is also configured to generate a second test signal according to the test instructions, and send the second test signal to the interface module of the interface test board in the form of a differential signal. The interface module is configured to convert the second test signal of the differential signal into a single-ended signal to obtain the first test signal, and detect the first test signal according to the test instructions from the host computer to obtain a second detection result. It is also configured to return the second detection result to the signal processing board in the form of a differential signal.

6. The detachable test device according to claim 4, characterized in that The interface test board further includes a first power supply module electrically connected to the first control module, the first communication module, and the interface module. The first power supply module is coupled to the VBUS pin of the first differential signal interface. The first power supply module is configured to convert the received first input voltage into the first power supply voltage required by the first control module, the first communication module, and the interface module, respectively.

7. The detachable test device according to claim 6, characterized in that The interface module further includes a programmable control chip, and the first power supply module further includes a first programmable power supply electrically connected to the programmable control chip; the programmable control chip is configured to generate the first test signal according to the test instructions of the host computer and to test the device under test; the first programmable power supply is configured to convert the first input voltage into a second power supply voltage required by the programmable control chip.

8. The separable test device of claim 1, wherein, The signal processing board further includes a second communication module electrically connected to the second control module. The D+ and D- pins of the second differential signal interface are also coupled to the D+ and D- pins of the second communication module. The SUB&CC, RX, and TX pins of the second control module are coupled to the SUB&CC, TX, and RX pins of the third differential signal interface. The second control module is coupled to the third differential signal interface.

9. The detachable test device according to claim 8, characterized in that When the signal processing board works independently, the second control module is configured to encode the test signal according to the test instructions from the host computer, convert the differential signal to a single-ended signal to obtain the first test signal, and detect the first test signal and feed back the obtained third detection result to the host computer. When the signal processing board works in conjunction with the interface test board, the second control module is configured to configure the test parameters of the interface test board according to the test instructions from the host computer, generate a second test signal according to the test instructions, send the second test signal to the interface module of the interface test board in the form of a differential signal, analyze the second detection result returned by the interface test board, and return the analyzed fourth detection result to the host computer.

10. The detachable test device according to claim 8, characterized in that The signal processing board also includes a second power supply module electrically connected to the second control module and the second communication module. The power supply module is coupled to the VBUS pin of the second differential signal interface. The second power supply module is configured to convert the received second input voltage into the third power supply voltage required by the second control module and the second communication module, respectively.

11. The detachable test device according to claim 10, characterized in that The second power supply also includes a second programmable power supply, and the second power supply module is also coupled to a power supply. The second programmable power supply is configured to convert the third input voltage of the power supply into a fourth power supply voltage; the fourth power supply voltage is greater than the third power supply voltage.

12. The dismountable testing device according to any one of claims 1 to 11, characterized in that, The performance of the second control module is superior to that of the first control module in the following ways: when the interface test board works independently, the accuracy of the first test signal used by the first control module in conjunction with the host computer to test the device under test is less than or equal to 5ns; when the signal processing board works alone, or when the interface test board works in conjunction with the signal processing board, the accuracy of the first test signal used by the second control module in conjunction with the host computer, or when the first control module and the second control module in conjunction with the host computer to test the device under test, is at the ps level.

13. A chip testing system, characterized by comprising: Includes the detachable testing device as described in any one of claims 1 to 12.

Images