Pseudo-static random access memory and the I / O interface used for it.
By introducing a level conversion module into the PSRAM's I/O interface, the write and read data levels are converted to a lower power supply voltage, which solves the PSRAM's shortcomings in low power consumption and enables low-power interaction with external hosts.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- XC MEMORY CO LTD
- Filing Date
- 2025-07-23
- Publication Date
- 2026-07-03
AI Technical Summary
Existing pseudo-static random access memory (PSRAM) is insufficient in terms of low power consumption and cannot meet the low power requirements of modern portable, embedded devices and Internet of Things (IoT) applications.
The design employs an I/O interface, including a first level conversion module and a second level conversion module, which convert the write data and read data levels to lower power supply voltages respectively, enabling interaction with an external host. The high level of the I/O interface is 0.6V, and the power supply voltage of the core is 1.8V.
Lower power consumption is achieved by reducing the voltage of the I/O interface, thus meeting the low-power requirements of modern devices.
Smart Images
Figure CN224457654U_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of storage, and in particular to a pseudo-static random access memory and an I / O interface therefor. Background Technology
[0002] The demands of modern electronic devices and applications have changed, especially in portable, embedded devices, and the Internet of Things (IoT), where low power consumption has become a critical requirement. As a memory product commonly used in low-power applications, pseudo-static random access memory (PSRAM) also benefits from low power consumption as a key performance requirement.
[0003] Therefore, it is hoped that the power consumption of PSRAM can be reduced. Utility Model Content
[0004] One of the technical problems this disclosure aims to solve is to provide a lower power consumption PSRAM.
[0005] According to a first aspect of this disclosure, an I / O interface for PSRAM is provided, comprising: a plurality of I / O terminals for interacting with a host external to the PSRAM, wherein the high level of each signal is a first power supply voltage; a first level conversion module configured to perform level conversion on at least write data received through the plurality of I / O terminals to obtain level-converted write data, wherein the high level of the write data changes to a second power supply voltage, wherein the second power supply voltage is higher than the first power supply voltage and is the power supply voltage used by the core of the PSRAM; and a second level conversion module configured to perform level conversion on at least read data read from the core of the PSRAM to obtain level-converted read data, wherein the high level of read data changes from the second power supply voltage to the first power supply voltage.
[0006] Optionally, the first level conversion module includes at least N low-to-high level conversion circuits, where N is the data width of the IO interface; the low-to-high level conversion circuit is configured to receive a signal to be converted and output a level-converted signal, and includes: a clamping transistor, as a PMOS transistor, whose drain and gate are coupled together to a first power supply voltage, and whose source is coupled to the node receiving the signal to be converted.
[0007] Optionally, the low-to-high level conversion circuit further includes: an inverter, whose input terminal receives the signal to be converted and whose output terminal outputs the inverted signal of the signal to be converted; a first input transistor, which is an NMOS transistor, whose gate receives the signal to be converted and whose source is grounded; a second input transistor, which is an NMOS transistor, whose gate receives the inverted signal of the signal to be converted and whose source is grounded; a third input transistor, which is a PMOS transistor, whose gate receives the signal to be converted and whose drain is coupled to the drain of the first input transistor; and a fourth input transistor, which is a PMOS transistor. The gate receives the inverted signal of the signal to be converted, and its drain is coupled to the drain of the second input transistor and serves as the output terminal of the low-to-high level conversion circuit to output the level-converted signal. The first cross-coupler and the second cross-coupler are both PMOS transistors. The gate of the first cross-coupler is coupled to the source of the fourth input transistor and the drain of the second cross-coupler. The drain of the first cross-coupler is coupled to the source of the third input transistor and the gate of the second cross-coupler. The source of the first cross-coupler and the source of the second cross-coupler are coupled together and coupled to the second power supply voltage.
[0008] Optionally, the clamping transistor, inverter, first input transistor, and second input transistor are all devices in the first power supply voltage domain, while the third input transistor, fourth input transistor, first cross-coupler and second cross-coupler are all devices in the second power supply voltage domain.
[0009] Optionally, the low-to-high level conversion circuit further includes: a first switch controlled by a low-voltage mode enable signal and coupled between the ground terminal in the inverter and ground; a second switch controlled by the inverted signal of the low-voltage mode enable signal and coupled between the source of the first cross-coupler and the second power supply voltage; and a third switch controlled by the inverted signal of the low-voltage mode enable signal and coupled between the output terminal of the low-to-high level conversion circuit and ground.
[0010] Optionally, the low-voltage mode enable signal is generated based on at least one bit of data in the mode register.
[0011] Optionally, the IO interface can switch between a normal voltage operating mode and a low voltage operating mode; the IO interface further includes: a receive control module configured to control whether the write data undergoes level conversion by a first level conversion module before entering the core of the PSRAM according to the setting of the operating mode of the IO interface; and an output control module configured to control whether the read data undergoes level conversion by a second level conversion module before being output via the plurality of IO terminals according to the setting of the operating mode of the IO interface.
[0012] Optionally, the plurality of I / O terminals are physically connected to corresponding terminals in the host via solder balls.
[0013] Optionally, the first power supply voltage is approximately 0.6V, and the second power supply voltage is approximately 1.8V.
[0014] According to a second aspect of this disclosure, a PSRAM is provided, comprising: an I / O interface according to any of the embodiments in the first aspect above; and a core unit that interacts with a host outside the PSRAM via the I / O interface to read and write data, thereby enabling the host to access the PSRAM.
[0015] Therefore, embodiments of this disclosure can achieve interaction with an external host with a lower interface voltage, thereby achieving lower power consumption. Attached Figure Description
[0016] The above and other objects, features and advantages of this disclosure will become more apparent from the more detailed description of exemplary embodiments thereof taken in conjunction with the accompanying drawings, wherein like reference numerals generally denote like parts.
[0017] Figure 1 An exemplary configuration diagram of a PSRAM and its external host is shown according to some embodiments of the present disclosure.
[0018] Figure 2 An exemplary circuit diagram of a low-to-high level conversion circuit according to some embodiments of the present disclosure is shown.
[0019] Figure 3 An exemplary circuit diagram of a low-to-high level conversion circuit according to some embodiments of the present disclosure is shown.
[0020] Figure 4 An exemplary circuit diagram of a high-to-low level conversion circuit according to some embodiments of the present disclosure is shown.
[0021] Figure 5 An exemplary compositional schematic diagram of a PSRAM according to some embodiments of the present disclosure is shown.
[0022] Figure 6 A schematic diagram of the packaging between a PSRAM die and a host die according to some embodiments of the present disclosure is shown. Detailed Implementation
[0023] Preferred embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
[0024] Currently, standard PSRAM uses two interface voltages: 1.8V or 3.3V.
[0025] In view of this, this disclosure proposes a new solution that enables interaction with an external host using a lower interface voltage, thereby achieving lower power consumption. According to embodiments of this disclosure, the signals transmitted between the PSRAM's I / O interface and the host use a lower high level (first power supply voltage), which is lower than the power supply voltage (second power supply voltage) used inside the PSRAM (its core, including, for example, read / write paths of the memory array). Therefore, the I / O interface also includes a first level conversion module and a second level conversion module to at least convert the transmitted write and read data to appropriate levels, thereby enabling the I / O interface to match the core of the PSRAM. For example, the first power supply voltage can be approximately 0.6V, and the second power supply voltage can be approximately 1.8V.
[0026] Figure 1 An exemplary compositional diagram of a PSRAM and an external host according to some embodiments of the present disclosure is shown.
[0027] like Figure 1 As shown, the PSRAM 100 includes an I / O interface 110 and a core 120. The I / O interface 110 is mainly used to interact with the host 200 outside the PSRAM, so that the host can access the memory array in the core 120 through it. The core 120 mainly includes the memory array and read / write paths to the memory array. The core 120 interacts with the host to read and write data through the I / O interface 110, so as to realize the host's access operation on the PSRAM.
[0028] The I / O interface 110 includes multiple I / O terminals for exchanging signals with the host 200, wherein the high level of each signal is a first power supply voltage VDDQ (e.g., approximately 0.6V). Figure 1 In the example, I / O interface 110 uses the xSPI protocol to interact with host 200, therefore the multiple I / O terminals may include A / DQ, CLK, and CMD terminals. The A / DQ terminal is used to transmit instructions, addresses, read data, and write data. The CLK terminal is used to send a clock signal from host 200 to PSRAM 100. The CMD terminal may include a chip select terminal CS# and a DQS / DM terminal, wherein the DQS / DM terminal is used to output a signal DQS from PSRAM 100 to synchronize the sampling of read data output on the A / DQ terminal during a read operation, and to receive a signal DM to mask the write data received on the A / DQ terminal during a write operation. However, this disclosure is not limited to this; I / O interface 110 may also use, for example, the LPDDR protocol to interact with host 200.
[0029] like Figure 1 As shown, since the core unit 120 operates in the second power supply voltage Vperi domain, the high level of the signal exchanged between the IO interface 110 and the core unit 120 must be the second power supply voltage Vperi (e.g., approximately 1.8V). Since the IO interface 110 must at least exchange write data from the host 200 and read data sent to the host 200 with the core unit 120, the IO interface 110 also includes a first level conversion module 111 and a second level conversion module 112.
[0030] The first level conversion module 111 is configured to transmit at least multiple I / O terminals (e.g., Figure 1 The write data received by the A / DQ terminal is level-converted to obtain the level-converted write data. Its high level becomes the second power supply voltage Vperi, where the second power supply voltage Vperi is higher than the first power supply voltage VDDQ.
[0031] The second level conversion module 112 is configured to perform level conversion on at least the read data read from the core unit 120 to obtain level-converted read data, the high level of which changes from the second power supply voltage Vperi to the first power supply voltage VDDQ.
[0032] When the data width of the IO interface 110 is N, i.e., there are N A / DQ terminals (e.g., N=8), the first level conversion module may include N low-to-high level conversion circuits for simultaneously converting the N bits of write data received from the N A / DQ terminals. In some cases, these N level conversion circuits can also be used to simultaneously convert the N bits of address data and / or instruction data received from the N A / DQ terminals.
[0033] In some cases, the first level conversion module 111 may also include more low-to-high level conversion circuits as needed, for level conversion of some or all of the signals received from the CLK and CMD terminals. In other cases, the signals received from the CLK and CMD terminals are processed in the IO interface 110 and do not need to be transmitted to the core unit 120, so there is no need to set up low-to-high level conversion circuits for them.
[0034] Various suitable circuit structures can be used to implement the aforementioned low-to-high level conversion circuit. The following will combine... Figure 2 and Figure 3 Examples will be described in more detail, but those skilled in the art will understand that this disclosure is not limited thereto.
[0035] Figure 2 An exemplary circuit diagram of a low-to-high level conversion circuit according to some embodiments of the present disclosure is shown.
[0036] like Figure 2 As shown, this level conversion circuit receives the signal to be converted (e.g., a received one-bit write data) VIN and outputs the level-converted signal VOUT. The node receiving VIN can be directly coupled to one of the A / DQ terminals.
[0037] This level shifting circuit adds a clamping transistor M5 at the node receiving VIN. This M5 acts as a PMOS transistor, with its drain and gate coupled together to the first power supply voltage VDDQ, and its source coupled to the node receiving VIN. Thus, ESD (Electrostatic Discharge) protection can be achieved using this clamping transistor, which is particularly advantageous when VDDQ is very low (e.g., about 0.6V).
[0038] The level conversion circuit also includes an inverter 2111, whose input terminal receives the signal to be converted, VIN, and whose output terminal outputs the inverted signal VINB of the signal to be converted.
[0039] exist Figure 2 The diagram illustrates a specific implementation circuit of inverter 2111, which includes PMOS transistor M6 and NMOS transistor M7, wherein the gates of M6 and M7 are coupled together as the input terminal, the drains of M6 and M7 are coupled together as the output terminal, the source of M6 is coupled to VDDQ, and the source of M7 is coupled to ground.
[0040] like Figure 2 As shown, the level conversion circuit also includes four input transistors: the first input transistor M1 and the second input transistor M2 as NMOS transistors, and the third input transistor M3 and the fourth input transistor M4 as PMOS transistors. The gates of M1 and M3 receive VIN, and the gates of M2 and M4 receive VINB.
[0041] The sources of M1 and M2 are both grounded, the drains of M1 and M3 are coupled together, and the drains of M2 and M4 are coupled together and used as the output terminal to output the level-converted signal VOUT.
[0042] By adding a third and fourth input tube, the voltage withstand capability of the first and second input tubes can be enhanced, preventing them from breaking down.
[0043] Figure 2 The level conversion circuit also includes two cross-coupled PMOS transistors, namely the first cross-coupled transistor M8 and the second cross-coupled transistor M9. The gate of M8 is coupled to the source of M4 and the drain of M9, the drain of M8 is coupled to the source of M3 and the gate of M9, and the sources of M8 and M9 are coupled together and coupled to Vperi.
[0044] In some cases, clamping transistor M5, inverter 2111 (e.g.) Figure 2 In the first input transistor M1 and the second input transistor M2, the first input transistor M6 and the second input transistor M2 are all VDDQ domain devices, while the third input transistor M3, the fourth input transistor M4, the first cross-coupler M8 and the second cross-coupler M9 are all Vperi domain devices.
[0045] In this paper, VDDQ domain devices refer to devices operating in the VDDQ domain. This means that the device's design structure and parameters (e.g., channel length, channel doping, oxide thickness) are matched to this power supply voltage domain, ensuring that its electrical characteristics (e.g., threshold voltage, voltage tolerance, drive capability) are suitable for this power supply voltage domain, thus guaranteeing stable and reliable operation of its functional logic under this power supply voltage domain. Similarly, Vperi domain devices refer to devices operating in the Vperi domain.
[0046] In some embodiments, it is also possible to Figure 2 Adding switches to the existing level shifting circuit allows control over its activation state. This is particularly useful when the I / O interface is designed to switch between a normal voltage operating mode (i.e., using the same interface voltage Vperi as the core's power supply, thus eliminating the need for level shifting) and a low-voltage operating mode (i.e., using a lower interface voltage VDDQ as previously mentioned, thus requiring level shifting).
[0047] Figure 3 An exemplary circuit diagram of a low-to-high level conversion circuit with a switch is shown.
[0048] Figure 3 The circuit in Figure 2 Three switches, namely the first to the third switches, are added to the circuit. They are controlled by the low-voltage mode enable signal mode_en or its inverted signal mode_enb, respectively. When mode_en is valid (e.g., it can be set to high level), the level conversion circuit is enabled and performs level conversion operation. When mode_en is invalid, the level conversion circuit stops working.
[0049] Specifically, the first switch, controlled by `mode_en`, is coupled between the ground terminal of the inverter and ground, thereby controlling whether the inverter operates normally. The second switch, controlled by `mode_enb`, is coupled between the source of the first or second cross-coupled connector and the second power supply voltage `Vperi`, thereby controlling whether the second power supply voltage is connected. The third switch, controlled by `mode_enb`, is coupled between the output of the level conversion circuit and ground, thereby controlling whether the output signal is grounded.
[0050] Figure 3The three switches are implemented by an NMOS transistor or a PMOS transistor, but those skilled in the art will understand that this disclosure is not limited to this, and other switch structures (such as transmission gates) can be used to implement the three switches.
[0051] like Figure 3 As shown, the first switch is an NMOS transistor M10, whose gate receives mode_en, and whose drain is coupled to the ground terminal in inverter 3111, i.e., the source of M7, whose source is coupled to ground.
[0052] The second switch is a PMOS transistor M11, whose gate receives mode_enb, whose drain is coupled to the source of M8 and M9, and whose source is coupled to Vperi.
[0053] The third switch is an NMOS transistor M12, whose gate receives mode_enb, whose drain is coupled to the output terminal, i.e., the drain of M2 and M4, and whose source is coupled to ground.
[0054] When mode_en is valid (high level), mode_enb is low. Therefore, both the first and second switches are on, having no effect on the circuit. The third switch is off, preventing the output signal from being grounded, also having no effect on the circuit. The level conversion circuit works normally, performing level conversion. When mode_en is invalid (low level), mode_enb is high. Therefore, both the first and second switches are off, causing the circuit to malfunction. Furthermore, the third switch is on, grounding the output signal and fixing it at a low level, thus stopping the level conversion circuit from working.
[0055] The low-voltage mode enable signal, mode_en, can be generated by the I / O interface in the PSRAM or by any control logic in the core based on the value of specific information. For example, mode_en can be generated based on the value of one or more trim bits(s) inside the PSRAM. Alternatively, mode_en can be generated based on at least one bit of data in the mode register, which can be a preset fixed value or can be changed by instructions sent from the host.
[0056] Similar to the first level conversion module described above, the second level conversion module, when the data width of the IO interface is N, may also include N high-to-low level conversion circuits to simultaneously convert the N-bit read data to be output to N A / DQ terminals.
[0057] Various suitable circuit structures can be used to implement the high-to-low level conversion circuit described above. The following will combine... Figure 4 Examples will be described in more detail, but those skilled in the art will understand that this disclosure is not limited thereto.
[0058] Figure 4 An exemplary circuit diagram of a high-to-low level conversion circuit according to some embodiments of the present disclosure is shown.
[0059] like Figure 4 As shown, the level conversion circuit includes PMOS transistors M41 and M42, and NMOS transistors M43, M44, M45 and M46.
[0060] The sources of M41 and M42, and the drains of M43 and M44 are all coupled to the first power supply voltage VDDQ. The drains of M41 and M42, the sources of M43 and M44, and the drains of M45 and M46 are all coupled together as the output terminal, outputting the level-converted signal VOUT_IO. The sources of M45 and M46 are all coupled to ground.
[0061] The gates of M41, M42, M43, M44, M45 and M46 respectively receive control signals PUO1, PUO2, PUBO1, PUBO2, PDO1 and PDO2, which are control signals generated by logical processing of one bit of read data read from the core unit 120 for controlling the output stage.
[0062] Figure 4 The level conversion circuit is applicable to a wide range of VDDQ.
[0063] When VDDQ is relatively high and not significantly different from the second power supply voltage Vperi, the design can be configured such that when the data to be converted is high, PMOS transistors M41 and / or M42 are turned on, while NMOS transistors M43-M46 are all turned off, thus outputting a high-level signal VOUT_IO, whose level has been converted to VDDQ. At this time, control signals PUO1 and / or PUO2 are low, and control signals PUBO1, PUBO2, PDO1, and PDO2 are all low.
[0064] Furthermore, when VDDQ is significantly lower than Vperi, causing PMOS transistors M41 and M42 to fail to conduct even with a low gate level, the design can be optimized so that NMOS transistors M43 and / or M44 conduct while NMOS transistors M45 and M46 are de-energized when the data to be converted is high, thus outputting a high-level signal VOUT_IO, whose level has been converted to VDDQ. At this time, control signals PUO1 and PUO2 can remain high, turning off PMOS transistors M41 and M42; control signals PUBO1 and / or PUBO2 can be high, turning on NMOS transistors M43 and / or M44; and control signals PDO1 and PDO2 can remain low.
[0065] In both VDDQ scenarios described above, when the data to be converted is low, PMOS transistors M41 and M42, as well as NMOS transistors M43 and M44, are turned off, while NMOS transistors M45 and / or M46 are turned on, thus outputting a low-level signal VOUT_IO. At this time, control signals PUO1 and PUO2 are high, control signals PUBO1 and PUBO2 are low, and control signals PDO1 and / or PDO2 are high.
[0066] When the I / O interface is designed to switch between normal voltage operating mode and low voltage operating mode, the I / O interface can also include a receive control module and an output control module to control whether write and read data need to undergo level conversion according to the current operating mode, for example... Figure 5 shown.
[0067] Figure 5 An exemplary compositional schematic diagram of a PSRAM according to some embodiments of the present disclosure is shown.
[0068] and Figure 1 Similarly, the PSRAM500 includes an I / O interface 510 and a core 520; and Figure 1 The main difference is that the IO interface 510 also includes a receive control module 513 and an output control module 514.
[0069] The receive control module 513 is configured to control whether the written data is level-converted by the first level conversion module 511 before entering the core unit 520, according to the setting of the working mode of the IO interface 510.
[0070] The output control module 514 is configured to control whether read data is level-converted by the second level conversion module 512 before being output via multiple IO terminals (e.g., A / DQ terminals) according to the operating mode settings of the IO interface 510.
[0071] For example, the PSRAM 500 can be configured to operate in a normal scenario or a low-power scenario. Correspondingly, the IO interface 510 can be designed with two sets of data paths. In the normal scenario, the IO interface 510 operates in a normal voltage operating mode. Under the control of the receiving control module 513 and the output control module 514, the read / write data follows the data path that does not pass through the first and second level conversion modules. In the low-power scenario, the IO interface 510 operates in a low-voltage operating mode. Under the control of the receiving control module 513 and the output control module 514, the read / write data follows the data path that passes through the first and second level conversion modules.
[0072] In some embodiments, a bump ball packaging method can be used to achieve the connection between the I / O interface and the host. For example, multiple I / O terminals of the I / O interface are physically connected to corresponding terminals in the host via bump balls. By adopting this packaging method, parasitics and inductance are reduced, power consumption can be further reduced, and the integrity of transmitted signals can be enhanced and signal interference reduced.
[0073] Figure 6 A schematic diagram of the packaging between a PSRAM die and a host die according to some embodiments of the present disclosure is shown.
[0074] like Figure 6 As shown, the PSRAM die 610 is flip-chip soldered onto the host die 620 via multiple solder balls 630. Thus, the solder balls 630 directly and physically connect to, for example... Figure 1 The PSRAM shown has multiple IO terminals (such as A / DQ, CLK, CMD, etc.) of its IO interface and corresponding terminals on the host.
[0075] In some examples, the solder ball 630 can be implemented using micro bumps.
[0076] In the traditional case of using bonding wires to solder PSRAM and the host, the load capacitance is generally around 3pF. However, in the embodiment of this disclosure, when the PSRAM is directly interconnected with the host in the form of solder balls, the resulting capacitance is generally around 500fF. The parasitic inductance is smaller, the signal interference is reduced, and the power consumption is further reduced.
[0077] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.
Claims
1. An IO interface for pseudo-static random access memory, characterized in that, include: Multiple I / O terminals are used to interact with external host signals of the pseudo-static random access memory, wherein the high level of the signals is the first power supply voltage; The first level conversion module is configured to perform level conversion on at least the write data received through the plurality of IO terminals to obtain level-converted write data, wherein the high level of the write data is changed to a second power supply voltage, wherein the second power supply voltage is higher than the first power supply voltage and is the power supply voltage used by the core of the pseudo-static random access memory. as well as The second level conversion module is configured to perform level conversion on at least the read data read from the core of the pseudo-static random access memory to obtain level-converted read data, wherein the high level of the read data changes from the second power supply voltage to the first power supply voltage.
2. The IO interface of claim 1, wherein, The first level conversion module includes at least N low-to-high level conversion circuits, where N is the data width of the IO interface; The low-to-high level conversion circuit is configured to receive a signal to be converted and output a level-converted signal, and includes: The clamping transistor, as a PMOS transistor, has its drain and gate coupled together to the first power supply voltage, and its source coupled to the node receiving the signal to be converted.
3. The IO interface of claim 2, wherein, The low-to-high level conversion circuit also includes: An inverter that receives the signal to be converted at its input and outputs the inverted signal of the signal to be converted at its output. The first input transistor, as an NMOS transistor, receives the signal to be converted at its gate and its source is grounded; The second input transistor, as an NMOS transistor, receives the inverted signal of the signal to be converted at its gate, and its source is grounded. The third input transistor, as a PMOS transistor, receives the signal to be converted at its gate and its drain is coupled to the drain of the first input transistor. The fourth input transistor, as a PMOS transistor, receives the inverted signal of the signal to be converted at its gate, and its drain is coupled to the drain of the second input transistor and serves as the output terminal of the low-to-high level conversion circuit to output the level-converted signal. The first cross-coupler and the second cross-coupler are both PMOS transistors. The gate of the first cross-coupler is coupled to the source of the fourth input transistor and the drain of the second cross-coupler. The drain of the first cross-coupler is coupled to the source of the third input transistor and the gate of the second cross-coupler. The source of the first cross-coupler and the source of the second cross-coupler are coupled together and coupled to the second power supply voltage.
4. The IO interface of claim 3, wherein, The clamping transistor, the inverter, the first input transistor, and the second input transistor are all devices in the first power supply voltage domain, while the third input transistor, the fourth input transistor, the first cross-coupler, and the second cross-coupler are all devices in the second power supply voltage domain.
5. The IO interface of claim 3, wherein, The low-to-high level conversion circuit also includes: The first switch, controlled by a low-voltage mode enable signal, is coupled between the ground terminal in the inverter and ground. The second switch, controlled by the inverted signal of the low-voltage mode enable signal, is coupled between the source of the first cross-coupled connector and the second power supply voltage; and The third switch, controlled by the inverted signal of the low-voltage mode enable signal, is coupled between the output of the low-to-high level conversion circuit and ground.
6. The IO interface of claim 5, wherein, The low-voltage mode enable signal is generated based on at least one bit of data in the mode register.
7. The IO interface of claim 1, wherein, The I / O interface can switch between normal voltage operating mode and low voltage operating mode; The I / O interface also includes: The receive control module is configured to control whether the write data undergoes level conversion by the first level conversion module before entering the core of the pseudo-static random access memory, based on the operating mode setting of the I / O interface; and The output control module is configured to control whether the read data is level-converted by the second level conversion module before being output via the plurality of IO terminals, based on the setting of the operating mode of the IO interface.
8. The IO interface of claim 1, wherein, The plurality of I / O terminals are physically connected to corresponding terminals in the host via solder balls.
9. The I / O interface according to claim 1, characterized in that, The first power supply voltage is approximately 0.6V, and the second power supply voltage is approximately 1.8V.
10. A pseudo-static random access memory, characterized by include: The I / O interface according to any one of claims 1-9; as well as The core unit interacts with the host outside the pseudo-static random access memory via the IO interface to read and write data, thereby enabling the host to access the pseudo-static random access memory.