Level conversion circuit, chip and electronic device

Abstract

The present disclosure provides a level conversion circuit, a chip and an electronic device. The level conversion circuit comprises: a boosting unit configured as a current mirror structure, comprising a first input end, a second input end and a first output end, the first input end is connected to a first power supply, the second input end is connected to a second power supply, to generate a mirror current at the first output end under the action of the first power supply; a third transistor comprising a third gate, a third source and a third drain, the third gate is adapted to receive a high level signal of the first power supply, the third source is connected to the first output end; the third drain is connected to the first power supply; an output unit comprising a third input end and a second output end, the third input end is connected to the second power supply, the output unit is adapted to receive and respond to a first signal, the second output end outputs a second signal of the same level as the first signal of the second power supply; wherein the voltage provided by the first power supply is lower than the voltage provided by the second power supply.

Description

Technical Field

[0001] This disclosure relates to the field of mixed-signal integrated circuit design technology, and in particular to a level conversion circuit, chip, and electronic device. Background Technology

[0002] As modern integrated circuit technology shrinks, gate oxide layers become thinner, presenting new challenges, such as gate oxide reliability and hot carrier degradation. To address these issues, the internal supply voltage (VDDC) must be reduced accordingly. While this lower supply voltage improves system performance and reduces power consumption, it introduces a new problem: voltage mismatch between the chip's internal and external circuits. Internal circuits typically use thin gate oxide devices and low supply voltages (e.g., 0.3V), while external circuitry usually operates at higher voltages (the mainstream operating voltage is 1.8V). Therefore, level shifting circuits are needed in the chip's general purpose input / output (GPIO) units to convert the low-voltage domain to the high-voltage domain.

[0003] Traditional level conversion circuits have a narrow voltage conversion range (1V~1.8V), while existing research on circuits that achieve a wide conversion range cannot guarantee a fast operating frequency and low power consumption. Summary of the Invention

[0004] To address at least one of the technical problems in the prior art, this disclosure provides a level conversion circuit, a chip, and an electronic device. By utilizing a third transistor as a transmission transistor, the voltage conversion rate is improved, thereby enabling operation at higher frequencies even under a wide switching voltage range.

[0005] One aspect of this disclosure provides a level conversion circuit, including: a boost unit, a third transistor, and an output unit. The boost unit is configured as a current mirror structure, including a first input terminal, a second input terminal, and a first output terminal. The first input terminal is connected to a first power supply, and the second input terminal is connected to a second power supply, so as to generate a mirror current at the first output terminal under the action of the first power supply. The third transistor includes a third gate, a third source, and a third drain. The third gate is adapted to receive a high-level signal from the first power supply, and the third source is connected to the first output terminal. The third drain is connected to the first power supply, so as to change the operating state of the third transistor under the switching of the first power supply, thereby controlling the first signal output by the first output terminal. The output unit includes a third input terminal and a second output terminal. The third input terminal is connected to the second power supply, and the output unit is adapted to receive and respond to the first signal. The second output terminal outputs a signal from the second power supply with the same level as the first power supply. The voltage provided by the first power supply is higher than the voltage provided by the second power supply.

[0006] According to embodiments of this disclosure, the boost unit includes: a second transistor, a fourth transistor, and a fifth transistor. The second transistor includes a second gate, a second source, and a second drain; the second gate is connected to the first input terminal, and the second source is connected to a reference ground. The fourth transistor includes a fourth gate, a fourth source, and a fourth drain; the fourth source is connected to the second input terminal, the fourth drain is connected to the second drain, and the fourth gate is connected to the fourth drain. The fifth transistor includes a fifth gate, a fifth source, and a fifth drain; the fifth source is connected to the second input terminal, the fifth gate is connected to the fourth gate, and the fifth drain is connected to the first output terminal.

[0007] According to an embodiment of this disclosure, the output unit includes: a first inverting unit and a second inverting unit. The first inverting unit is adapted to receive and output a third signal in response to the first signal, the third signal being a signal inverted from the first power supply input to the first input terminal; the second inverting unit is adapted to receive and output the second signal in response to the third signal.

[0008] According to an embodiment of this disclosure, the second drain is connected to a reference ground via a first transistor. The first transistor includes a first gate, a first source, and a first drain. The first drain is connected to the second drain, and the first source is connected to the reference ground. The first gate receives and responds to the third signal, and when the third signal is high, it cuts off the quiescent current generated by the boost unit.

[0009] According to embodiments of this disclosure, the first inverting unit includes a sixth transistor and an eighth transistor. The sixth transistor includes a sixth gate, a sixth source, and a sixth drain. The sixth gate is connected to the first output terminal, and the sixth source is connected to a reference ground. The eighth transistor includes an eighth gate, an eighth source, and an eighth drain. The eighth gate is connected to the first output terminal, the eighth source is connected to the second power supply, and the eighth drain is connected to the sixth drain, outputting the third signal. The first gate is connected to the eighth source.

[0010] According to an embodiment of this disclosure, the eighth source is connected to the second power supply via a seventh transistor. The seventh transistor includes a seventh gate, a seventh source, and a seventh drain. The seventh drain is connected to the second power supply, and the seventh gate and the seventh drain are connected to the eighth source.

[0011] According to an embodiment of this disclosure, the output unit further includes a ninth transistor. The ninth transistor includes a ninth gate, a ninth source, and a ninth drain. The ninth gate receives and responds to the second signal to control the operating state of the ninth transistor. The ninth source is connected to the second power supply, and the ninth drain is connected to the eighth drain.

[0012] According to an embodiment of this disclosure, when the first power supply is at a high level, the third transistor is turned off, the boost unit generates a mirror current at the first output terminal, and the output unit receives and responds to the mirror current by outputting a high-level signal of the second power supply.

[0013] In another aspect of this disclosure, a chip is provided that includes any of the level conversion circuits described above.

[0014] In another aspect of this disclosure, an electronic device is provided, the electronic device including the chip described above.

[0015] According to embodiments of this disclosure, a current mirror structure is adopted in the design of the boost unit, using a third transistor as a transmission transistor. The gate of the third transistor is connected to a high-level signal of the first power supply (low voltage domain). When the first drain receives a high-level signal of the first power supply, the third transistor is turned off, so that the first output terminal outputs the mirror current signal generated by the boost unit under the action of the second power supply (high voltage domain). When the first drain receives a low-level signal of the first power supply, the third transistor is turned on, so that the first output terminal outputs a low-level signal, replacing the inverter unit in the conventional structure, improving the voltage conversion rate, and thus enabling it to operate at a higher frequency (5MHz-10MHz) under a wide conversion voltage condition. Attached Figure Description

[0016] Figure 1 An overall block diagram of a level conversion circuit according to an embodiment of the present disclosure is schematically shown; and

[0017] Figure 2 A circuit diagram of a level conversion circuit according to an embodiment of the present disclosure is shown schematically.

[0018] Explanation of reference numerals in the attached figures:

[0019] 1-Boost unit;

[0020] 2-Output Unit;

[0021] 21 - First inverting unit;

[0022] 22 - Second inverting unit;

[0023] M1 - First transistor;

[0024] M2 - Second transistor;

[0025] M3 - Third transistor;

[0026] M4 - Fourth transistor;

[0027] M5 - the fifth transistor;

[0028] M6 - the sixth transistor;

[0029] M7 - the seventh transistor;

[0030] M8 - the eighth transistor; and

[0031] M9 - Ninth transistor. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings. However, this disclosure can be implemented in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art. In the accompanying drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated, and the same reference numerals denote the same elements throughout.

[0033] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0034] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0035] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0036] To facilitate understanding of the technical solutions disclosed herein by those skilled in the art, the following technical terms are explained.

[0037] When using expressions such as "at least one of A, B, and C," the expression should generally be interpreted in accordance with the meaning commonly understood by a person skilled in the art (e.g., "a system having at least one of A, B, and C" should include, but is not limited to, systems having A alone, having B alone, having C alone, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.). When using expressions such as "at least one of A, B, or C," the expression should generally be interpreted in accordance with the meaning commonly understood by a person skilled in the art (e.g., "a system having at least one of A, B, or C" should include, but is not limited to, systems having A alone, having B alone, having C alone, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.).

[0038] Figure 1 An overall block diagram of a level conversion circuit according to an embodiment of the present disclosure is schematically shown. Figure 2 A circuit diagram of a level conversion circuit according to an embodiment of the present disclosure is shown schematically.

[0039] One aspect of this disclosure provides a level conversion circuit, such as... Figure 1 and Figure 2 As shown, the level conversion circuit includes: boost unit 1, output unit 2 and third transistor M3.

[0040] Wherein, VDDC represents the high-level signal of the voltage provided by the first power supply (low voltage domain), and VSSC represents the reference ground (0V). VDDIO represents the high-level signal of the voltage provided by the second power supply (high voltage domain), and VSSIO represents the reference ground (0V). The IN terminal represents the first input terminal, which is the input terminal of the level conversion circuit. The first input terminal receives the voltage signal provided by the first power supply. The OUT terminal is the output terminal of the level conversion circuit, which is used to output the second signal.

[0041] The boost unit 1 is configured as a current mirror structure, including a first input terminal, a second input terminal and a first output terminal. The first input terminal is connected to a first power supply and the second input terminal is connected to a second power supply, so that a mirror current is generated at the first output terminal under the action of the first power supply.

[0042] The third transistor M3 includes a third gate, a third source, and a third drain. The third gate is suitable for receiving a high-level signal from the first power supply. The third source is connected to the first output terminal. The third drain is connected to the first power supply so that the operating state of the third transistor M3 can be changed under the switching of the first power supply, thereby controlling the first signal output from the first output terminal.

[0043] The output unit 2 includes a third input terminal and a second output terminal. The third input terminal is connected to a second power supply. The output unit 2 is adapted to receive and respond to a first signal. The second output terminal outputs a second signal from the second power supply with the same level as the first power supply. The voltage provided by the first power supply is higher than the voltage provided by the second power supply.

[0044] According to embodiments of this disclosure, the level conversion circuit provided by this disclosure can amplify the signal from a first power source (low voltage domain) to a second power source (high voltage domain) for transmission.

[0045] According to the embodiments of this disclosure, a current mirror structure is adopted in the design of the boost unit 1, and the third transistor M3 is used as the transmission transistor. The gate of the third transistor M3 is connected to the high-level signal of the first power supply (low voltage domain). When the first drain receives the high-level signal of the first power supply, the third transistor M3 is turned off, so that the first output terminal outputs the mirror current signal generated by the boost unit 1 under the action of the second power supply (high voltage domain). When the first drain receives the low-level signal of the first power supply, the third transistor M3 is turned on, so that the first output terminal outputs the low-level signal, replacing the inverter unit in the conventional structure, improving the voltage conversion rate, so that it can operate at a higher frequency (5MHz-10MHz) under a wide conversion voltage condition.

[0046] According to embodiments of this disclosure, the high-level voltage range of the voltage provided by the first power supply is 0.25V to 0.35V, and the high-level voltage range of the voltage provided by the second power supply is 1.2V to 1.5V.

[0047] According to embodiments of this disclosure, the voltage input range of the first input terminal is 0 to VDDC. The OUT port is the second output terminal, serving as a signal output port, and its voltage output range is 0 to VDDIO.

[0048] In one illustrative embodiment, the voltage provided by the first power supply is 0.27V, so the signal logic 0 in the low voltage domain is 0V and the logic 1 is 0.27V (VDDC). The voltage provided by the second power supply is 1.45V, so the signal logic 0 in the high voltage domain is 0V and the logic 1 is 1.45V (VDDIO).

[0049] In one illustrative embodiment, the level conversion circuit provided in this disclosure can achieve a level conversion of 0.3V to 1.4V.

[0050] In one illustrative embodiment, the level conversion circuit provided in this disclosure can achieve a level conversion of 0.25V to 1.2V.

[0051] In one illustrative embodiment, the level conversion circuit provided in this disclosure can achieve a level conversion of 0.25V to 1.5V.

[0052] In one illustrative embodiment, the level conversion circuit provided in this disclosure can achieve a level conversion of 0.35V to 1.3V.

[0053] According to an embodiment of this disclosure, the third transistor M3 is an NMOS transistor.

[0054] According to an embodiment of this disclosure, the second input terminal is connected to a high-level signal of a second power supply.

[0055] According to embodiments of this disclosure, the source and drain of the transistor used in this disclosure are essentially symmetrical, and the source and drain are separated for ease of description.

[0056] According to an embodiment of this disclosure, when the first power supply is at a high level, the third transistor M3 is turned off, the boost unit 1 generates a mirror current at the first output terminal, and the output unit 2 receives and responds to the mirror current to output a high-level signal of the second power supply.

[0057] According to an embodiment of this disclosure, since the gate of the third transistor M3 is connected to a high-level signal of the first power supply, when the third drain receives a high-level signal of the first power supply, the third transistor M3 is turned off, and the first output terminal outputs the mirror current generated by the boost unit 1.

[0058] According to an embodiment of this disclosure, when the first power supply is at a low level, the third transistor M3 is turned on, the first output terminal outputs a low-level signal, and the output unit 2 receives and responds to the low-level signal output by the first output terminal by outputting a low-level signal of the second power supply.

[0059] According to embodiments of this disclosure, such as Figure 2 As shown, the boost unit 1 includes: a second transistor M2, a fourth transistor M4, and a fifth transistor M5. The second transistor M2 includes a second gate, a second source, and a second drain. The second gate is connected to the first input terminal, and the second source is connected to reference ground. The fourth transistor M4 includes a fourth gate, a fourth source, and a fourth drain. The fourth source is connected to the second input terminal, the fourth drain is connected to the second drain, and the fourth gate is connected to the fourth drain. The fifth transistor M5 includes a fifth gate, a fifth source, and a fifth drain. The fifth source is connected to the first input terminal, the fifth gate is connected to the fourth gate, and the fifth drain is connected to the first output terminal.

[0060] According to an embodiment of this disclosure, the second transistor M2 is an NMOS transistor.

[0061] According to embodiments of this disclosure, the fourth transistor M4 and the fifth transistor M5 are PMOS transistors.

[0062] According to embodiments of this disclosure, such as Figure 2As shown, the output unit 2 includes a first inverting unit 21 and a second inverting unit 22. The first inverting unit 21 is adapted to receive and respond to a first signal to output a third signal, wherein the third signal is a signal that is inverted from the first power supply input to the first input terminal; the second inverting unit 22 is adapted to receive and respond to the third signal to output the second signal.

[0063] According to an embodiment of this disclosure, the first inverting unit 21 includes a power input terminal, a fourth input terminal, and a third output terminal. The power input terminal of the first inverting unit 21 is the third input terminal of the output unit 2 and is connected to a second power supply. The fourth input terminal receives and responds to a first signal and outputs a third signal at the third output terminal.

[0064] According to an embodiment of this disclosure, the second inverting unit 22 includes a power input terminal, a fifth input terminal, and a second output terminal. The power input terminal of the second inverting unit 22 is connected to a second power supply, the fifth input terminal receives and responds to a third signal, and outputs a second signal at the second output terminal.

[0065] According to embodiments of this disclosure, such as Figure 2 As shown, the second drain is connected to the reference ground through the first transistor M1. The first transistor M1 includes a first gate, a first source, and a first drain. The first drain is connected to the second drain, the first source is connected to the reference ground, and the first gate receives and responds to a third signal. When the third signal is high, it cuts off the static current generated by the boost unit 1.

[0066] According to an embodiment of this disclosure, the first transistor M1 is an NMOS transistor.

[0067] According to embodiments of this disclosure, the first transistor M1 serves as a feedback transistor, which can reduce the leakage current of the boost unit 1 and lower static power consumption.

[0068] According to embodiments of this disclosure, such as Figure 2 As shown, the first inverting unit 21 includes a sixth transistor M6 and an eighth transistor M8. The sixth transistor M6 includes a sixth gate, a sixth source, and a sixth drain. The sixth gate is connected to the first output terminal, and the sixth source is connected to reference ground. The eighth transistor M8 includes an eighth gate, an eighth source, and an eighth drain. The eighth gate is connected to the first output terminal, the eighth source is connected to the second power supply, and the eighth drain is connected to the sixth drain, outputting a third signal. The first gate is connected to the eighth source.

[0069] According to an embodiment of this disclosure, the sixth transistor M6 is an NMOS transistor.

[0070] According to an embodiment of this disclosure, the eighth transistor M8 is a PMOS transistor.

[0071] According to embodiments of this disclosure, such as Figure 2 As shown, the eighth source is connected to the second power supply through the seventh transistor M7. The seventh transistor M7 includes a seventh gate, a seventh source, and a seventh drain. The seventh drain is connected to the second power supply, and the seventh gate and the seventh drain are connected to the eighth source.

[0072] According to embodiments of this disclosure, the seventh transistor M7 is a PMOS transistor used to reduce quiescent current and correct signal waveform.

[0073] According to embodiments of this disclosure, by adding a seventh transistor M7 and using a diode design for the seventh transistor M7, the signal swing of the boost unit 1 is reduced, thereby reducing the duration of leakage current during level transition and reducing power consumption.

[0074] According to embodiments of this disclosure, such as Figure 2 As shown, output unit 2 further includes a ninth transistor M9. The ninth transistor M9 includes a ninth gate, a ninth source, and a ninth drain. The ninth gate receives and responds to the second signal to control the operating state of the ninth transistor M9. The ninth source is connected to the second power supply, and the ninth drain is connected to the eighth drain.

[0075] According to an embodiment of this disclosure, the ninth transistor M9 is a PMOS transistor.

[0076] According to an embodiment of this disclosure, the ninth transistor M9 and the second inverting unit 22 constitute a waveform correction module. By setting the ninth transistor M9, the voltage pull-up speed is increased, and the smooth waveform output by the boost unit 1 is transformed into a steep rising and falling edge, thereby reducing the rise and fall time.

[0077] According to embodiments of this disclosure, such as Figure 2 As shown, when the signal at the first input terminal (IN port) transitions from logic 0 to logic 1 (i.e., 0V→VDDC), since the second output terminal (OUT port) remains at logic 0 and has not changed, the third output terminal (N3 node) does not transition from logic 1 to logic 0 for a short period of time. That is, the gate of the first transistor M1 is not at a high level, and the first transistor M1 remains in the on state. At this time, due to the change in the input signal at the first input terminal (IN port), the second transistor M2 turns on, and the voltage between the third gate and the third source of the third transistor M3 decreases, causing the third transistor M3 to turn off.

[0078] The fourth gate voltage of the fourth transistor M4 decreases due to the opening of the paths of the first transistor M1 and the second transistor M2. Since the fourth gate of the fourth transistor M4 is connected to the fourth drain, the fourth transistor M4 is in a saturated conducting state, and the branch formed by the fourth transistor M4, the second transistor M2, and the first transistor M1 is also conducting. Because the voltage between the fourth gate and the fourth source of the fourth transistor M4 is the same as the voltage between the fifth gate and the fifth source of the fifth transistor M5, a mirror current is generated at the first output terminal (node ​​N1) through the fifth transistor M5. The mirror current charges the N1 node, and the signal is then transmitted to the first inverting unit 21.

[0079] The voltage at node N1 turns on the sixth transistor M6, causing the voltage at node N3 to decrease. This results in a decrease in the first gate voltage of the first transistor M1, turning it off. The turned-off first transistor M1 cuts off the high quiescent current flowing through the second transistor M2 and the fourth transistor M4, resulting in a smaller voltage swing at point N1. Furthermore, because the seventh transistor M7 is a diode, the voltage swing at node N2 is also small, and since the voltage swings at node N2 and N1 are the same, the eighth transistor M8 can be quickly turned off. The leakage current flowing through the eighth transistor M8 is small, reducing power consumption.

[0080] Finally, the N3 signal passes through the waveform correction module composed of the second inverting unit 22 and the ninth transistor M9. At this time, the OUT port outputs logic 1 (VDDIO), completing the conversion of the output level from logic 0 to logic 1.

[0081] When the IN port signal transitions from logic 1 to logic 0 (i.e., VDDC→0V), the second transistor M2 is turned off to disable the mirror current, and the third transistor M3 is turned on. Node N1 discharges rapidly through the third transistor M3, and the first signal is transmitted to the first inverting unit 21. Node N3 is charged due to the sixth transistor M6 being turned off and the eighth transistor M8 being turned on. Simultaneously, due to the ninth transistor M9 being turned on, node N3 is rapidly charged to VDDIO, significantly reducing the fallback delay. Finally, the N3 signal passes through the waveform correction module, causing the OUT port output to be logic 0, completing the output level transition from logic 1 to logic 0 (VDDIO→0V).

[0082] It should be noted that when node N3 is high, the second output terminal (OUT port) is low. Since the ninth transistor M9 is a PMOS transistor and its output is connected to the ninth gate, the ninth transistor M9 is turned on. Conversely, when N3 is low, the second output terminal (OUT port) is high, and the ninth transistor M9 is turned off.

[0083] In another aspect of this disclosure, a chip is provided that includes any of the level conversion circuits described above.

[0084] In another aspect of this disclosure, an electronic device is provided, which includes the chip described above.

[0085] The embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. It should be noted that implementations not illustrated or described in the drawings or the main text of the specification are forms known to those skilled in the art and are not described in detail. Furthermore, the definitions of the various elements and methods described above are not limited to the specific structures, shapes, or methods mentioned in the embodiments, and those skilled in the art can easily modify or substitute them.

[0086] Based on the above description, those skilled in the art should have a clear understanding of the level conversion circuit, chip, and electronic equipment provided in this disclosure.

[0087] In summary, this disclosure provides a level conversion circuit, chip, and electronic device that can realize the conversion from a low voltage domain to a high voltage domain. By using a third transistor M3, the circuit area is effectively reduced. By using a ninth transistor M9, the fallback delay of the second output port (OUT port) is reduced, thereby improving the conversion rate of the level conversion circuit. As a result, the level conversion circuit provided by this disclosure can operate at a higher frequency under a wide conversion voltage condition.

[0088] It should also be noted that the directional terms mentioned in the embodiments, such as "up," "down," "front," "back," "left," and "right," are only for reference to the directions in the accompanying drawings and are not intended to limit the scope of protection of this disclosure. Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or constructions will be omitted where they may cause confusion in understanding this disclosure, and the shapes and dimensions of the components in the drawings do not reflect actual size and proportion, but are only schematic representations of the embodiments of this disclosure.

[0089] Unless otherwise stated, the numerical parameters in this specification and the appended claims are approximate values ​​and can be varied according to desired characteristics derived from the content of this disclosure. Specifically, all figures used in the specification and claims to indicate composition, reaction conditions, etc., should be understood to be modified by the term "about" in all cases. Generally, this means that a specific amount may vary by ±10% in some embodiments, ±5% in some embodiments, ±1% in some embodiments, and ±0.5% in some embodiments.

[0090] The use of ordinal numbers such as "first," "second," "third," etc., in the specification and claims to modify the corresponding elements does not imply that the element has any ordinal number, nor does it represent the order of one element with another element, or the order of manufacturing methods. The use of these ordinal numbers is only to enable a named element to be clearly distinguished from another element with the same name.

[0091] Furthermore, unless specifically described or required to occur in a specific order, the order of the above steps is not limited to those listed above and can be varied or rearranged according to the desired design. Moreover, the above embodiments can be used in combination with each other or with other embodiments based on design and reliability considerations; that is, technical features from different embodiments can be freely combined to form more embodiments.

[0092] The specific embodiments described above further illustrate the purpose, technical solutions, and beneficial effects of this disclosure. It should be understood that the above descriptions are merely specific embodiments of this disclosure and are not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A level conversion circuit, characterized in that, include: The boost unit is configured as a current mirror structure, including a first input terminal, a second input terminal and a first output terminal. The first input terminal is connected to a first power supply and the second input terminal is connected to a second power supply, so that a mirror current is generated at the first output terminal under the action of the first power supply. The third transistor includes a third gate, a third source, and a third drain. The third gate is adapted to receive a high-level signal from the first power supply. The third source is connected to the first output terminal. The third drain is connected to the first power supply to change the operating state of the third transistor under the switching of the first power supply, thereby controlling the first signal output from the first output terminal. The output unit includes a third input terminal and a second output terminal. The third input terminal is connected to the second power supply. The output unit is adapted to receive and respond to the first signal. The second output terminal outputs a second signal of the second power supply with the same level as the first power supply. The voltage provided by the first power source is lower than the voltage provided by the second power source.

2. The level conversion circuit according to claim 1, characterized in that, The boost unit includes: The second transistor includes a second gate, a second source, and a second drain. The second gate is connected to the first input terminal, and the second source is connected to a reference ground. The fourth transistor includes a fourth gate, a fourth source, and a fourth drain, wherein the fourth source is connected to the second input terminal, the fourth drain is connected to the second drain, and the fourth gate is connected to the fourth drain. The fifth transistor includes a fifth gate, a fifth source, and a fifth drain. The fifth source is connected to the second input terminal, the fifth gate is connected to the fourth gate, and the fifth drain is connected to the first output terminal.

3. The level conversion circuit according to claim 2, characterized in that, The output unit includes: The first inverting unit is adapted to receive and respond to the first signal to output a third signal, wherein the third signal is a signal that is inverted from the first power supply input to the first input terminal; The second inverting unit is adapted to receive and output the second signal in response to the third signal.

4. The level conversion circuit according to claim 3, characterized in that, The second drain is connected to reference ground via the first transistor; The first transistor includes a first gate, a first source, and a first drain. The first drain is connected to the second drain, and the first source is connected to a reference ground. The first gate receives and responds to the third signal, and when the third signal is high, it cuts off the quiescent current generated by the boost unit.

5. The level conversion circuit according to claim 4, characterized in that, The first inverting unit includes: The sixth transistor includes a sixth gate, a sixth source, and a sixth drain. The sixth gate is connected to the first output terminal, and the sixth source is connected to a reference ground. The eighth transistor includes an eighth gate, an eighth source, and an eighth drain. The eighth gate is connected to the first output terminal, the eighth source is connected to the second power supply, and the eighth drain is connected to the sixth drain, outputting the third signal. The first gate is connected to the eighth source.

6. The level conversion circuit according to claim 5, characterized in that, The eighth source is connected to the second power supply via the seventh transistor; The seventh transistor includes a seventh gate, a seventh source, and a seventh drain. The seventh drain is connected to the second power supply, and the seventh gate and the seventh drain are connected to the eighth source.

7. The level conversion circuit according to claim 5, characterized in that, The output unit further includes: The ninth transistor includes a ninth gate, a ninth source, and a ninth drain. The ninth gate receives and responds to the second signal to control the operating state of the ninth transistor. The ninth source is connected to the second power supply, and the ninth drain is connected to the eighth drain.

8. The level conversion circuit according to claim 1, characterized in that, When the first power supply is at a high level, the third transistor is turned off, the boost unit generates a mirror current at the first output terminal, and the output unit receives and responds to the mirror current to output a high-level signal of the second power supply.

9. A chip, characterized in that, The chip includes a level conversion circuit as described in any one of claims 1-8.

10. An electronic device, characterized in that, The electronic device includes the chip as described in claim 9.

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