An FPGA-based CML video interface device

Abstract

This utility model discloses a CML video interface device based on FPGA, comprising: a CML video signal serial-to-parallel conversion module, including a first bitrate configuration unit, a first chip, a second bitrate configuration unit, and a second chip; wherein, the CML video signal serial-to-parallel conversion module is connected to the output terminal of a CML digital video generation unit through a switching unit, and the output terminal of the CML video signal serial-to-parallel conversion module is connected to the input terminal of a downstream processing unit; the CML digital video generation unit is integrated in the FPGA processing module, and the input terminal of the CML digital video generation unit is connected to a video data source; based on the bitrate range of the downstream processing unit, the switching unit controls the switching between the first output line and the second output line of the CML video signal serial-to-parallel conversion module; the first output line includes the first bitrate configuration unit and the first chip, and the second output line includes the second bitrate configuration unit and the second chip.

Description

Technical Field

[0001] This utility model relates to the field of video processing technology, and specifically to a CML video interface device based on FPGA. Background Technology

[0002] CML (Current Mode Logic) digital video interfaces are widely used in modern military equipment, especially in devices such as image trackers, infrared and television cameras. These devices are responsible for performing critical functions such as target recognition, tracking, and image processing. Currently, devices such as infrared and television cameras can generate CML video signals and transmit the acquired image data to downstream processing units via a serial interface. Therefore, the development of downstream products relies on this type of CML signal source.

[0003] Currently, infrared and television camera equipment are expensive and difficult to obtain, even in the early stages of project development. Due to the mismatch in bitrate specifications between the video signal source and the downstream processing unit, it is usually necessary to prepare adapters with different bitrate ranges to adapt to actual use needs. Furthermore, the transmission rates and protocols of CML data sources with different requirements are usually different, which will significantly prolong the R&D cycle and increase development costs. Utility Model Content

[0004] In view of this, the present invention provides an FPGA-based CML video interface device to solve the problems in the prior art where the resolution and frame rate of CML video signal sources are diverse, the bit rate is mismatched with the downstream processing unit, and there is a lack of compatible parts between devices, which leads to development difficulties.

[0005] This utility model embodiment provides an FPGA-based CML video interface device, including:

[0006] The CML video signal serial-to-parallel conversion module includes a first bit rate configuration unit, a first chip, a second bit rate configuration unit, and a second chip.

[0007] The CML video signal serial-to-parallel conversion module is connected to the output of the CML digital video generation unit via a switching unit, and the output of the CML video signal serial-to-parallel conversion module is connected to the input of the downstream processing unit. The CML digital video generation unit is integrated into the FPGA processing module, and its input is connected to a video data source. Based on the bitrate range of the downstream processing unit, the switching unit controls the switching between the first and second output lines of the CML video signal serial-to-parallel conversion module. The first output line includes a first bitrate configuration unit and a first chip, and the second output line includes a second bitrate configuration unit and a second chip.

[0008] Optionally, the FPGA processing module also includes:

[0009] A camera configuration unit is used to configure the binocular camera connected to the FPGA processing module;

[0010] The DVP interface image processing unit has its input end connected to the output end of the binocular camera, and its output end is connected to the input end of the CML digital video generation unit.

[0011] Optionally, the first chip is a BLK2711 chip, and the second chip is an SC5103 chip.

[0012] Optionally, the CML video signal serial-to-parallel conversion module is integrated on a single PCB board; the CML video signal serial-to-parallel conversion module is electrically connected to the FPGA processing module via an FMC interface at the edge of the PCB board.

[0013] Optionally, the PCB board is fixedly connected to the FPGA processing module by at least one washer screw; the PCB board at least partially overlaps the FPGA processing module above or below.

[0014] Optionally, several SMA RF connectors are provided on the side of the PCB board away from the FPGA processing module.

[0015] Optionally, eight SMA RF connectors are selected to form four pairs of CML differential signal interfaces, wherein the four pairs of CML differential signal interfaces include: input / output of CML1_P, input / output of CML1_N, input / output of CML2_P and input / output of CML2_N.

[0016] Optionally, six SMA RF connectors are selected and brought out from the GTX clock data interface and a pair of GTX data interfaces of the FPGA processing module via the FMC interface to realize the expansion of GTX communication in 1 lane.

[0017] Optionally, both the first rate configuration unit and the second rate configuration unit include: an initialization parameter configuration subunit, a clock frequency configuration subunit, a working mode configuration subunit, and a register configuration subunit.

[0018] Optionally, it also includes:

[0019] The bitrate identification unit has its input end connected to the output end of the downstream processing unit, and its output end connected to the CML digital video generation unit. The bitrate identification unit determines the bitrate range based on the data received from the downstream processing unit and sends the corresponding switching signal to the switching unit to switch the output line of the CML video signal serial-to-parallel conversion module.

[0020] The beneficial effects of this utility model are:

[0021] 1. The FPGA-based CML video interface device provided in this embodiment fills the technical gap of direct interconnection between 0.5Gbps to 2.5Gbps CML digital video interface and FPGA, and provides a clear idea and feasible implementation path for the localization of CML digital video interface chip, thereby improving the integration and miniaturization of weapon equipment such as seekers and image trackers.

[0022] 2. This embodiment provides an FPGA-based CML video interface device, employing a multi-chip architecture. It primarily utilizes FPGA to construct a 0.5Gbps to 2.5Gbps CML digital video interface. Market research reveals that products from most FPGA chip manufacturers, including Xilinx, Shanghai Fudan Microelectronics, and Shenzhen Guowei Electronics, can achieve 0.5Gbps to 2.5Gbps CML digital video interface expansion through the FPGA-based CML video interface device provided in this embodiment.

[0023] 3. This embodiment provides an FPGA-based CML video interface device that employs a low-power, compact embedded image processing technology. It can adapt to various resolutions and frame rates, enabling real-time acquisition, processing, and output of CML digital video under limited data link bandwidth conditions. This technology has broad application potential in the field of image recording for optoelectronic equipment on aviation, land, and offshore platforms. Attached Figure Description

[0024] The features and advantages of this utility model will be more clearly understood by referring to the accompanying drawings. The drawings are schematic and should not be construed as limiting the utility model in any way. In the drawings:

[0025] Figure 1 A structural diagram of an FPGA-based CML video interface device is shown in an embodiment of this utility model.

[0026] Figure 2 A block diagram of an FPGA-based CML video interface device is shown in an embodiment of the present invention.

[0027] Figure 3 A schematic diagram of the BLK2711 chip and its surrounding circuitry in an FPGA-based CML video interface device according to an embodiment of this utility model is shown.

[0028] Figure 4 A schematic diagram of the SC5103 chip and its surrounding circuitry in an FPGA-based CML video interface device according to an embodiment of this utility model is shown.

[0029] Figure 5A structural diagram of another FPGA-based CML video interface device is shown in an embodiment of this utility model;

[0030] Figure 6 This diagram shows a PCB planar structure of a CML video signal serial-to-parallel conversion module according to an embodiment of the present invention;

[0031] Figure 7 This shows a PCB side view of a CML video signal serial-to-parallel conversion module according to an embodiment of the present invention;

[0032] Figure 8 The diagram shows a PCB planar structure of an FPGA-based CML video interface device according to an embodiment of the present invention.

[0033] Figure 9 A PCB side view of an FPGA-based CML video interface device according to an embodiment of the present invention is shown. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0035] This utility model provides an FPGA-based CML video interface device, including a CML video signal serial-to-parallel conversion module. The CML video signal serial-to-parallel conversion module includes a first bitrate configuration unit 102, a first chip 201, a second bitrate configuration unit 103, and a second chip 202. The CML video signal serial-to-parallel conversion module is connected to the output of a CML digital video generation unit 101 via a switching unit, and the output of the CML video signal serial-to-parallel conversion module is connected to the input of a downstream processing unit 400. The CML digital video generation unit 101 is integrated into the FPGA processing module, and the input of the CML digital video generation unit 101 is connected to a video data source. Based on the bitrate range of the downstream processing unit 400, the switching unit controls the switching between the first and second output lines of the CML video signal serial-to-parallel conversion module; the first output line includes the first bitrate configuration unit 102 and the first chip 201, and the second output line includes the second bitrate configuration unit 103 and the second chip 202.

[0036] like Figure 1As shown, the FPGA processing module also includes a camera configuration unit 105 and a DVP interface image processing unit 106. The camera configuration unit 105 is used to configure the binocular camera 300 connected to the FPGA processing module. The input terminal of the DVP interface image processing unit 106 is connected to the output terminal of the binocular camera 300, and the output terminal of the DVP interface image processing unit 106 is connected to the input terminal of the CML digital video generation unit 101.

[0037] As an optional implementation, a bitrate identification unit 104 is also included. The input of the bitrate identification unit 104 is connected to the output of the downstream processing unit 400, and the output of the bitrate identification unit 104 is connected to the CML digital video generation unit 101. The bitrate identification unit 104 determines the bitrate range based on the data received from the downstream processing unit 400 and sends a corresponding switching signal to the switching unit to switch the output line of the CML video signal serial-to-parallel conversion module. In a specific embodiment, the switching unit is integrated into the CML digital video generation unit 101.

[0038] In a specific embodiment, the binocular camera inputs real-time video signals into the FPGA for processing via the DVP interface, and the processed video can be used as the source of CML digital video signals.

[0039] As an optional implementation, the CML video signal serial-to-parallel conversion module employs two chips supporting different serial port transmission rates. In a specific embodiment, the first chip is a BLK2711 chip, whose serial port transmission rate ranges from 1.6 to 2.5 Gbps, and the second chip is an SC5103 chip, whose serial port transmission rate ranges from 0.6 to 1.5 Gbps. The module framework is as follows: Figure 2 As shown, the binocular camera is connected to the FPGA development board. The FPGA development board is connected to the BLK2711 chip and the SC5103 chip through two sets of interfaces respectively. The specific serial port connection relationship is as follows: the FPGA development board sends data to the BLK2711 chip / SC5103 chip through the parallel port 16-bit, and the FPGA development board receives data from the BLK2711 chip / SC5103 chip through the parallel port 16-bit. In addition, the FPGA development board and the BLK2711 chip / SC5103 chip transmit control signals and clock signals through one serial port. The two channels have a total of 33 pairs of differential signal lines.

[0040] The specific circuit connection of the BLK2711 chip is as follows: Figure 3 As shown:

[0041] The ENABLE pin of the BLK2711 chip is connected to the CML_VDD voltage through a 10KΩ resistor. This pin can be grounded through another 10KΩ resistor, or directly grounded.

[0042] The PRSSEN pin of the BLK2711 chip is connected to the CML_VDD voltage via a 10KΩ resistor, or directly to the CML_VDD voltage, and this pin is grounded via another 10KΩ resistor.

[0043] The DOUTTXP and DOUTTXN pins of the BLK2711 chip are the CML signal output terminals, corresponding to... Figure 2 CML_OUT+ and CML_OUT-.

[0044] The DINRXP and DINRXN pins of the BLK2711 chip are the CML signal input terminals, corresponding to... Figure 2 CML1_IN+ and CML1_IN-.

[0045] The specific circuit connection of the SC5103 chip is as follows: Figure 4 As shown:

[0046] The DINRXP and DINRXN pins of the SC5103 chip are the CML signal input terminals, corresponding to... Figure 2 The CML2_IN+ and CML2_IN- signals are filtered by an RC circuit.

[0047] Both the first and second rate configuration units include: an initialization parameter configuration subunit, a clock frequency configuration subunit, a working mode configuration subunit, and a register configuration subunit.

[0048] The working principle of the FPGA-based CML video interface device using BLK2711 and SC5103 chips is as follows: Figure 5 As shown, the camera configuration module is used to configure the camera's initialization parameters, including clock frequency, working mode, image resolution, and image format. The DVP interface image processing module is used to receive and process DVP interface video signal input from external devices, realizing image data acquisition, format conversion, and preprocessing functions. The CML digital video generation module selectively outputs the processed video signal to either the BLK2711 channel or the SC5103 channel according to the actual bitrate and application requirements.

[0049] The initialization process of the BLK2711 channel is as follows:

[0050] The BLK2711 configuration module sets the initialization parameters of the BLK2711 chip, including clock frequency, operating mode, and register configuration, to ensure that its output serial signal operates stably in the required frequency band (1.6~2.5Gbps).

[0051] The initialization process for the SC5103 channel is as follows:

[0052] The SC5103 configuration module initializes the SC5103 chip by setting parameters, including clock frequency, operating mode, and register configuration, to ensure that its output serial signal operates stably in the required frequency band (0.5~1.5Gbps).

[0053] As an optional implementation method, such as Figure 6 As shown, the CML video signal serial-to-parallel conversion module is integrated on a PCB board; the CML video signal serial-to-parallel conversion module is electrically connected to the FPGA processing module through the FMC interface at the edge of the PCB board.

[0054] The PCB design features a 6-layer structure with a thickness of 1.6mm, using IT180A board material. This module integrates one BLK2711 and one SC5103 chip, supporting CML digital video signal input and output from 0.5Gbps to 2.5Gbps. The module offers flexible power supply options, allowing for either an external 12V power supply or power from the FPGA development board via the FMC interface.

[0055] like Figures 7 to 9 As shown, a standardized FMC LPC interface 3 is designed on the PCB board. This interface directly interfaces with the FMC interface on the FPGA development board, making installation convenient, highly versatile, and supporting connection to the FMC expansion ports of other development boards. The FMC interface 3 is located on one side of the CML video signal serial-to-parallel conversion module PCB board, while several SMA RF connectors 4 are located on the other side of the PCB board.

[0056] The PCB board 2 is fixedly connected to the FPGA processing module 1 by at least one washer screw 5; the PCB board 2 is located above or below the FPGA processing module 1 at least partially overlapping.

[0057] On the side of the PCB board away from the FPGA processing module, there are several SMA RF connectors 4. In a specific embodiment, 14 SMA connectors are provided.

[0058] Eight SMA RF connectors are selected to form four pairs of CML differential signal interfaces. The four pairs of CML differential signal interfaces include: input / output of CML1_P, input / output of CML1_N, input / output of CML2_P, and input / output of CML2_N.

[0059] Six SMA RF connectors are selected and brought out from the GTX clock data interface and a pair of GTX data interfaces of the FPGA processing module via the FMC interface to realize the expansion of GTX communication in 1 lane.

[0060] This embodiment provides an FPGA-based CML video interface device, which fills the technical gap of direct interconnection between 0.5Gbps to 2.5Gbps CML digital video interfaces and FPGAs. It provides a clear idea and feasible implementation path for the localization of CML digital video interface chips, thereby improving the integration and miniaturization of weapon equipment such as seekers and image trackers.

[0061] This embodiment provides an FPGA-based CML video interface device, employing a multi-chip architecture. It primarily utilizes FPGAs to construct a 0.5Gbps to 2.5Gbps CML digital video interface. Market research reveals that products from most FPGA chip manufacturers, including Xilinx, Shanghai Fudan Microelectronics, and Shenzhen Guowei Electronics, can achieve 0.5Gbps to 2.5Gbps CML digital video interface expansion through the FPGA-based CML video interface device provided in this embodiment.

[0062] This embodiment provides an FPGA-based CML video interface device that employs a low-power, compact embedded image processing technology. It can adapt to various resolutions and frame rates, enabling real-time acquisition, processing, and output of CML digital video under limited data link bandwidth. This technology has broad application potential in the field of image recording for optoelectronic equipment on aviation, land, and offshore platforms.

[0063] Although embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. An FPGA-based CML video interface device, characterized by, include: The CML video signal serial-to-parallel conversion module includes a first bit rate configuration unit, a first chip, a second bit rate configuration unit, and a second chip. The CML video signal serial-to-parallel conversion module is connected to the output of the CML digital video generation unit via a switching unit, and the output of the CML video signal serial-to-parallel conversion module is connected to the input of the downstream processing unit; the CML digital video generation unit is integrated in the FPGA processing module, and the input of the CML digital video generation unit is connected to the video data source. Based on the bitrate range of the downstream processing unit, the switching unit controls the switching of the first output line and the second output line of the CML video signal serial-to-parallel conversion module; the first output line includes the first bitrate configuration unit and the first chip, and the second output line includes the second bitrate configuration unit and the second chip.

2. The FPGA-based CML video interface apparatus of claim 1, wherein, The FPGA processing module also includes: A camera configuration unit is used to configure the binocular camera connected to the FPGA processing module; The DVP interface image processing unit has its input end connected to the output end of the binocular camera, and its output end is connected to the input end of the CML digital video generation unit.

3. The FPGA-based CML video interface apparatus of claim 1, wherein, The first chip is a BLK2711 chip, and the second chip is an SC5103 chip.

4. The FPGA-based CML video interface apparatus of claim 1, wherein, The CML video signal serial-to-parallel conversion module is integrated on a PCB board; the CML video signal serial-to-parallel conversion module is electrically connected to the FPGA processing module through the FMC interface at the edge of the PCB board.

5. The FPGA-based CML video interface apparatus of claim 4, wherein, The PCB board is fixedly connected to the FPGA processing module by at least one washer screw; the PCB board is located above or below the FPGA processing module at least partially overlapping it.

6. The FPGA-based CML video interface apparatus of claim 5, wherein, On the side of the PCB board away from the FPGA processing module, there are several SMA RF connectors.

7. The FPGA-based CML video interface apparatus of claim 6, wherein, Eight SMA RF connectors are selected to form four pairs of CML differential signal interfaces, wherein the four pairs of CML differential signal interfaces include: input / output of CML1_P, input / output of CML1_N, input / output of CML2_P, and input / output of CML2_N.

8. The FPGA-based CML video interface apparatus of claim 6, wherein, Six SMA RF connectors are selected and brought out from the GTX clock data interface and a pair of GTX data interfaces of the FPGA processing module via the FMC interface to realize the expansion of GTX communication in 1 lane.

9. The FPGA-based CML video interface apparatus of claim 1, wherein, Both the first code rate configuration unit and the second code rate configuration unit include: an initialization parameter configuration subunit, a clock frequency configuration subunit, a working mode configuration subunit, and a register configuration subunit.

10. The FPGA-based CML video interface apparatus of claim 1, wherein, Also includes: A bitrate recognition unit, the input of which is connected to the output of the downstream processing unit, and the output of the bitrate recognition unit is connected to the CML digital video generation unit; The bitrate identification unit determines the bitrate range based on the data received from the downstream processing unit and sends a corresponding switching signal to the switching unit to switch the output line of the CML video signal serial-to-parallel conversion module.

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