Display panel and display device
By optimizing the anti-static circuit layout within the display panel bezel area and using titanium-aluminum-titanium materials to set up signal lines and scan lines on different layers to form multiple diodes to release static electricity, the problem of increased bezel space was solved, achieving the effect of narrow bezel and low impedance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- YUNGU GUAN TECH CO LTD
- Filing Date
- 2025-04-30
- Publication Date
- 2026-07-03
AI Technical Summary
Existing integrated gate-driven display panels require anti-static devices and wiring in the bezel area, which increases the bezel space and makes it difficult to achieve a narrow bezel.
The layout of the anti-static circuit within the frame area is optimized by placing the signal lines above the anti-static devices. The signal lines and scan lines are made of titanium-aluminum-titanium materials and are set on different layers. Static electricity is released through the switch branch, forming multiple diodes to reduce the wiring space.
It achieves the goal of reducing the width of the bezel area, lowering the impedance of the signal lines, and preventing the internal circuitry from being damaged by electrostatic discharge while maintaining the anti-static function.
Smart Images
Figure CN224460469U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, and more specifically to a display panel and display device. Background Technology
[0002] Organic Light Emitting Diode (OLED) display technology is considered the most promising next-generation flat panel display technology. Currently, integrated gate driver (GIP) display panels require integrated gate drivers and signal lines to be located within the bezel areas on both sides of the display area. To prevent electrostatic discharge (ESD) damage to the GIP, an ESD protection design is necessary within the bezel area. This requires additional ESD protection devices and corresponding wiring, increasing the wiring space within the bezel area, which is detrimental to achieving narrow bezels.
[0003] Therefore, existing display panels need to be improved. Summary of the Invention
[0004] In view of this, the purpose of this application is to provide a display panel and display device that aims to improve the performance of the display panel.
[0005] To achieve the above objectives, this application adopts the following technical solution.
[0006] A display panel includes a display area and a border area that at least partially surrounds the display area.
[0007] It also includes a substrate and a driving circuit layer disposed on the substrate.
[0008] The driving circuit layer includes a pixel driving circuit located in the display area, and a scanning circuit and an anti-static circuit located in the border area;
[0009] The anti-static circuit includes a switch branch, one end of which is electrically connected to a first signal line and the other end of which is electrically connected to a second signal line. The switch branch has an access point, which is electrically connected to a scan line. The scan line is used to electrically connect to the scan circuit and release the static electricity of the scan circuit through the first signal line or the second signal line. The scan line is on a different layer than the first signal line and the second signal line.
[0010] In a preferred embodiment, the scan line is located on the upper side of the switch branch.
[0011] In a preferred embodiment, the anti-static circuit includes a switching branch having at least a first transistor and a second transistor. The gate of the first transistor is connected via a trace to its first electrode and the first signal line. The second electrode of the second transistor is electrically connected to the second signal line. The second electrode of the first transistor is connected to an access point, and the gate of the second transistor is connected via a trace to its first electrode access point. The access point is electrically connected to a scan line, which is used to electrically connect to the scan circuit. The scan line is stacked with the transistor.
[0012] Preferably, the anti-static circuit includes a switching branch having a first transistor, a second transistor, a third transistor, and a fourth transistor.
[0013] The gate terminal of the first transistor is connected to its first electrode and the first signal line via a trace, and the second electrode of the second transistor is electrically connected to the second signal line.
[0014] The gate of the third transistor is connected to its first terminal via a trace and then to the second terminal of the first transistor. The second terminal of the third transistor is electrically connected to an access point, and the access point is electrically connected to a scan line.
[0015] The gate terminal of the fourth transistor is connected to its first terminal via a trace and connected to the access point. The second terminal of the fourth transistor is connected to the first terminal of the second transistor, and the gate terminal of the second transistor is connected to its first terminal via a trace.
[0016] In a preferred embodiment, the driving circuit layer includes a stacked semiconductor layer and a first metal layer.
[0017] The semiconductor layer includes an active layer located in the border region and extending along a second direction;
[0018] Preferably, the semiconductor layer includes a plurality of active layers located in the border region and extending along a second direction;
[0019] Preferably, the semiconductor layer includes a plurality of mutually parallel active layers located in the border region and extending along a second direction;
[0020] The first metal layer includes a plurality of first metals, which are configured to be spaced apart along the active layer, and adjacent first metals do not contact each other in a first direction;
[0021] Preferably, each of the active layers has at least two of the first metals above it, and each of the first metals is combined with the active layer to form a transistor;
[0022] Preferably, each of the active layers has four of the first metals above it, and each of the first metals is combined with the active layer to form a transistor.
[0023] In a preferred embodiment, the display panel includes a third metal layer and a fourth metal layer. The third metal layer is stacked on the first metal layer through an insulating film layer. The third metal layer includes a first signal line, a second signal line, and a second metal. The first signal line and the second signal line are electrically connected to the active layer, respectively.
[0024] The insulating film layer includes a plurality of first and second through-holes. The second metal is electrically connected to the first metal through the first through-holes and electrically connected to the active layer through the corresponding second through-holes. The second metal is used to short-circuit the gate and source or drain of the transistor formed by the second metal and the active layer.
[0025] The fourth metal layer is stacked on the third metal layer through an insulating layer, and the fourth metal layer includes scan lines that are electrically connected to the second metal.
[0026] In a preferred embodiment, the first perforation faces the second metal to expose a portion of the second metal, and the second perforation faces the active layer to expose a portion of the active layer;
[0027] Preferably, the orthographic projections of the first and second perforations onto the substrate are circular, elliptical, triangular, or square.
[0028] In a preferred embodiment, in the display panel, a plurality of second metals are electrically connected to the gate and source or drain of the corresponding second metal and the transistor formed by the active layer, so as to form a plurality of diodes;
[0029] Preferably, the four second metals are electrically connected to the gate and source or drain of the transistor formed by the corresponding second metal and the active layer, respectively, to form a first diode, a second diode, a third diode and a fourth diode, wherein the first diode is close to the first signal line and the fourth diode is close to the second signal line.
[0030] In a preferred embodiment, the insulating layer is provided with a plurality of perforations, the orthogonal projection of which onto the third metal layer covers one of the second metals that matches the active layer;
[0031] Preferably, the perforation faces the second metal that matches the third diode, with the exposed portion serving as an input point;
[0032] Preferably, the scan line is electrically connected to the input point through the perforation.
[0033] In a preferred embodiment, the anti-static circuit is disposed between the two scanning circuits, and the anti-static circuit is electrically connected to the scanning circuit.
[0034] Based on the same inventive concept, this application proposes a display device that includes the aforementioned display panel.
[0035] Compared with the prior art, the display panel proposed in this application optimizes the wiring of the anti-static devices and corresponding signal lines of the anti-static circuit in the bezel area. The signal lines are set on the upper side of the anti-static device area. Compared with the current signal line routing around the ESD device, the wiring space of the anti-static circuit can be reduced, thus achieving a narrow bezel. Attached Figure Description
[0036] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0037] Figure 1 A schematic diagram showing the installation of anti-static circuitry and signal line routing on an existing display panel;
[0038] Figure 2 This is a schematic diagram of the topology of the anti-static circuit according to an embodiment of this application;
[0039] Figure 3 This is a schematic diagram of the anti-static circuit topology according to another embodiment of this application;
[0040] Figures 4-9 for Figure 3 A layered schematic diagram of the anti-static circuit traces in the embodiment;
[0041] Figure 10 This is a schematic diagram of the anti-static circuit and signal line routing on the display panel according to an embodiment of this application. Detailed Implementation
[0042] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.
[0043] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0044] In integrated gate driver (GIP) display panels, integrated gate driver (GIP) units and signal lines need to be installed in the bezel areas on both sides. To prevent the GIP units 200 from being damaged by electrostatic discharge (ESD), an ESD protection design is required. This necessitates the installation of ESD protection device areas and corresponding wiring in the bezel areas on both sides, such as... Figure 1 As shown, the anti-static device area is located in the corner of the display panel (e.g., the four corners). The signal line (M1(Mo)) that needs to be connected to the anti-static device (ESD) 100 is routed around the ESD device. The signal line (M1(Mo)) is connected to the input in point of the anti-static device through the line bridge (M3(TiAlTi)). This increases the space of the bezel, which is not conducive to narrow bezels.
[0045] To this end, the applicant has optimized the wiring in the bezel area of the existing integrated gate-driven display panel and adjusted the anti-static circuit in the bezel area, which includes the wiring of the anti-static device and the corresponding signal line. The signal line is located above the anti-static device, thus satisfying the anti-static requirements while reducing the width of the bezel area, which is beneficial for achieving a narrow bezel.
[0046] The display panel and display device proposed in this application will now be described with reference to the accompanying drawings.
[0047] The display panel has a display area AA and a bezel area (NA) that at least partially surrounds the display area AA. Preferably, the bezel area is provided with a bonding area, on which a driving module is mounted in a subsequent process, thereby enabling the display panel to operate based on the driving of the driving module.
[0048] The display panel includes a substrate, a driving circuit layer disposed on the substrate, and a light-emitting layer disposed on the side of the driving circuit layer away from the substrate. The substrate can be flexible and can be formed of any suitable insulating material with flexibility. The driving circuit layer may include stacked semiconductor layers, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, and an insulating film layer disposed between two adjacent conductive film layers. Signal traces are provided in the first, second, third, and fourth metal layers (and in some cases, a fifth metal layer). The corresponding signal traces are electrically connected to each other to form multiple pixel driving circuits in the display area. Signal traces, scanning circuits (such as GIP units), and anti-static (ESD) circuits are formed in the bezel area. The anti-static circuit includes a switch branch, one end of which is electrically connected to the first signal line and the other end of which is electrically connected to the second signal line. The switch branch has an access point that is electrically connected to the scan line. The scan line is used to electrically connect to the scanning circuit (GIP unit) and releases the static electricity accumulated on the scan line or conducted by the scan circuit through the first or second signal line. The scan line is set on a different layer from the first and second signal lines.
[0049] The scan line is stacked with the switch branch (e.g., the scan line is located above the switch branch) to optimize the routing space of the anti-static circuit and facilitate the achievement of a narrow bezel.
[0050] like Figure 2 The diagram shows the topology of the anti-static circuit on the display panel according to an embodiment of this application.
[0051] The anti-static circuit includes transistor 10 (first transistor) and transistor 20 (second transistor). The gate of transistor 10 is electrically connected via wiring to its first terminal and a first signal line (VGH), and the first signal line (VGH) is electrically connected to the first terminal of transistor 10. Signal line 30 is electrically connected to the second terminal of transistor 10 and the first terminal of transistor 20 (the connection point between the second terminal of transistor 10 and the first terminal of transistor 20 serves as an input point, and signal line 30 is electrically connected to this input point). The second terminal of transistor 20 is connected to a second signal line (VGL). The gate of transistor 20 is electrically connected via wiring to signal line 30, the second terminal of transistor 10, and the first terminal of transistor 20. In this way, any positive or negative charge accumulating on signal line 30 can be released to one end, preventing damage to internal circuitry (such as GIP units). Signal line 30 can be electrically connected to internal circuitry (such as GIP units) to prevent electrostatic discharge damage.
[0052] As Figure 2 Variations of the implementation method, such as Figure 3 The diagram shows a topology of an anti-static circuit on a display panel according to another embodiment of this application.
[0053] The anti-static circuit includes a first transistor 11, a third transistor 12, a fourth transistor 21, and a second transistor 22 (collectively referred to as transistors, and numbered for ease of description in the accompanying drawings).
[0054] The gate of the first transistor 11 is electrically connected to its first terminal and the first signal line (VGH) via wiring, and the first signal line (VGH) is electrically connected to the first terminal of the first transistor 11. The second terminal of the first transistor 11 is electrically connected to the first terminal of the third transistor 12. The second terminal of the third transistor 12 is electrically connected to the first terminal of the fourth transistor 21. The second terminal of the fourth transistor 21 is electrically connected to the first terminal of the second transistor 22. The second terminal of the second transistor 22 is connected to the second signal line (VGL). The connection point between the second terminal of the third transistor 12 and the first terminal of the fourth transistor 21 serves as the input point (also called the in point), and this input point is electrically connected to the signal line 30 (Vin signal line). The gate of the third transistor 12 is electrically connected to its first terminal and the second terminal of the first transistor 11 via wiring. The gate of the second transistor 22 is electrically connected to its first terminal and the second terminal of the fourth transistor 21 via wiring. The first terminal of the fourth transistor 21 is electrically connected to the signal line 30, its first terminal, and the second terminal of the third transistor 12. In this way, any positive or negative charge accumulating on the signal line 30 can be released to one end, thus preventing damage to internal circuitry (such as the GIP unit). The signal line 30 can be electrically connected to internal circuitry (such as the GIP unit).
[0055] Signal line 30 is connected to the anti-static device via an input point. Its two ends are connected to the first signal line (VGH) and the second signal line (VGL). This allows any positive or negative charge accumulating on the signal line to be released to one end, preventing damage to the internal circuitry. In this embodiment, for each transistor, its gate is electrically connected to its first electrode (source / drain) via wiring to form a diode, thus constituting four diodes. These four diodes are located between the first signal line (VGH) and the second signal line (VGL). An input point (also called an in point) is located between the second and third diodes and connected to signal line 30. Any positive or negative charge accumulating on the signal line can be released to one end, preventing damage to the internal circuitry. In this embodiment, signal line 30 is made of titanium-aluminum-titanium alloy and is disposed on a different layer from the first signal line (VGH) and the second signal line (VGL). This avoids placing the signal line around the anti-static device (transistor), which helps to reduce the signal line wiring space and achieve a narrow bezel. In addition, the signal line 30 is made of titanium aluminum titanium, which reduces impedance compared to the molybdenum (Mo) used in the current solution. Furthermore, the signal line 30 does not short-circuit with the internal anti-static device.
[0056] Next, combine Figures 4-9 and combined Figure 3 This is a schematic diagram illustrating the layered wiring of the anti-static circuit of this application.
[0057] The display panel includes a substrate and a driving circuit layer disposed on the substrate.
[0058] The driving circuit layer covers the frame area and includes a stacked semiconductor layer, a first metal layer, a third metal layer, a fourth metal layer, and an insulating film layer disposed between two adjacent conductive film layers.
[0059] The semiconductor layer includes an active layer 1 extending along the second direction (y-direction), see [link to relevant documentation]. Figure 4 The PSIs are arranged in two rows, and the signal lines are connected in series using long straight traces of the active layer 1 (semiconductor PSI layer).
[0060] The first metal layer includes a plurality of first metals 2, which are configured to be spaced apart along the active layer 1, and adjacent first metals 2 do not contact each other in the first direction (x direction) (i.e., there is a gap between adjacent first metals 2). Four first metals 2 are matched above each active layer 1. See [reference needed]. Figure 5 The first metal 2 is combined with the active layer 1 to form transistors 11 / 12 / 21 / 22 (see...) Figure 3 The first metal 2 is made of Mo material.
[0061] An insulating film layer is stacked on a first metal layer, and a plurality of first perforations 3a and matching second perforations 3b are provided on the insulating film layer. The first perforations 3a face the first metal 2 to expose a portion of the first metal 2, and the second perforations 3b face the active layer 1 to expose a portion of the active layer 1.
[0062] The driving circuit layer also includes a third metal layer and a fourth metal layer.
[0063] A third metal layer is stacked on an insulating film layer. The third metal layer includes a first signal line 41 (i.e., signal line VGH), a second signal line 41 (signal line VGL), and a second metal 43. The second metal 43 is electrically connected to the first metal 2 and the matching active layer 1 (i.e., the second metal 43 is electrically connected to the gate and source / drain of the transistor) through a first through-hole 3a and a matching second through-hole 3b.
[0064] A fourth metal layer is stacked on top of the third metal layer through an insulating layer. A via 51 is provided on the insulating layer. The fourth metal layer includes a third metal 61 (i.e., signal line 30), which is electrically connected to an input point (also called the in point) through the via 51. The via 51 exposes a second metal 43 (i.e., the orthographic projection of the via 51 onto the third metal layer covers one of the second metals 43). The area 43a of the exposed second metal 43 serves as the input point (also called the in point), and the third metal 61 is electrically connected to the input point (also called the in point) through the via 51. Connecting an anti-static device through the input point simplifies wiring space.
[0065] The orthographic projection of the first and second perforations onto the substrate is circular, elliptical, triangular, or square.
[0066] In this embodiment, the gate and source / drain of the corresponding transistor are shorted by electrically connecting the second metal 43 (such as titanium aluminum titanium / TiAlTi material), which is equivalent to forming four diodes D1 / D2 / D3 / D4 (the topology of which is referenced). Figure 3 Four diodes are connected in series between the first signal line (VGH) and the second signal line (VGL). The first signal line (VGH) and the second signal line (VGL) are made of TiAlTi. A third metal 61 passes through the internal structure of the device and is electrically connected between diodes D2 and D3 (as the Vin point). The use of TiAlTi for the third metal 61 reduces impedance compared to traditional molybdenum (Mo) traces and avoids short-circuiting with internal anti-static devices. Alternatively, the gate and source / drain of the corresponding transistor can be shorted by electrically connecting the second metal 43 (e.g., made of TiAlTi), effectively forming two diodes (the topology is referenced here). Figure 2 ).
[0067] In other embodiments, the antistatic device may include six or more transistors, without limitation.
[0068] In a preferred embodiment, the anti-static circuit is disposed within the bezel area on both sides of the display area AA of the display panel, such as the area between GIP units (also known as the dummy area). Figure 10 The anti-static circuit 400 is located in the area between the two GIP units (scanning circuits) 300, and the anti-static circuit is electrically connected to the scanning circuit. It can balance the wiring space of the GIP unit, optimize the placement space of the anti-static device area, and make it easier to reduce the bezel size. At the same time, it has the function of releasing the anti-static function of the scanning circuit.
[0069] Based on the same inventive concept, this application also provides a display device, which includes the display panel provided in the above embodiments. By optimizing the placement space of the anti-static circuits in the bezel areas on both sides of the display area AA of the display panel, it is more conducive to reducing the bezel size, while also providing anti-static functionality.
[0070] While this application has been described herein with reference to specific embodiments, it should be understood that these embodiments are merely examples of the principles and applications of this application. Therefore, it should be understood that many modifications can be made to the exemplary embodiments, and other arrangements can be designed without departing from the spirit and scope of this application as defined by the appended claims. It should be understood that different dependent claims and features described herein can be combined in ways different from those described in the original claims. It is also understood that features described in conjunction with individual embodiments can be used in other described embodiments.
Claims
1. A display panel, characterized by, Includes a display area and at least a border area surrounding the display area. It also includes a substrate and a driving circuit layer disposed on the substrate. The driving circuit layer includes a pixel driving circuit located in the display area, and a scanning circuit and an anti-static circuit located in the border area; The anti-static circuit includes a switch branch, one end of which is electrically connected to a first signal line and the other end of which is electrically connected to a second signal line. The switch branch has an access point, which is electrically connected to a scan line. The scan line is used to electrically connect to the scan circuit and release the static electricity of the scan circuit through the first signal line or the second signal line. The scan line is on a different layer than the first signal line and the second signal line.
2. The display panel as described in claim 1, characterized in that, The scan line is located on the upper side of the switch branch.
3. The display panel as described in claim 1, characterized in that, The anti-static circuit includes a switching branch having a first transistor and a second transistor. The gate of the first transistor is connected to its first electrode and the first signal line via a trace. The second electrode of the second transistor is electrically connected to the second signal line. The second electrode of the first transistor is connected to an access point, and the gate of the second transistor is connected to its first electrode access point via a trace. The access point is electrically connected to a scan line. The scan line is used to electrically connect to the scan circuit, and the scan line is stacked with the transistor.
4. The display panel as described in claim 3, characterized in that, The anti-static circuit also includes a switching branch for the third transistor and the fourth transistor. The gate terminal of the first transistor is connected to its first electrode and the first signal line via a trace, and the second electrode of the second transistor is electrically connected to the second signal line. The gate of the third transistor is connected to its first terminal via a trace and then to the second terminal of the first transistor. The second terminal of the third transistor is electrically connected to an access point, and the access point is electrically connected to a scan line. The gate terminal of the fourth transistor is connected to its first terminal via a trace and connected to the access point. The second terminal of the fourth transistor is connected to the first terminal of the second transistor, and the gate terminal of the second transistor is connected to its first terminal via a trace.
5. The display panel as described in claim 1, characterized in that, The driving circuit layer includes a stacked semiconductor layer and a first metal layer. The semiconductor layer includes an active layer located in the border region and extending along a second direction; The first metal layer includes a plurality of first metals, which are configured to be spaced apart along the active layer, and adjacent first metals do not contact each other in a first direction.
6. The display panel as described in claim 5, characterized in that, The semiconductor layer includes a plurality of active layers located in the border region and extending along a second direction.
7. The display panel as described in claim 5, characterized in that, The semiconductor layer includes a plurality of parallel active layers located in the border region and extending along a second direction.
8. The display panel as described in claim 5, characterized in that, Each of the active layers has at least two of the first metals above it, and each of the first metals is combined with the active layer to form a transistor.
9. The display panel as described in claim 5, characterized in that, Each of the active layers has four of the first metals above it, and each of the first metals is combined with the active layer to form a transistor.
10. The display panel as claimed in claim 5, characterized in that, It includes a third metal layer and a fourth metal layer. The third metal layer is stacked on the first metal layer through an insulating film layer. The third metal layer includes a first signal line, a second signal line and a second metal. The first signal line and the second signal line are electrically connected to the active layer, respectively. The insulating film layer includes a plurality of first and second through-holes. The second metal is electrically connected to the first metal through the first through-holes and electrically connected to the active layer through the corresponding second through-holes. The second metal is used to short-circuit the gate and source or drain of the transistor formed by the second metal and the active layer. The fourth metal layer is stacked on the third metal layer through an insulating layer, and the fourth metal layer includes scan lines that are electrically connected to the second metal.
11. The display panel as claimed in claim 10, characterized in that, The orthographic projection of the first and second perforations onto the substrate is circular, elliptical, triangular, or square.
12. The display panel as claimed in claim 10, characterized in that, The plurality of second metals are electrically connected to the gate and source or drain of the transistor formed by the corresponding second metal and the active layer.
13. The display panel as claimed in claim 10, characterized in that, The four second metals are electrically connected to the gate and source or drain of the transistor formed by the corresponding second metal and the active layer, respectively, to form a first diode, a second diode, a third diode and a fourth diode, wherein the first diode is close to the first signal line and the fourth diode is close to the second signal line.
14. The display panel as claimed in claim 13, characterized in that, The insulating layer is provided with a plurality of perforations, and the orthogonal projection of the perforations on the third metal layer covers one of the second metals that matches the active layer; The perforation is aligned with the second metal that matches the third diode, with the exposed portion serving as an input point; The scan line is electrically connected to the input point through the perforation.
15. The display panel as claimed in claim 1, characterized in that, The anti-static circuit is disposed in the frame area on both sides of the display area and in the area between the two scanning circuits, and the anti-static circuit is electrically connected to the scanning circuit.
16. A display device comprising: Includes the display panel as described in any one of claims 1-15.