Synchronous clock control device
By setting up a sampling channel and a closed-loop control mechanism in the digital isolation system, the timing error problem caused by the delay factor of the isolation device is solved by dynamically adjusting the delay variation of the isolation device, thus ensuring the timing accuracy and data transmission reliability of the system.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- BEIJING SHIGAN XINGBANG TECH CO LTD
- Filing Date
- 2025-08-12
- Publication Date
- 2026-07-07
AI Technical Summary
In digital isolation systems, the delay of isolation devices is affected by factors such as temperature, voltage, and device aging, causing the real-time clock delay between the transmitting and receiving ends to change constantly. Existing fixed delay compensation methods cannot dynamically adapt to these changes, affecting the timing accuracy and stability of the system.
The isolated sampling clock is fed back to the FPGA chip through the sampling channel to form a closed-loop control mechanism. The clock signal and data are transmitted in the same isolation path through the sampling channel, realizing real-time tracking and dynamic adjustment of the isolation delay. The trigger samples the data based on the sampling clock to dynamically compensate for the propagation delay.
It eliminates the latency accumulated during the isolation process, ensures that the data establishment and retention times meet the timing requirements, and improves the accuracy of the digital isolation system and the reliability of data transmission.
Smart Images
Figure CN224472024U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of synchronous clock technology for digital isolation systems, and more particularly to a synchronous clock control device. Background Technology
[0002] In digital isolation systems, the clock signal of the synchronous bus needs to be transmitted with electrical isolation through isolation devices. However, isolation devices introduce propagation delay during signal transmission, causing the clock signals at the transmitting and receiving ends to be out of sync, which seriously affects the timing accuracy and stability of the system. Existing technologies typically use fixed delay compensation circuits to adjust the delay parameters of the isolation devices to match the clock signal. However, the delay of the isolation devices is affected by factors such as temperature, voltage, and device aging, causing the real-time clock delay between the transmitting and receiving ends to vary constantly. Existing fixed delay compensation methods cannot dynamically adapt to changes, resulting in the accumulation of timing errors and seriously affecting the timing accuracy of the system. Summary of the Invention
[0003] In view of this, this application proposes a synchronous clock control device, including: an FPGA chip, an ADC chip, an isolation device, and a sampling channel;
[0004] The clock signal output terminal of the FPGA chip is connected to the clock signal input terminal of the isolation device through the first synchronous bus, and the isolated clock output terminal of the isolation device is electrically connected to the isolated clock input terminal of the ADC chip through the second synchronous bus.
[0005] The data output terminal of the ADC chip is connected to the first data input terminal of the isolation device through the second synchronization bus, and the first data output terminal of the isolation device is connected to the first data input terminal of the FPGA chip through the first synchronization bus.
[0006] The mining channel includes a first mining channel and a second mining channel;
[0007] The input terminal of the first sampling channel is electrically connected to the isolation clock output terminal of the isolation device, the output terminal of the first sampling channel is electrically connected to the first data input terminal of the isolation device, the input terminal of the second sampling channel is electrically connected to the first data output terminal of the isolation device, and the output terminal of the second sampling channel is connected to the second data input terminal of the FPGA chip, so as to transmit the sampling clock isolated by the isolation device to the FPGA chip.
[0008] The FPGA chip contains a trigger, which is suitable for sampling the data transmitted by the ADC chip using a sampling clock.
[0009] In one possible implementation, the data output of the FPGA chip is connected to the second data input of the isolation device via a first synchronization bus.
[0010] The data input terminal of the ADC chip is connected to the second data output terminal of the isolation device via the second synchronization bus.
[0011] In one possible implementation, the on-chip signal output of the FPGA chip is connected to the on-chip signal input of the isolation device via a first synchronization bus.
[0012] The chip signal input terminal of the ADC chip is connected to the chip signal output terminal of the isolation device through the second synchronous bus.
[0013] In one possible implementation, the isolation device is an optocoupler, a magnetic coupler, or a capacitively isolated device.
[0014] In one possible implementation, the input ground terminal and the output ground terminal of the isolation device are respectively grounded.
[0015] In one possible implementation, a first power supply and a second power supply are also included;
[0016] The output terminal of the first power supply is electrically connected to the high-voltage side power supply terminal of the isolation device, and the output terminal of the second power supply is electrically connected to the low-voltage side power supply terminal of the isolation device.
[0017] In one possible implementation, a first packaged capacitor is also included;
[0018] One end of the first packaged capacitor is connected to the high-voltage side power supply terminal of the isolation device, and the other end of the first packaged capacitor is grounded.
[0019] In one possible implementation, a second packaged capacitor is also included;
[0020] One end of the second-packaged capacitor is connected to the low-voltage side power supply terminal of the isolation device, and the other end of the second-packaged capacitor is grounded.
[0021] Beneficial effects
[0022] This application establishes a sampling channel that feeds back the isolated sampling clock FPGA-SCLK-FB to the FPGA chip to form a closed-loop control mechanism. The sampling channel ensures that the clock signal ADC-SCLK and ADC-MISO data are transmitted in the same isolation path, thereby enabling the FPGA chip to track and dynamically adjust the isolation delay changes in real time. This eliminates the delay accumulated in the FPGA-MISO data during the isolation process. The trigger can sample the transmitted FPGA-MISO data based on the sampling clock FPGA-SCLK-FB, thereby dynamically compensating for the propagation delay caused by environmental changes or aging of the isolation device. This avoids timing errors caused by delay fluctuations, ensuring that the data setup time and hold time always meet the timing requirements, thus ensuring the accuracy of the digital isolation system and improving the reliability of data transmission.
[0023] Other features and aspects of this application will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description
[0024] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this application together with the specification and serve to explain the principles of this application.
[0025] Figure 1 The circuit diagram shows an embodiment of the isolation device of this application;
[0026] Figure 2 This paper shows a circuit diagram of a synchronous clock control device according to an embodiment of the present application;
[0027] Figure 3 A flowchart illustrating a synchronous clock control device according to an embodiment of this application is shown. Detailed Implementation
[0028] Various exemplary embodiments, features, and aspects of this application will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.
[0029] It should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model or simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.
[0030] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this utility model, "a plurality of" means two or more, unless otherwise explicitly specified.
[0031] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.
[0032] Furthermore, to better illustrate this application, numerous specific details are provided in the following detailed embodiments. Those skilled in the art should understand that this application can be implemented without certain specific details. In some instances, methods, means, components, and circuits well-known to those skilled in the art have not been described in detail in order to highlight the main points of this application.
[0033] This application proposes a synchronous clock control device, such as... Figures 1 to 3 As shown, it includes: an FPGA chip 100, an ADC chip 200, an isolation device 300, and a data acquisition channel; the clock signal output terminal of the FPGA chip 100 is connected to the clock signal input terminal of the isolation device 300 via a first synchronous bus, and the isolated clock output terminal of the isolation device 300 is connected to the isolated clock input terminal of the ADC chip 200 via a second synchronous bus; the data output terminal of the ADC chip 200 is connected to the first data input terminal of the isolation device 300 via the second synchronous bus, and the first data output terminal of the isolation device 300 is connected to the first data input terminal of the FPGA chip 100 via the first synchronous bus; the data acquisition channel includes a first data acquisition channel and... The second sampling channel; the input terminal of the first sampling channel is electrically connected to the isolation clock output terminal of the isolation device 300, the output terminal of the first sampling channel is electrically connected to the first data input terminal of the isolation device 300, the input terminal of the second sampling channel is electrically connected to the first data output terminal of the isolation device 300, and the output terminal of the second sampling channel is connected to the second data input terminal (i.e., pin E10 of FPGA chip 100) of FPGA chip 100, so as to transmit the sampling clock isolated by the isolation device 300 to FPGA chip 100; wherein, FPGA chip 100 is provided with a trigger, which is suitable for sampling the data transmitted by ADC chip 200 using the sampling clock.
[0034] It should be noted here that the FPGA chip 100 is used to provide a reference clock source for the entire system and receive feedback signals. The input terminal of the first synchronous bus is electrically connected to the clock signal output terminal of the FPGA chip 100 (i.e., pin A8 of the FPGA chip 100), and the output terminal of the first synchronous bus is electrically connected to the clock signal input terminal of the isolation device 300 (i.e., pin VIA of the isolation device 300). The FPGA chip 100 transmits the generated clock signal FPGA-SCLK to the isolation device 300 through the first synchronous bus. The isolation device 300 is located between the FPGA chip 100 and the AD... Between the C chips 200, the electrical connection between the FPGA chip 100 and the ADC chip 200 is isolated, while signal transmission between the FPGA chip 100 and the ADC chip 200 is realized. The isolation device 300 electrically isolates the received clock signal FPGA-SCLK to form the clock signal ADC-SCLK. The input terminal of the second synchronous bus is electrically connected to the isolated clock output terminal (i.e., the VOA pin of the isolation device 300), and the output terminal of the second synchronous bus is connected to the isolated clock input terminal (i.e., the RDn pin of the ADC chip 200). The isolation device 300 transmits the isolated clock signal ADC-SCLK to the ADC chip 200 via the second synchronous bus. The ADC chip 200 is used to convert analog input signals to generate ADC-MISO data. The input terminal of the second synchronous bus is electrically connected to the data output terminal of the ADC chip 200 (i.e., the MISO pin of the ADC chip 200), and the output terminal of the second synchronous bus is electrically connected to the first data input terminal of the isolation device 300 (i.e., the VIF pin of the isolation device 300). The ADC chip 200 transmits the converted ADC-MISO data to the ADC chip 200 via the second synchronous bus. ISO data is transmitted to isolator 300 for isolation to form FPGA-MISO data; the input of the first synchronous bus is electrically connected to the first data output of isolator 300 (i.e., the VOF pin of isolator 300), and the output of the first synchronous bus is electrically connected to the first data input of FPGA chip 100 (i.e., the G14 pin of FPGA chip 100). Isolator 300 transmits the isolated FPGA-MISO data to FPGA chip 100 through the first synchronous bus. Isolator 300 has two VIF pins and two VOF pins respectively.
[0035] The first sampling channel is used to partially sample the clock signal ADC-SCLK output from the isolator 300 to the ADC chip 200 back to the isolator 300. This ensures that the clock signal ADC-SCLK and ADC-MISO data are transmitted in the same isolation path before being fed back to the FPGA chip 100, ensuring that their delay change trends are consistent and guaranteeing that the delay characteristics of the clock signal ADC-SCLK and ADC-MISO data are synchronized, avoiding timing mismatch caused by inconsistent delay changes. The isolator 300 electrically isolates the clock signal ADC-SCLK to form the sampling clock FPGA-SCLK-FB. The second sampling channel will sample the FPGA-SCLK-FB clock. The SCLK-FB is transmitted to the FPGA chip 100; the second sampling channel is used to transmit the sampling clock FPGA-SCLK-FB to the FPGA chip 100, thereby providing a precise time base for the data sampling of the trigger; the trigger uses the sampling clock FPGA_SCLK_FB to sample the FPGA-MISO data returned by the ADC chip 200. Since the sampling clock FPGA_SCLK_FB and the FPGA-MISO data have passed through the same isolation path, the relative timing relationship between the sampling clock FPGA_SCLK_FB and the FPGA-MISO data remains stable, ensuring that the setup time and hold time always meet the timing requirements.
[0036] This application establishes a sampling channel that feeds back the isolated sampling clock FPGA-SCLK-FB to the FPGA chip 100 to form a closed-loop control mechanism. The sampling channel ensures that the clock signal ADC-SCLK and ADC-MISO data are transmitted in the same isolation path, thereby enabling the FPGA chip 100 to track and dynamically adjust the isolation delay changes in real time. This eliminates the accumulated delay of the FPGA-MISO data during the isolation process. The trigger can sample the transmitted FPGA-MISO data based on the sampling clock FPGA-SCLK-FB, thereby dynamically compensating for the propagation delay of the isolation device 300 caused by environmental changes or aging. This avoids timing errors caused by delay fluctuations, ensuring that the data setup time and hold time always meet the timing requirements, thus ensuring the accuracy of the digital isolation system and improving the reliability of data transmission.
[0037] In one possible implementation, the data output terminal of the FPGA chip 100 is connected to the second data input terminal of the isolation device 300 via a first synchronization bus, and the data input terminal of the ADC chip 200 is connected to the second data output terminal of the isolation device 300 via a second synchronization bus.
[0038] It should be noted that the input of the first synchronous bus is electrically connected to the H14 pin of the FPGA chip 100 (i.e., the data output of the FPGA chip 100), and the output of the first synchronous bus is electrically connected to the VIC pin of the isolation device 300 (i.e., the second data input of the isolation device 300). The FPGA_MOSI data generated by the FPGA chip 100 is transmitted to the isolation device 300 through the first synchronous bus. The isolation device 300 performs electrical isolation on the received FPGA_MOSI data to form ADC_MOSI data, thereby completely isolating the power domain of the FPGA chip 100 from the power domain of the ADC chip 200, avoiding interference from the high-voltage domain from affecting the low-voltage domain chip. The input of the second synchronous bus is connected to the VOC pin of the isolation device 300 (i.e., the second data output of the isolation device 300), and the output of the second synchronous bus is connected to the MOSI pin of the ADC chip 200 (i.e., the data input of the ADC chip 200). The isolation device 300 transmits the electrically isolated ADC_MOSI data to the ADC chip 200 through the second synchronous bus.
[0039] In one possible implementation, the chip signal output of FPGA chip 100 is connected to the chip signal input of isolation device 300 via a first synchronization bus, and the chip signal input of ADC chip 200 is connected to the chip signal output of isolation device 300 via a second synchronization bus.
[0040] It should be noted that the input of the first synchronous bus is connected to the A9 pin of the FPGA chip 100 (i.e., the chip signal output of the FPGA chip 100), and the output of the first synchronous bus is connected to the VIB pin of the isolation device 300 (i.e., the chip signal input of the isolation device 300). The chip select signal FPGA_CS generated by the PGA chip is transmitted to the isolation device 300 through the first synchronous bus. The isolation device 300 electrically isolates the received chip select signal FPGA_CS to form the chip select signal ADC-CS. The input of the second synchronous bus is connected to the VOB pin of the isolation device 300 (i.e., the chip signal output of the isolation device 300), and the output of the second synchronous bus is connected to the CSn pin of the ADC chip 200 (i.e., the chip signal input of the ADC chip 200). The isolation device 300 transmits the electrically isolated chip select signal ADC-CS to the ADC chip.
[0041] In one possible implementation, the isolation device 300 is an optocoupler isolation device 300, a magnetic coupler isolation device 300, or a capacitive isolation device 300.
[0042] In one possible implementation, the input ground terminal and the output ground terminal of the isolator 300 are respectively grounded; the input ground terminal of the isolator 300 (i.e., the GND1 pin of the isolator 300) is usually connected to the primary side of the isolator 300 (i.e., the low-voltage side where the FPGA chip 100 is located), and the output ground terminal of the isolator 300 (i.e., the GND2 pin of the isolator 300) is connected to the secondary side (i.e., the high-voltage side or high-noise side where the ADC chip 200 is located). The two are grounded separately and independently, which physically cuts off the direct electrical connection between the primary side and the secondary side, avoids common-mode current interference caused by the potential difference between the two sides, and thus reduces interference to clock signals and data signals.
[0043] In one possible implementation, a first power supply and a second power supply are also included; the output terminal of the first power supply is electrically connected to the high-voltage side power supply terminal of the isolation device 300, and the output terminal of the second power supply is electrically connected to the low-voltage side power supply terminal of the isolation device 300.
[0044] It should be noted that the output of the first power supply is connected to the VDD1 pin of the isolation device 300 (i.e., the high-voltage side power supply of the isolation device 300), and the output of the second power supply is connected to the VDD2 pin of the isolation device 300 (i.e., the low-voltage side power supply of the isolation device 300). The first and second power supplies are used to provide different power requirements for the FPGA chip 100 and the ADC chip 200, respectively, so as to flexibly adapt to the voltage requirements of different devices. The first power supply supplies power to the primary side (i.e., the side connected to the FPGA chip 100), and the second power supply supplies power to the secondary side (i.e., the side connected to the ADC chip 200). The two operate independently and have no direct electrical connection, avoiding electrical coupling between the two power supplies through the power supply loop, ensuring the unified signal isolation and power isolation functions of the isolation device 300, thereby ensuring the normal operation of the isolation device 300.
[0045] In one possible implementation, a first packaged capacitor is also included; one end of the first packaged capacitor is connected to the high-voltage side power supply terminal of the isolation device 300, and the other end of the first packaged capacitor is grounded.
[0046] It should be noted that the first packaged capacitor is used to provide a stable and clean power supply voltage for the 300VDD1 pin of the isolation device, so as to prevent high-frequency noise from being coupled to the clock signal FPGA-SCLK transmission path of the primary side of the isolation device 300 through the first power supply loop, thus ensuring the timing stability of the clock signal FPGA-SCLK transmission between the primary side and the FPGA chip 100 and reducing sampling errors caused by power supply fluctuations.
[0047] In one possible implementation, a second packaged capacitor is also included; one end of the second packaged capacitor is connected to the low-voltage side power supply terminal of the isolation device 300, and the other end of the second packaged capacitor is grounded. It should be noted that the second packaged capacitor has the same configuration, function, and principle as the first packaged capacitor, which has been described in detail above and will not be repeated here.
[0048] In one possible implementation, the FPGA chip 100 is an existing model FMK230T8 chip, the ADC chip 200 is an existing model CM2248 chip, and the isolation device 300 is an existing model PAI162E30 chip.
[0049] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.
Claims
1. A synchronous clock control device, characterized in that, include: FPGA chip, ADC chip, isolation device and data acquisition channel; The clock signal output terminal of the FPGA chip is connected to the clock signal input terminal of the isolation device through a first synchronization bus, and the isolation clock output terminal of the isolation device is connected to the isolation clock input terminal of the ADC chip through a second synchronization bus. The data output terminal of the ADC chip is connected to the first data input terminal of the isolation device through the second synchronization bus, and the first data output terminal of the isolation device is connected to the first data input terminal of the FPGA chip through the first synchronization bus. The mining channel includes a first mining channel and a second mining channel; The input terminal of the first sampling channel is electrically connected to the isolation clock output terminal of the isolation device, the output terminal of the first sampling channel is electrically connected to the first data input terminal of the isolation device, the input terminal of the second sampling channel is electrically connected to the first data output terminal of the isolation device, and the output terminal of the second sampling channel is connected to the second data input terminal of the FPGA chip, so as to transmit the sampling clock isolated by the isolation device to the FPGA chip. The FPGA chip is equipped with a trigger, which is used to sample the data transmitted by the ADC chip using the sampling clock.
2. The synchronous clock control device according to claim 1, characterized in that, The data output terminal of the FPGA chip is connected to the second data input terminal of the isolation device via the first synchronization bus. The data input terminal of the ADC chip is connected to the second data output terminal of the isolation device via the second synchronization bus.
3. The synchronous clock control device according to claim 1, characterized in that, The chip signal output terminal of the FPGA chip is connected to the chip signal input terminal of the isolation device through the first synchronization bus. The chip signal input terminal of the ADC chip is connected to the chip signal output terminal of the isolation device through the second synchronization bus.
4. The synchronous clock control device according to claim 1, characterized in that, The isolation device is an optocoupler isolation device, a magnetic coupler isolation device, or a capacitive isolation device.
5. The synchronous clock control device according to claim 1, characterized in that, The input grounding terminal and the output grounding terminal of the isolation device are respectively grounded.
6. The synchronous clock control device according to claim 1, characterized in that, It also includes a first power supply and a second power supply; The output terminal of the first power supply is electrically connected to the high-voltage side power supply terminal of the isolation device, and the output terminal of the second power supply is electrically connected to the low-voltage side power supply terminal of the isolation device.
7. The synchronous clock control device according to claim 6, characterized in that, It also includes the first package capacitor; One end of the first encapsulated capacitor is connected to the high-voltage side power supply terminal of the isolation device, and the other end of the first encapsulated capacitor is grounded.
8. The synchronous clock control device according to claim 6, characterized in that, It also includes a second-package capacitor; One end of the second encapsulated capacitor is connected to the low-voltage side power supply terminal of the isolation device, and the other end of the second encapsulated capacitor is grounded.