Display panel and display device

Abstract

A display panel and a display device, the display panel comprising a substrate substrate, the substrate substrate comprising a driving chip area, the driving chip area comprising a connection pin area and a chip binding pin area; at least one repair pin located in the connection pin area; at least one repair line located in the non-display area, a first end of the at least one repair line being connected with a corresponding repair pin, a second end of the at least one repair line being connected with a corresponding data line through a welding spot; at least one repair test terminal located in the driving chip area and between the connection pin area and the chip binding pin area, the at least one repair test terminal being connected with a corresponding repair line through the at least one repair pin, the at least one repair test terminal being configured to provide an external test signal to the at least one repair line in a test stage.

Description

Technical Field

[0001] This article relates to the field of display technology, particularly display panels and display devices. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, and extremely fast response speed. With the continuous development of display technology, display devices using OLEDs as the light-emitting device and thin-film transistors (TFTs) for signal control have become the mainstream products in the display field. Utility Model Content

[0003] This disclosure provides a display panel and display device that enable testing of repair lines in the backplane (BP) process section.

[0004] This disclosure provides a display panel, including: a substrate, the substrate including a display area and a non-display area surrounding the display area, the non-display area including a bonding area located on one side of the display area, the bonding area including a driver chip area, the driver chip area including a connection pin area and a chip bonding pin area, the chip bonding pin area being located on the side of the connection pin area away from the display area;

[0005] Multiple sub-pixels and multiple data lines are located on one side of the substrate and in the display area, and the multiple sub-pixels and multiple data lines are electrically connected.

[0006] At least one repair pin is located in the connection pin area;

[0007] At least one repair line is located in the non-display area, the first end of the at least one repair line is connected to the corresponding repair pin, and the second end of the at least one repair line is connected to the corresponding data line through a solder joint;

[0008] At least one repair test terminal is located in the driver chip area and between the connection pin area and the chip bonding pin area. The at least one repair test terminal is connected to the corresponding repair line through the at least one repair pin. The at least one repair test terminal is configured to provide an external test signal to the at least one repair line during the test phase.

[0009] In an exemplary embodiment, the number of the at least one repair test terminal is multiple, the number of the at least one repair pin is multiple, and the multiple repair test terminals are connected one-to-one with the multiple repair pins.

[0010] In an exemplary embodiment, the number of the at least one repair test terminal is multiple, and the number of the at least one repair pin is multiple; the driver chip area also includes at least one repair multiplexing circuit, and one of the multiple repair test terminals is connected to at least two of the multiple repair pins through one of the at least one repair multiplexing circuit.

[0011] In an exemplary embodiment, the number of the at least one repair test terminal is multiple, and the number of the at least one repair pin is multiple; the driver chip area further includes at least one repair multiplexing circuit, and a portion of the multiple repair test terminals is connected to a portion of the multiple repair pins in a one-to-one correspondence; one of the repair test terminals in another portion of the multiple repair test terminals is connected to at least two repair pins in another portion of the multiple repair pins through one of the repair multiplexing circuits in the at least one repair multiplexing circuit.

[0012] In an exemplary embodiment, at least one virtual test terminal is also included, located between the connection pin area and the chip bonding pin area, wherein the at least one virtual test terminal is multiplexed as the at least one repair test terminal.

[0013] In an exemplary embodiment, the number of the at least one repair pin is multiple, and the solder joint includes a first solder joint; the at least one repair line includes a fan-out repair line, the first end of the fan-out repair line is connected to one of the repair pins of the multiple repair pins, the second end of the fan-out repair line is connected to a first solder joint, and the first solder joint is connected to the first end of one of the multiple data lines near the bonding area.

[0014] In an exemplary embodiment, the plurality of data lines extend along a second direction and are spaced apart along a first direction. The display panel has a center line extending along the second direction. The center line has mutually disconnected fan-out repair lines on opposite sides of the first direction. The first direction and the second direction intersect each other.

[0015] In an exemplary embodiment, the number of the at least one repair pin is multiple, and the solder joint includes a second solder joint; the at least one repair line includes an edge repair line, the first end of the edge repair line is connected to another repair pin among the multiple repair pins, the second end of the edge repair line is connected to a second solder joint, and the second solder joint is connected to the second end of another data line among the multiple data lines away from the bonding area.

[0016] In an exemplary embodiment, the plurality of data lines extend along a second direction and are spaced apart along a first direction. The display panel has a center line extending along the second direction. The center line has mutually disconnected edge repair lines on opposite sides of the first direction. The first direction and the second direction intersect each other.

[0017] In an exemplary embodiment, the connection pin area further includes a plurality of data pins, and the plurality of data lines are connected one-to-one with the plurality of data pins. The display panel further includes a plurality of data test units, which are located in the driver chip area between the connection pin area and the chip bonding pin area. One of the plurality of data test units is connected to one of the plurality of data pins. The data test unit is configured to provide an external test signal to the corresponding data line during the test phase.

[0018] In an exemplary embodiment, the plurality of data test units are electrically connected to the plurality of data pins one by one.

[0019] In an exemplary embodiment, the display panel further includes at least one data multiplexing circuit, and one of the plurality of data test units is connected to at least two of the plurality of data pins through one of the data multiplexing circuits.

[0020] In an exemplary embodiment, the display panel has a center line extending along a second direction, and the at least one repair pin is farther away from the center line in a first direction relative to the plurality of data pins, the first direction intersecting the second direction.

[0021] In an exemplary embodiment, the chip bonding pin area includes a plurality of chip bonding pins, and the connection pin area includes a plurality of connection pins, wherein the plurality of chip bonding pins and the plurality of connection pins are configured to be bonded and connected to the driver chip.

[0022] This disclosure also provides a display device, including the aforementioned display panel.

[0023] This embodiment of the display panel adds repair pins and repair test terminals in the driver chip area. In the backplane (BP) process segment of the display panel, the repair test signal can be transmitted to the repair line through the repair test terminals and repair pins to test the repair line and check for problems such as short circuits and open circuits. This ensures the yield of the display panel, prevents defective display panels from flowing into the next process segment, and reduces resource waste.

[0024] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the embodiments described in the description and the accompanying drawings. Attached Figure Description

[0025] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0026] Figure 1 This is a schematic diagram of the planar structure of the display panel according to an embodiment of the present disclosure;

[0027] Figure 2 This is a schematic diagram of a planar structure showing a broken data cable in the display panel according to an embodiment of the present disclosure;

[0028] Figure 3 This is a schematic diagram of a planar structure showing a broken data cable in the display panel according to an embodiment of the present disclosure;

[0029] Figure 4a This is a schematic diagram of a planar structure of a driver chip area and a bonding pin area in a display panel, provided by an embodiment of the present disclosure.

[0030] Figure 4b A schematic diagram of the planar structure of the driver chip area and the bonding pin area in another display panel provided in this embodiment of the present disclosure;

[0031] Figure 4c A schematic diagram of the planar structure of the driver chip area and the bonding pin area in another display panel provided in this embodiment of the present disclosure;

[0032] Figure 4d This is a schematic diagram of the planar structure of the driver chip area and the bonding pin area in another display panel provided in an embodiment of this disclosure. Detailed Implementation

[0033] This application describes several embodiments, but these descriptions are exemplary and not limiting, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0034] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application can also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this application can be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes can be made within the scope of the appended claims.

[0035] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that the method or process does not depend on the specific order of steps described herein. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims relating to the method and / or process should not be limited to the steps performed in the order written, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments disclosed herein.

[0036] One end of the repair line in the bonding area of ​​the relevant display panel is connected to the corresponding data line, and the other end of the repair line is directly connected to the pin in the bonding area. There is no test terminal in the bonding area for testing the repair line, so the repair line cannot be detected in the backplane (BP) process of the relevant display panel. This can easily lead to defective display panels flowing into the next process, wasting resources.

[0037] This disclosure provides a display panel, including: a substrate, the substrate including a display area and a non-display area surrounding the display area, the non-display area including a bonding area located on one side of the display area, the bonding area including a driver chip area, the driver chip area including a connection pin area and a chip bonding pin area, the chip bonding pin area being located on the side of the connection pin area away from the display area;

[0038] Multiple sub-pixels and multiple data lines are located on one side of the substrate and in the display area, and the multiple sub-pixels and multiple data lines are electrically connected.

[0039] At least one repair pin is located in the connection pin area;

[0040] At least one repair line is located in the non-display area, the first end of the at least one repair line is connected to the corresponding repair pin, and the second end of the at least one repair line is connected to the corresponding data line through a solder joint;

[0041] At least one repair test terminal is located in the driver chip area and between the connection pin area and the chip bonding pin area. The at least one repair test terminal is connected to the corresponding repair line through the at least one repair pin. The at least one repair test terminal is configured to provide an external test signal to the at least one repair line during the test phase.

[0042] The following examples illustrate the solution of this embodiment.

[0043] Figure 1 This is a schematic diagram of the planar structure of the display panel according to an embodiment of the present disclosure. In an exemplary embodiment, such as Figure 1As shown, in a plane parallel to the display panel, the display panel may include: a substrate; the substrate includes a display area 100 and non-display areas 200 located around the display area 100. The non-display areas 200 may include a bonding area 210 located on one side of the display area 100 in the second direction Y and edge areas located on other sides of the display area 100; the edge areas include a first border area 220 located on the side of the display area 100 away from the bonding area 210, and second border areas 230 and third border areas 240 located on opposite sides of the display area 100 in the first direction X. The second border areas 230 and 240 are both connected to the bonding area 210 at one end in the second direction Y, and both are connected to the first border area 220 at one end in the opposite direction of the second direction Y. For example, the bonding area 210 may be the bottom border of the display panel, the first border area 220 may be the top border of the display panel, the second border area 230 may be the left border of the display panel, and the third border area 240 may be the right border of the display panel. In this case, the first direction X and the second direction Y intersect each other; for example, the first direction X and the second direction Y are perpendicular to each other.

[0044] In an exemplary embodiment, the display area 100 may be a flat area, and a plurality of sub-pixels constituting a pixel array are disposed on one side of the display area 100 on the substrate. The plurality of sub-pixels may be configured to display dynamic images or still images. The display area 100 may be referred to as the active area. The display area 100 may be rectangular. However, this embodiment is not limited to this. For example, the display area may be other shapes such as circular or elliptical. In some examples, the display panel may be a flexible panel, and thus the display panel may be deformable, such as rollable, bent, folded, or rolled up.

[0045] In an exemplary embodiment, a sub-pixel may include a pixel circuit and a light-emitting element sequentially disposed on a substrate, the light-emitting element being electrically connected to the pixel circuit. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In the above circuit structures, T refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. The light-emitting element may be any of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a micro-LED (including mini-LED or micro-LED). For example, the light-emitting element may be an OLED, which, driven by its corresponding pixel circuit, can emit red, green, blue, or white light. The color of the light emitted by the light-emitting element can be determined as needed. In some examples, the light-emitting element may include an anode, a cathode, and an organic light-emitting layer located between the anode and cathode. The anode of the light-emitting element can be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

[0046] In an exemplary embodiment, a plurality of data lines 10 are provided on one side of the display area 100 of the substrate. The plurality of data lines 10 extend along the second direction Y and are arranged at intervals along the first direction X. Each data line 10 can be electrically connected to a plurality of sub-pixels and each data line 10 can be configured to provide data signals to the plurality of sub-pixels.

[0047] In an exemplary embodiment, the bonding region 210 of the substrate may include: a fan-out region 211, at least one driver chip region 212, and at least one bonding pin region 213 sequentially arranged along a direction away from the display region 100. The fan-out region 211 may have multiple data transmission lines 11, one end of which is connected to the driver chip in the driver chip region 212, and the other end of which is connected to the data line 10 of the display region 100 via a fan-out routing method. The driver chip region 212 may have a driver IC chip configured to connect to the multiple data transmission lines 11. In some embodiments, the driver chip may be a Touch and Display Driver Integration (TDDI) chip. The bonding pin region 213 may have multiple board bonding pins (PINs), which can be connected to the driver chip in the driver chip region 212 via multiple signal transmission lines 12, and are configured to be bonded to a flexible printed circuit board (FPC).

[0048] In an exemplary embodiment, the number of driver chip regions 212 in the bonding region 210 can be two. In some embodiments, the number of driver chip regions in the bonding region can also be one, three, four, etc., and this disclosure does not limit the number of such regions.

[0049] In an exemplary embodiment, the number of bonded pin areas 213 in the bonding region 210 can be two. In some embodiments, the number of bonded pin areas in the bonding region can also be one, three, four, etc., and this disclosure does not limit the number of such pin areas.

[0050] In an exemplary embodiment, the display panel has a center line O extending along a second direction Y, which divides the display panel into a left portion and a right portion. The left portion is the part of the display panel located on the side opposite to the first direction X of the center line O, and the right portion is the part of the display panel located on the side of the first direction X of the center line O.

[0051] In an exemplary embodiment, multiple data lines 10 are provided in the display areas of both the left and right sides of the display panel. For example, the multiple data lines 10 in the left and right sides are mirror images of each other about the center line O. At least one driver chip area 212 of the binding area 210 includes a first driver chip area 212-1 and a second driver chip area 212-2. Both the first driver chip area 212-1 and the second driver chip area 212-2 extend along a first direction X and are spaced apart along the first direction X. The first driver chip area 212-1 and the second driver chip area 212-2 are located on opposite sides of the center line O in the first direction X. The first driver chip area 212-1 is located in the left side of the display panel, and the second driver chip area 212-2 is located in the right side of the display panel. For example, the first driver chip area 212-1 and the second driver chip area 212-2 are mirror images of each other about the center line O.

[0052] In an exemplary embodiment, the first driver chip region 212-1 includes a connection pin region 31 and a chip bonding pin region 33 arranged sequentially along a direction away from the display area 100. The connection pin region 31 of the first driver chip region 212-1 includes a plurality of first connection pins spaced apart along a first direction X. The chip bonding pin region 33 of the first driver chip region 212-1 includes a plurality of first driver chip bonding pins spaced apart along a first direction X. The plurality of first driver chip bonding pins are located on the side of the plurality of first connection pins away from the display area. The first driver chip has a plurality of first connection electrodes and a plurality of second connection electrodes. The plurality of first connection electrodes are spaced apart along the first direction X, and the plurality of second connection electrodes are spaced apart along the first direction X. The plurality of first connection electrodes of the first driver chip are bonded to the plurality of first connection pins of the connection pin region, and the plurality of second connection electrodes of the first driver chip are bonded to the plurality of first driver chip bonding pins of the chip bonding pin region, so that the first driver chip is bonded to the first driver chip region 212-1. The first ends of the multiple data lines 10 on the left side extend to the fan-out area 211 on the left side and are connected to the multiple data transmission lines 11 in the fan-out area 211, for example, in a one-to-one correspondence. The multiple data transmission lines 11 are connected to the first driver chip in the first driver chip area 212-1, so that the data signal output by the first driver chip in the first driver chip area 212-1 is transmitted to the multiple data lines 10 on the left side through the multiple data transmission lines 11.

[0053] In an exemplary embodiment, the second driver chip region 212-2 includes a connection pin region 31 and a chip bonding pin region 33 arranged sequentially along a direction away from the display area 100. The connection pin region 31 of the second driver chip region 212-2 includes a plurality of second connection pins spaced apart along a first direction X. The chip bonding pin region 33 of the second driver chip region 212-2 includes a plurality of second driver chip bonding pins spaced apart along a first direction X. The plurality of second driver chip bonding pins are located on the side of the plurality of second connection pins away from the display area. The second driver chip has a plurality of third connection electrodes and a plurality of fourth connection electrodes. The plurality of third connection electrodes are spaced apart along the first direction X, and the plurality of fourth connection electrodes are spaced apart along the first direction X. The plurality of third connection electrodes and the plurality of fourth connection electrodes are arranged along a second direction Y. The plurality of third connection electrodes of the second driver chip are bonded to the plurality of second connection pins of the connection pin region, and the plurality of fourth connection electrodes of the second driver chip are bonded to the plurality of second driver chip bonding pins of the chip bonding pin region, so that the second driver chip is bonded to the second driver chip region 212-2. The first ends of the multiple data lines 10 on the right side extend to the fan-out area 211 on the right side and are connected to the multiple data transmission lines 11 in the fan-out area 211, for example, in a one-to-one correspondence. The multiple data transmission lines 11 are connected to the second driver chip in the second driver chip area 212-2, so that the data signal output by the second driver chip in the second driver chip area 212-2 is transmitted to the multiple data lines 10 on the right side through the multiple data transmission lines 11.

[0054] In an exemplary embodiment, at least one bonding pin area 213 of the bonding region 210 includes a first bonding pin area 213-1 and a second bonding pin area 213-2. Both the first bonding pin area 213-1 and the second bonding pin area 213-2 extend along a first direction X and are spaced apart along the first direction X. The first bonding pin area 213-1 and the second bonding pin area 213-2 are located on opposite sides of the center line O in the first direction X. The first bonding pin area 213-1 is located on the left side of the display panel, and the second bonding pin area 213-2 is located on the right side of the display panel. For example, the first bonding pin area 213-1 and the second bonding pin area 213-2 are mirror images of each other with the center line O as the axis. The pins in the first bonding pin area 213-1 are connected to a first driver chip in the first driver chip area 212-1 via multiple signal transmission lines 12, and the pins in the second bonding pin area 213-2 are connected to a second driver chip in the second driver chip area 212-2 via multiple signal transmission lines 12.

[0055] In an exemplary embodiment, the non-display area 200 of the display panel is provided with at least one repair line, and the driver chip area 212 is provided with multiple repair pins. The first end of the at least one repair line is connected to the corresponding repair pin in the driver chip area 212, and the second end of the at least one repair line is connected to the corresponding data line 10 through a solder joint. The repair line is configured to repair the data line 10 that has a break, so that the data signal can be transmitted to the data line 10 that has a break through the repair line.

[0056] In an exemplary embodiment, at least one repair line may include a fan-out repair line 21. The fan-out repair line 21 is located in the fan-out region 211 of the bonding region 210. The first end of the fan-out repair line 21 is connected to the corresponding repair pin in the driver chip region 212, and the first end of the fan-out repair line 21 is located on the side of the plurality of data transmission lines 11 away from the center line O in the first direction X. The second end of the fan-out repair line 21 may be connected to the first end of the corresponding data line 10 near the bonding region 210. The second end of the fan-out repair line 21 is connected to a first solder joint 13-1, and the first solder joint 13-1 is connected to the first end of one of the plurality of data lines 10. When the path for transmitting data signals to the data line 10 by the driver chip in the driver chip region 212, such as the first driver chip and / or the second driver chip, is interrupted, the fan-out repair line 21 is configured to be electrically connected to the first end of the interrupted data line 10 through the first solder joint 13-1, so that the data signal can be transmitted to the first end of the interrupted data line 10 through the fan-out repair line 21.

[0057] In an exemplary embodiment, a first fan-out repair line 21-1 is provided in the fan-out area 211 on the left side of the display panel, and a second fan-out repair line 21-2 is provided in the fan-out area 211 on the right side of the display panel. The first fan-out repair line 21-1 and the second fan-out repair line 21-2 are located on opposite sides of the center line O in the first direction X. For example, the first fan-out repair line 21-1 and the second fan-out repair line 21-2 are mirror images of each other with the center line O as the axis, and the first fan-out repair line 21-1 and the second fan-out repair line 21-2 are disconnected from each other. The first end of the first fan-out repair line 21-1 is connected to the corresponding repair pin in the first driver chip area 212-1, and the second end of the first fan-out repair line 21-1 is connected to the first end of the corresponding data line 10 located on the left side. The second fan-out repair line 21-2 is located in the fan-out area 211 on the right side. The first end of the second fan-out repair line 21-2 is connected to the corresponding repair pin in the second driver chip area 212-2, and the second end of the second fan-out repair line 21-2 is connected to the first end of the corresponding data line 10 located on the right side.

[0058] In an exemplary embodiment, at least one repair line may include an edge repair line 22. The first end of the edge repair line 22 is connected to a corresponding repair pin in the driver chip area 212, and the first end of the edge repair line 22 is located on the side of the fan-out repair line 21 away from the center line O in the first direction X. The second end of the edge repair line 22 extends to the first border area 220 and is connected to the second end of the corresponding data line 10 away from the bonding area 210. The second end of the edge repair line 22 is connected to a second solder joint 13-2, which is connected to the second end of one of the multiple data lines 10. When a break occurs in the path of the driver chip in the driver chip area 212, such as the first driver chip and / or the second driver chip, transmitting data signals to the data line 10, the edge repair line 22 is configured to be electrically connected to the second end of the broken data line 10 via the second solder joint 13-2, allowing the data signal to be transmitted through the edge repair line 22 to the second end of the broken data line 10.

[0059] In an exemplary embodiment, a first edge repair line 22-1 is provided in the non-display area 200 on the left side of the display panel, and a second edge repair line 22-2 is provided in the non-display area 200 on the right side of the display panel. The first edge repair line 22-1 and the second edge repair line 22-2 are located on opposite sides of the center line O in the first direction X, and are mirror images of each other with the center line O as the axis, and are disconnected from each other. The first end of the first edge repair line 22-1 is connected to the corresponding repair pin in the first driver chip area 212-1, and the second end of the first edge repair line 22-1 passes sequentially through the fan-out area 211 and the second frame area 230 of the left side, extending to the first frame area 220 of the left side, and the second end of the first edge repair line 22-1 is connected to the second end of the corresponding data line 10 located on the left side. The first end of the second edge repair line 22-2 is connected to the corresponding repair pin in the second driver chip area 212-2. The second end of the second edge repair line 22-2 passes through the fan-out area 211 and the third border area 240 of the right side in sequence, and extends to the first border area 220 of the right side. The second edge repair line 22-2 is connected to the second end of the corresponding data line 10 located in the right side.

[0060] Figure 2 This is a schematic diagram of a planar structure showing a broken data cable in a display panel according to an embodiment of this disclosure. In an exemplary embodiment, such as... Figure 2As shown, in a plane parallel to the display panel, when a data line 10 in the display area on the left side of the display panel experiences a data open (DO), the first solder joint 13-1 connected to the first end of the data line 10 with the DO is soldered, and the second solder joint 13-2 connected to the second end of the data line 10 with the DO is soldered, so that the first end of the data line 10 is electrically connected to the first fan-out repair line 21-1, and the second end of the data line 10 is electrically connected to the first edge repair line 22-1. The data signal output by the first driver chip in the first driver chip area 212-1 can be transmitted to the data line 10 with the DO through the first fan-out repair line 21-1 and the first edge repair line 22-1 respectively, thereby repairing the data line 10 with the DO.

[0061] Figure 3 This is a schematic diagram of a planar structure showing a broken data cable in a display panel according to an embodiment of this disclosure. In an exemplary embodiment, such as... Figure 3 As shown, in a plane parallel to the display panel, when the data line 10 of the display area on the left side of the display panel experiences an open circuit (LO) at the data transmission line 11 of the fan-out area 211, i.e., a lead open circuit (LO), the first solder joint 13-1 connected to the first end of the data line 10 with the open circuit (LO) is soldered, so that the first end of the data line 10 is electrically connected to the first fan-out repair line 21-1. The data signal output by the first driver chip area 212-1 can be transmitted to the data line 10 with the open circuit (DO) through the first fan-out repair line 21-1, thereby repairing the data line 10 with the open circuit (DO). Alternatively, the second solder joint 13-2 connected to the second end of the data line 10 with the open circuit (LO) can be soldered to make the second end of the data line 10 electrically connected to the first edge repair line 22-1. The data signal output by the first driver chip in the first driver chip area 212-1 can be transmitted to the data line 10 with the open circuit (DO) through the first edge repair line 22-1, thereby repairing the data line 10 with the open circuit (DO).

[0062] The number of repair lines on the display panel in this embodiment depends on the number of repair channels supported by the driver circuit (Driver IC) in the driver chip area 212. The more repair channels there are, the more repair lines are set on the display panel.

[0063] Figure 4a This is a schematic diagram of a planar structure of a driver chip area and a bonding pin area in a display panel, provided as an embodiment of this disclosure. Figure 4a It indicated Figure 1 A magnified view of point a. In an exemplary embodiment, such as Figure 4a As shown, in a plane parallel to the display panel, the driver chip area 212 includes a connection pin area 31, an array test unit area 32, and a chip bonding pin area 33 arranged sequentially along a direction away from the display area 100. The array test unit area 32 is located between the connection pin area 31 and the chip bonding pin area 33. The connection pin area 31 includes multiple connection pins, including multiple data pins 31-1 and multiple repair pins 31-2. The multiple data pins 31-1 are arranged at intervals along a first direction X. The first end of the multiple data pins 31-1 is connected to multiple data transmission lines 11 in a one-to-one correspondence. The second end of the multiple data pins 31-1 is electrically connected to multiple data test units 32-1 of the array test unit area 32 in a one-to-one correspondence. The multiple data pins 31-1 are configured to transmit the external test signals provided by the array test unit area 32 to the data lines. Multiple repair pins 31-2 are arranged at intervals along a first direction X, and are located on the side of multiple data pins 31-1 away from the center line O in the first direction X. The first end of at least one of the multiple repair pins 31-2 is connected to the fan-out repair line 21 in a one-to-one correspondence. The first end of at least one of the multiple repair pins 31-2 is connected to the edge repair line 22 in a one-to-one correspondence. The second end of the multiple repair pins 31-2 is connected to the multiple repair test units 32-2 of the array test unit area 32 in a one-to-one correspondence. The multiple repair pins 31-2 are configured to transmit the external test signal provided by the repair test unit 32-2 to the fan-out repair line 21 and the edge repair line 22.

[0064] In an exemplary embodiment, the array test unit area 32 includes at least a plurality of data test terminals 32-1 and a plurality of repair test terminals 32-2. The plurality of data test terminals 32-1 are located in the driver chip area 212 between the connection pin area 31 and the chip bonding pin area 33. The plurality of data test terminals 32-1 are arranged at intervals along a first direction X. The plurality of data test terminals 32-1 are connected one-to-one with the plurality of data pins 31-1. The plurality of data test terminals 32-1 are configured to provide an external test signal to at least one data line during the test phase, thereby testing the data line to check for short circuits, open circuits, or other problems. Multiple repair test terminals 32-2 are located in the driver chip area 212 between the connection pin area 31 and the chip bonding pin area 33. The multiple repair test terminals 32-2 are arranged at intervals along the first direction X and are located on the side of the multiple data test terminals 32-1 away from the center line O in the first direction X. The multiple repair test terminals 32-2 are connected to the multiple repair pins 31-2 one by one. The multiple repair test terminals 32-2 are configured to provide external test signals to at least one fan-out repair line 21 and at least one edge repair line 22 during the test phase, so as to test the fan-out repair line 21 and the edge repair line 22 to check for short circuits, open circuits and other problems.

[0065] In an exemplary embodiment, the chip bonding pin area 33 includes a plurality of chip bonding pins 33-1, which are arranged at intervals along a first direction X, and the plurality of chip bonding pins 33-1 and a plurality of connection pins are configured to bond and connect with a driver chip.

[0066] In an exemplary embodiment, the bonding pin area 213 may be provided with a plurality of circuit board bonding pins 34, which are arranged at intervals along a first direction X. The plurality of circuit board bonding pins 34 are connected to the driver chip of the driver chip area 212 through the signal transmission line 12, and the plurality of circuit board bonding pins 34 are configured to be bonded to a flexible circuit board (FPC).

[0067] In this embodiment of the display panel, a repair pin 31-2 and a repair test terminal 32-2 are added to the driver chip area 212. In the backplane (BP) process section of the display panel, external test signals can be transmitted to the repair line through the repair test terminal 32-2 and the repair pin 31-2 to test the repair line and check for problems such as short circuits and open circuits. This ensures the yield of the display panel, prevents defective display panels from flowing into the next process section, and reduces resource waste.

[0068] In an exemplary embodiment, the array test unit area 32 further includes a plurality of virtual test terminals, including a first virtual test terminal located in the first driver chip area 212-1 and a second virtual test terminal located in the second driver chip area 212-2. The first virtual test terminal is located between the connection pin area 31 and the chip bonding pin area 33 in the first driver chip area 212-1. There can be multiple first virtual test terminals, which are arranged at intervals along a first direction X and are located on the side of the plurality of data test terminals 32-1 in the first driver chip area 212-1 away from the center line O. At least one first virtual test terminal is reused as a repair test terminal 32-2, thereby eliminating the need to add new test terminals, simplifying the process, and reducing costs. The second virtual test terminal is located between the connection pin area 31 and the chip bonding pin area 33 in the second driver chip area 212-2. There can be multiple second virtual test terminals. Multiple second virtual test terminals are arranged at intervals along the first direction X and are located on the side of the multiple data test terminals 32-1 in the second driver chip area 212-2 away from the center line O in the first direction X. At least one second virtual test terminal is reused as a repair test terminal 32-2, so that no new test terminals need to be added, simplifying the process and reducing costs.

[0069] Figure 4b This is a schematic diagram of the planar structure of the driver chip area and the bonding pin area in another display panel provided in an embodiment of this disclosure. Figure 4bAs shown, the main structure of the display panel in this embodiment is similar to... Figure 4a The main structure of the display panel in the illustrated embodiment is basically the same. The difference is that the driver chip area 212 of the display panel in this embodiment also includes at least one data multiplexing circuit 41. The at least one data multiplexing circuit 41 is arranged at intervals along the first direction X. The at least one data multiplexing circuit 41 is located between the connection pin area 31 and the array test unit area 32. The first end of the data multiplexing circuit 41 can be connected to the second end of n data pins 31-1, where n is an integer greater than or equal to 2. The second end of the data multiplexing circuit 41 can be connected to a data test unit 32-1. The data multiplexing circuit 41 can be configured such that a data test unit 32-1 provides external test signals to the n data transmission lines 11.

[0070] Figure 4c This is a schematic diagram of the planar structure of the driver chip area and the bonding pin area in another display panel provided in an embodiment of this disclosure. Figure 4c As shown, the main structure of the display panel in this embodiment is similar to... Figure 4b The main structure of the display panel in the illustrated embodiment is basically the same. The difference is that the driver chip area 212 of the display panel in this embodiment also includes at least one repair multiplexing circuit 42. The at least one repair multiplexing circuit 42 is arranged at intervals along the first direction X. The at least one repair multiplexing circuit 42 is located between the connection pin area 31 and the array test unit area 32, and is located on the side of the data multiplexing circuit 41 away from the center line O in the first direction X. The first end of the repair multiplexing circuit 42 can be connected to the second end of m repair pins 31-2, where m is an integer greater than or equal to 2. For example, the first end of the repair multiplexing circuit 42 can be connected to multiple repair pins 31-2, and the multiple repair pins 31-2 are connected to the corresponding fan-out repair line 21 and edge repair line 22. The second end of the repair multiplexing circuit 42 can be connected to a repair test unit 32-2. The repair multiplexing circuit 42 can be configured such that the repair test unit 32-2 provides external test signals to the m repair lines.

[0071] Figure 4d This is a schematic diagram of the planar structure of the driver chip area and the bonding pin area in another display panel provided in an embodiment of this disclosure. Figure 4d As shown, the main structure of the display panel in this embodiment is similar to... Figure 4cThe main structure of the display panel in the illustrated embodiment is basically the same. The difference is that the first driver chip area 212-1 of the display panel in this embodiment is provided with at least one repair multiplexing circuit 42. One repair test unit 32-2 in the first driver chip area 212-1 is connected to m repair pins 31-2 through one repair multiplexing circuit 42, where m is an integer greater than or equal to 2. The second driver chip area 212-2 is not provided with a repair multiplexing circuit 42. At least two repair test units 32-2 in the second driver chip area 212-2 are connected to at least two repair pins 31-2 in a one-to-one correspondence.

[0072] This embodiment also provides a display device, including the display panel of the foregoing embodiments. In some examples, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator, or it can be a product or component with touch and display functions.

[0073] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0074] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include at least one of those features.

[0075] In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.

[0076] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," "fixing," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0077] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0078] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0079] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A display panel, characterized in that, include: A substrate, the substrate including a display area and a non-display area surrounding the display area, the non-display area including a bonding area located on one side of the display area, the bonding area including a driver chip area, the driver chip area including a connection pin area and a chip bonding pin area, the chip bonding pin area being located on the side of the connection pin area away from the display area; Multiple sub-pixels and multiple data lines are located on one side of the substrate and in the display area, and the multiple sub-pixels and multiple data lines are electrically connected. At least one repair pin is located in the connection pin area; At least one repair line is located in the non-display area, the first end of the at least one repair line is connected to the corresponding repair pin, and the second end of the at least one repair line is connected to the corresponding data line through a solder joint; At least one repair test terminal is located in the driver chip area and between the connection pin area and the chip bonding pin area. The at least one repair test terminal is connected to the corresponding repair line through the at least one repair pin. The at least one repair test terminal is configured to provide an external test signal to the at least one repair line during the test phase.

2. The display panel according to claim 1, characterized in that, The number of the at least one repair test terminal is multiple, the number of the at least one repair pin is multiple, and the multiple repair test terminals are connected one-to-one with the multiple repair pins.

3. The display panel according to claim 1, characterized in that, The number of the at least one repair test terminal is multiple, and the number of the at least one repair pin is multiple; the driver chip area also includes at least one repair multiplexing circuit, and one of the multiple repair test terminals is connected to at least two of the multiple repair pins through one of the at least one repair multiplexing circuit.

4. The display panel according to claim 1, characterized in that, The number of the at least one repair test terminal is multiple, and the number of the at least one repair pin is multiple; the driver chip area also includes at least one repair multiplexing circuit, and a portion of the multiple repair test terminals is connected to a portion of the multiple repair pins in a one-to-one correspondence; one of the repair test terminals in another portion of the multiple repair test terminals is connected to at least two repair pins in another portion of the multiple repair pins through one of the repair multiplexing circuits in the at least one repair multiplexing circuit.

5. The display panel according to claim 1, characterized in that, It also includes at least one virtual test terminal located between the connection pin area and the chip bonding pin area, wherein the at least one virtual test terminal is multiplexed as the at least one repair test terminal.

6. The display panel according to any one of claims 1 to 5, characterized in that, The number of the at least one repair pin is multiple, and the solder joint includes a first solder joint; the at least one repair line includes a fan-out repair line, the first end of the fan-out repair line is connected to one of the multiple repair pins, the second end of the fan-out repair line is connected to a first solder joint, and the first solder joint is connected to the first end of one of the multiple data lines near the bonding area.

7. The display panel according to claim 6, characterized in that, The multiple data lines extend along the second direction and are spaced apart along the first direction. The display panel has a center line extending along the second direction. The center line has mutually disconnected fan-out repair lines on opposite sides of the first direction. The first direction and the second direction intersect each other.

8. The display panel according to any one of claims 1 to 5, characterized in that, The number of the at least one repair pin is multiple, and the solder joint includes a second solder joint; the at least one repair line includes an edge repair line, the first end of the edge repair line is connected to another repair pin among the multiple repair pins, the second end of the edge repair line is connected to a second solder joint, and the second solder joint is connected to the second end of another data line among the multiple data lines away from the bonding area.

9. The display panel according to claim 8, characterized in that, The multiple data lines extend along the second direction and are spaced apart along the first direction. The display panel has a center line extending along the second direction. The center line has mutually disconnected edge repair lines on opposite sides of the first direction. The first direction and the second direction intersect each other.

10. The display panel according to any one of claims 1 to 5, characterized in that, The connection pin area also includes multiple data pins, and the multiple data lines are connected to the multiple data pins one by one. The display panel also includes multiple data test units, which are located in the driver chip area between the connection pin area and the chip bonding pin area. One of the multiple data test units is connected to one of the multiple data pins. The data test unit is configured to provide an external test signal to the corresponding data line during the test phase.

11. The display panel according to claim 10, characterized in that, The plurality of data test units are electrically connected to the plurality of data pins one by one.

12. The display panel according to claim 10, characterized in that, The display panel further includes at least one data multiplexing circuit, and one of the multiple data test units is connected to at least two of the multiple data pins through one of the data multiplexing circuits.

13. The display panel according to claim 10, characterized in that, The display panel has a center line extending along a second direction, and the at least one repair pin is farther away from the center line in a first direction than the plurality of data pins, the first direction intersecting the second direction.

14. The display panel according to any one of claims 1 to 5, characterized in that, The chip bonding pin area includes multiple chip bonding pins, and the connection pin area includes multiple connection pins. The multiple chip bonding pins and the multiple connection pins are configured to be bonded and connected to the driver chip.

15. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 14.

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