A video signal splicing circuit and display device

Abstract

This utility model discloses a video signal splicing circuit and a display device. The video signal splicing circuit includes: a control module, used to split an original video signal of a first resolution into a first video signal of a second resolution and a second video signal of a second resolution; the second resolution is half of the first resolution; a data conversion module, connected to the control module, wherein the data conversion amount of the data conversion module matches the data amount of the first video signal and the second video signal, used to receive the first video signal and convert it into a first logic level signal, and also used to receive the second video signal and convert it into a second logic level signal; and a signal synthesis module, connected to the data conversion module, used to synthesize the first logic level signal and the second logic level signal into a display video signal of the first resolution, and transmit it to the display module for image display. This utility model has a low cost and achieves high-resolution image display.

Description

Technical Field

[0001] This utility model relates to the field of display device technology, and in particular to a video signal splicing circuit and display device. Background Technology

[0002] As the resolution of display devices continues to increase, the amount of data in video signals also continues to grow. Some video signal input interfaces may be unable to directly receive high-resolution video signals, requiring the replacement of new input interfaces for data transmission. Furthermore, due to the increase in data volume, subsequent data conversion of video signals also requires higher bandwidth. Therefore, existing display devices cannot achieve high-resolution image display at low cost. Utility Model Content

[0003] This invention provides a video signal splicing circuit and a display device to solve the problem that display devices cannot achieve high-resolution image display at low cost.

[0004] According to one aspect of the present invention, a video signal splicing circuit is provided, comprising:

[0005] A control module is used to divide the original video signal at a first resolution into a first video signal at a second resolution and a second video signal at a second resolution; the second resolution is half of the first resolution.

[0006] A data conversion module is connected to the control module. The data conversion amount of the data conversion module is matched with the data amount of the first video signal and the second video signal. It is used to receive the first video signal and convert it into a first logic level signal, and also to receive the second video signal and convert it into a second logic level signal.

[0007] The signal synthesis module, connected to the data conversion module, is used to synthesize the first logic level signal and the second logic level signal into a display video signal with a first resolution, and transmit it to the display module for image display.

[0008] Optionally, the data conversion module includes:

[0009] A first data conversion unit, the input interface of which is connected to the control module, and the output interface of which is connected to the signal synthesis module;

[0010] The second data conversion unit has an input interface connected to the control module and an output interface connected to the signal synthesis module.

[0011] The first data conversion unit and the second data conversion unit have the same structure.

[0012] Optionally, the input interface of the first data conversion unit and the input interface of the second data conversion unit are both HDMI 2.0 interfaces.

[0013] Optionally, both the first data conversion unit and the second data conversion unit include: a data conversion chip connected to the control module and the signal synthesis module, used to receive the first video signal and convert it into the first logic level signal, or used to receive the second video signal and convert it into the second logic level signal.

[0014] Optionally, the first data conversion unit and the second data conversion unit further include: a connection detection circuit;

[0015] The connection detection circuit is connected between the control module and the data conversion chip, and the data conversion chip is used to output a hot-plug detection signal to the control module through the connection detection circuit.

[0016] Optionally, the first data conversion unit and the second data conversion unit further include: a level matching circuit;

[0017] The level matching circuit is connected between the control module and the data conversion chip. The control module is also used to output resolution data information to the data conversion chip through the level matching circuit.

[0018] Optionally, the control module includes: at least one first data transmission chip and at least one second data transmission chip;

[0019] The first data transmission chip is connected to the data conversion chip and is used to transmit the first video signal or the second video signal to the data conversion chip.

[0020] The first data transmission chip is also connected to the connection detection circuit for receiving the hot-plug detection signal;

[0021] The second data transmission chip is connected to the level matching circuit and is used to transmit the resolution data information to the level matching circuit.

[0022] Optionally, the first resolution is 8K and the second resolution is 4K.

[0023] Optionally, both the first logic level signal and the second logic level signal are of the type of TTL signal.

[0024] According to another aspect of the present invention, a display device is provided, comprising: a display module and a video signal splicing circuit as described in any embodiment of the present invention.

[0025] This embodiment of the invention, through the inclusion of a control module, divides the original video signal at a first resolution into a first video signal and a second video signal at a second resolution. A data conversion module processes the lower-resolution video signal, ensuring its capacity to receive and process data matches the data volume of the second-resolution signal. Furthermore, a signal synthesis module combines the first and second logic level signals, converting the low-resolution signal back to a high-resolution signal, which is then displayed in high resolution by a display module. This invention features a simple structure and achieves high-resolution display without requiring a higher-specification data conversion module, resulting in lower costs.

[0026] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this utility model, nor is it intended to limit the scope of this utility model. Other features of this utility model will become readily apparent from the following description. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a schematic diagram of a video signal splicing circuit according to an embodiment of the present utility model;

[0029] Figure 2 This is a schematic diagram of another video signal splicing circuit provided according to an embodiment of the present utility model;

[0030] Figure 3 This is a schematic diagram of the structure of a first data transmission chip according to an embodiment of the present utility model;

[0031] Figure 4 This is a schematic diagram of the structure of a second data transmission chip according to an embodiment of the present utility model;

[0032] Figure 5 This is a schematic diagram of the structure of the first sub-chip of a data conversion chip according to an embodiment of the present invention;

[0033] Figure 6 This is a schematic diagram of the structure of the second sub-chip of a data conversion chip according to an embodiment of the present invention;

[0034] Figure 7This is a schematic diagram of a connection detection circuit according to an embodiment of the present utility model;

[0035] Figure 8 This is a schematic diagram of a level matching circuit provided according to an embodiment of the present utility model. Detailed Implementation

[0036] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0037] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the utility model described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0038] This utility model embodiment provides a video signal splicing circuit. Figure 1 This is a schematic diagram of a video signal splicing circuit provided in an embodiment of the present invention. (Reference) Figure 1 The video signal splicing circuit 10 includes a control module 1, a data conversion module 2, and a signal synthesis module 3. The control module 1 is used to split the original video signal at a first resolution into a first video signal at a second resolution and a second video signal at a second resolution; the second resolution is half of the first resolution. The data conversion module 2 is connected to the control module 1, and the data conversion amount of the data conversion module 2 matches the data amount of the first and second video signals. It is used to receive the first video signal and convert it into a first logic level signal, and also to receive the second video signal and convert it into a second logic level signal. The signal synthesis module 3 is connected to the data conversion module 2 and is used to synthesize the first and second logic level signals into a display video signal at the first resolution, and transmit it to the display module 4 for image display.

[0039] Because the data conversion module 2 has a limited data capacity, directly transmitting the original video signal at the first resolution to it would be insufficient in terms of receiving and processing capabilities. Therefore, the control module 1 can divide the original video signal at the first resolution into a first video signal at a second resolution and a second video signal at a second resolution. This effectively divides the display of the original video signal into two equal parts, reducing its resolution and data volume to half that of the original video signal. The data conversion module 2 can be used to convert the first video signal at the second resolution and the second video signal at the second resolution. For example, the first and second video signals can be 4K resolution video signals with a 60Hz refresh rate.

[0040] By dividing the high-resolution original video signal into a lower-resolution first video signal and a second video signal, the amount of data received by the data conversion module 2 is halved. Since the amount of data converted by the data conversion module 2 matches the amount of data in the first video signal and the second video signal, the data conversion module 2 can process the first video signal and the second video signal better and convert them into a first logic level signal and a second logic level signal.

[0041] The signal synthesis module 3 is used to splice the first logic level signal and the second logic level signal together so that the first logic level signal and the second logic level signal can be synthesized into a display video signal with a first resolution. For example, the display video signal can be an 8K resolution video signal with a 30Hz refresh rate.

[0042] This embodiment of the invention, through the inclusion of a control module, divides the original video signal at a first resolution into a first video signal and a second video signal at a second resolution. A data conversion module processes the lower-resolution video signal, ensuring its capacity to receive and process data matches the data volume of the second-resolution signal. Furthermore, a signal synthesis module combines the first and second logic level signals, converting the low-resolution signal back to a high-resolution signal, which is then displayed in high resolution by a display module. This invention features a simple structure and achieves high-resolution display without requiring a higher-specification data conversion module, resulting in lower costs.

[0043] Figure 2 A schematic diagram of another video signal splicing circuit provided in an embodiment of this utility model. (Reference) Figure 2Based on the above embodiments, optionally, the data conversion module includes: a first data conversion unit 21 and a second data conversion unit 22. The input interface of the first data conversion unit 21 is connected to the control module 1, and the output interface of the first data conversion unit 21 is connected to the signal synthesis module 3. The input interface of the second data conversion unit 22 is connected to the control module 1, and the output interface of the second data conversion unit 22 is connected to the signal synthesis module 3. The first data conversion unit 21 and the second data conversion unit 22 have the same structure.

[0044] Optionally, the input interface of the first data conversion unit 21 and the input interface of the second data conversion unit 22 are both HDMI 2.0 interfaces.

[0045] The HDMI 2.0 interface supports a maximum resolution of 4K for data transmission, but it cannot meet the transmission requirements for application scenarios with resolutions exceeding 4K. Upgrading the HDMI 2.0 interface to the HDMI 2.1 interface would place high demands on the bandwidth of the back-end conversion chip.

[0046] The amount of data that both the first data conversion unit 21 and the second data conversion unit 22 can process is sufficient to meet the data volume requirements of the first video signal and the second video signal. This invention, by setting up a first data conversion unit 21 and a second data conversion unit 22, divides the original 8K resolution video signal into a first video signal and a second video signal with 4K resolution. This allows the first data conversion unit 21 to receive and process the 4K resolution first video signal, and the second data conversion unit 22 to receive and process the 4K resolution second video signal, converting them respectively into first logic level signals and second logic level signals.

[0047] Optionally, the type of the first logic level signal and the type of the second logic level signal are both TTL (Transistor-Transistor Logic) signals.

[0048] This embodiment of the invention establishes a first data conversion unit and a second data conversion unit, uses two HDMI 2.0 interfaces to transmit audio and video data, and employs a signal synthesis module to splice the first and second logic level signals, combining the two images into a single display. This elevates the two 4K resolution video signals to a single 8K resolution display video signal. Compared to a single HDMI 2.0 interface, this represents a significant increase in bandwidth transmission; compared to a single HDMI 2.1 interface, it offers substantial advantages in cost and ease of use.

[0049] Figure 3This is a schematic diagram of the structure of a first data transmission chip provided in an embodiment of the present invention. Figure 4 This is a schematic diagram of the structure of a second data transmission chip provided in an embodiment of the present invention. (In conjunction with...) Figures 2 to 4 Based on the above embodiments, optionally, the control module 1 includes: at least one first data transmission chip 11 and at least one second data transmission chip 12. The first data transmission chip 11 is connected to the data conversion chip and is used to transmit a first video signal or a second video signal to the data conversion chip. The first data transmission chip 11 is also connected to a connection detection circuit and is used to receive a hot-plug detection signal. The second data transmission chip 12 is connected to a level matching circuit and is used to transmit resolution data information to the level matching circuit.

[0050] Specifically, pins AP36 and AR36 of the first data transmission chip 11 transmit a pair of HDMI data (HDMI_TX2P_PORT and HDMI_TX2N_PORT) via either resistor R1 or resistor R1. Pins AR35 and AP35 transmit a pair of HDMI data (HDMI_TX1P_PORT and HDMI_TX1N_PORT) via either resistor R3 or resistor R4. Pins AP33 and AR33 transmit a pair of HDMI data (HDMI_TX0P_PORT and HDMI_TX0N_PORT) via either resistor R5 or resistor R6. Pins AR32 and AP32 of the first data transmission chip 11 transmit a pair of clock data (HDMI_TXCLKP_PORT and HDMI_TXCLKN_PORT) via either resistor R7 or resistor R8, which are used to transmit clock signals to the data conversion chip. For example, the resistance values ​​of resistors R1 through R8 can all be 2.2 ohms. These four pairs of data together constitute either the first video signal or the second video signal.

[0051] Pin 1U16 of the first data transmission chip 11 is also grounded through a ninth resistor R9. Exemplarily, the resistance of the ninth resistor R9 can be 1.62 kΩ. Pins 1N14 and 1N13 of the first data transmission chip 11 are connected to the first power supply terminal through a second capacitor C2 and a fourth capacitor C4. Exemplarily, the second capacitor C2 can be 100 nF, the fourth capacitor C4 can be 1 μF, and the voltage of the first power supply terminal can be 0.9 V. Pin 1P13 of the first data transmission chip 11 is connected to the second power supply terminal through a first capacitor C1 and a third capacitor C3. Exemplarily, the voltage of the second power supply terminal can be 1.8 V, the first capacitor C1 can be 100 nF, and the third capacitor C3 can be 1 μF.

[0052] Pin AG8 of the second data transmission chip 12 transmits clock data for HDMITX_SCL, and pin AG7 transmits resolution data for HDMITX_SDA. Pin V12 is connected to the third power supply terminal via a fifth capacitor C5. For example, the voltage of the second power supply terminal can be 3.3V, and the fifth capacitor C5 can be 100nF.

[0053] Figure 5 This is a schematic diagram of the structure of the first sub-chip of a data conversion chip provided in an embodiment of the present invention. Figure 6 This is a schematic diagram of the structure of a second sub-chip of a data conversion chip provided in an embodiment of the present invention. (Combined with...) Figures 2 to 6 Based on the above embodiments, optionally, both the first data conversion unit 21 and the second data conversion unit 22 include: a data conversion chip, connected to the control module 1 and the signal synthesis module 3, for receiving the first video signal and converting it into a first logic level signal, or for receiving the second video signal and converting it into a second logic level signal.

[0054] In this circuit, pin E4 of the first sub-chip 23 of the data conversion chip is connected to the third power supply terminal via the tenth resistor R10. For example, the voltage of the third power supply terminal can be 5V.

[0055] Pins B1 and A1 of the first sub-chip 23 are used to receive a pair of HDMI data from HDMI_TX2P_PORT and HDMI_TX2N_PORT, respectively. Pins B3 and A3 of the first sub-chip 23 are used to receive a pair of HDMI data from HDMI_TX1P_PORT and HDMI_TX1N_PORT, respectively. Pins B5 and A5 of the first sub-chip 23 are used to receive a pair of HDMI data from HDMI_TX0P_PORT and HDMI_TX0N_PORT, respectively. Pins B7 and A7 of the first sub-chip 23 are used to receive a pair of clock data from HDMI_TXCLKP_PORT and HDMI_TXCLKN_PORT, respectively, thereby realizing the reception of the first video signal or the second video signal.

[0056] The second sub-chip 24 is used to convert the first video signal or the second video signal into 48-bit TTL signal data and transmit it to the signal synthesis module 3 via pins TTL0-TTL47. Pins TTLVS, TTLHS, TTLVS, TTLLVCLK, and TTLDE of the second sub-chip 24 are configuration signals for 48-bit TTL signal data. For example, the signal synthesis module 3 may include an FPGA (Field Programmable Gate Array).

[0057] Figure 7 This is a schematic diagram of a connection detection circuit provided in an embodiment of the present utility model. (In conjunction with...) Figures 2 to 7 Based on the above embodiments, optionally, the first data conversion unit 21 and the second data conversion unit 22 further include a connection detection circuit. The connection detection circuit is connected between the control module 1 and the data conversion chip, and the data conversion chip is used to output a hot-plug detection signal to the control module 1 through the connection detection circuit.

[0058] The first sub-chip 23 outputs an HDMI_TX_HPD_PORT hot-plug detection signal via pin D6. This signal is converted into an HDMI_TX_HPDIN signal after passing through the eleventh resistor R11 and the twelfth resistor R12, and then transmitted to pin 1V17 of the first data transmission chip 11 via the sixth capacitor C6. When the first data transmission chip 11 receives the HDMI_TX_HPDIN signal, it indicates that the connection between the control module 1 and the data conversion module 2 is good, and the control module 1 begins to output the first video signal and the second video signal. For example, the eleventh resistor R11 can be 1 kΩ, the twelfth resistor R12 can be 100 kΩ, and the sixth capacitor C6 can be 100 nF.

[0059] Figure 8 This is a schematic diagram of a level matching circuit provided in an embodiment of the present utility model. (In conjunction with...) Figures 2 to 8 Based on the above embodiments, optionally, the first data conversion unit 21 and the second data conversion unit 22 further include a level matching circuit. The level matching circuit is connected between the control module 1 and the data conversion chip, and the control module 1 is also used to output resolution data information to the data conversion chip through the level matching circuit.

[0060] In this circuit, the first transistor Q1 is connected between the first input and the first output of the level matching circuit. The control terminal of the first transistor Q1 is connected to the second power supply terminal. The thirteenth resistor R13 is connected between the first terminal and the control terminal of the first transistor Q1. The second terminal of the first transistor Q1 is connected to the third power supply terminal through the fourteenth resistor R14 and the first diode D1. The second transistor Q2 is connected between the second input and the second output of the level matching circuit. The control terminal of the second transistor Q2 is connected to the second power supply terminal. The fifteenth resistor R15 is connected between the first terminal and the control terminal of the second transistor Q2. The second terminal of the second transistor Q2 is connected to the third power supply terminal through the sixteenth resistor R16 and the first diode D1.

[0061] The first terminal of the first transistor Q1 receives 3.3V HDMITX_SCL clock data, converts it to 5V HDMI_TXDDC_SCL_PORT clock data, and then transmits it to pin D4 of the first sub-chip 23. The first terminal of the second transistor Q2 receives 3.3V HDMITX_SDA resolution data, converts it to 5V HDMI_TXDDC_SDA_PORT resolution data, and then transmits it to pin D of the first sub-chip 23. A level matching circuit can be used to match the level differences of the transmitted signals between the control module and the data conversion chip.

[0062] This utility model embodiment also provides a display device. The display device includes a display module and a video signal splicing circuit provided in any embodiment of this utility model, possessing similar beneficial effects to the video signal splicing circuit, which will not be described in detail here.

[0063] It should be understood that the various forms of the process shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this utility model can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this utility model can be achieved, and this is not limited herein.

[0064] The specific embodiments described above do not constitute a limitation on the scope of protection of this utility model. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this utility model should be included within the scope of protection of this utility model.

Claims

1. A video signal splicing circuit, characterized in that, include: The control module is used to divide the original video signal at a first resolution into a first video signal at a second resolution and a second video signal at a second resolution. The second resolution is half of the first resolution; A data conversion module is connected to the control module. The data conversion amount of the data conversion module matches the data amount of the first video signal and the second video signal. It is used to receive the first video signal and convert it into a first logic level signal, and also to receive the second video signal and convert it into a second logic level signal. The signal synthesis module, connected to the data conversion module, is used to synthesize the first logic level signal and the second logic level signal into a display video signal with a first resolution, and transmit it to the display module for image display.

2. The video signal splicing circuit according to claim 1, characterized in that, The data conversion module includes: A first data conversion unit, the input interface of which is connected to the control module, and the output interface of which is connected to the signal synthesis module; The second data conversion unit has an input interface connected to the control module and an output interface connected to the signal synthesis module. The first data conversion unit and the second data conversion unit have the same structure.

3. The video signal splicing circuit according to claim 2, characterized in that, The input interfaces of both the first data conversion unit and the second data conversion unit are HDMI 2.0 interfaces.

4. The video signal splicing circuit according to claim 2, characterized in that, Both the first data conversion unit and the second data conversion unit include: a data conversion chip, connected to the control module and the signal synthesis module, for receiving the first video signal and converting it into the first logic level signal, or for receiving the second video signal and converting it into the second logic level signal.

5. The video signal splicing circuit according to claim 4, characterized in that, The first data conversion unit and the second data conversion unit further include: a connection detection circuit; The connection detection circuit is connected between the control module and the data conversion chip, and the data conversion chip is used to output a hot-plug detection signal to the control module through the connection detection circuit.

6. The video signal splicing circuit according to claim 5, characterized in that, The first data conversion unit and the second data conversion unit further include: a level matching circuit; The level matching circuit is connected between the control module and the data conversion chip. The control module is also used to output resolution data information to the data conversion chip through the level matching circuit.

7. The video signal splicing circuit according to claim 6, characterized in that, The control module includes: at least one first data transmission chip and at least one second data transmission chip; The first data transmission chip is connected to the data conversion chip and is used to transmit the first video signal or the second video signal to the data conversion chip. The first data transmission chip is also connected to the connection detection circuit for receiving the hot-plug detection signal; The second data transmission chip is connected to the level matching circuit and is used to transmit the resolution data information to the level matching circuit.

8. The video signal splicing circuit according to claim 1, characterized in that, The first resolution is 8K, and the second resolution is 4K.

9. The video signal splicing circuit according to claim 1, characterized in that, The type of both the first logic level signal and the second logic level signal is: TTL signal.

10. A display device, characterized in that, include: The display module and the video signal splicing circuit according to any one of claims 1-9.

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