Power module and electronic device
By employing a U-shaped liner design and a centrally positioned gate lead frame in the power module, the overheating problem of the EconoDUAL3 package in high-power, low-voltage, and high-current scenarios is solved, achieving more efficient heat dissipation and current sharing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- ZHUHAI GREE ELECTRONIC COMPONENTS CO LTD
- Filing Date
- 2025-07-25
- Publication Date
- 2026-07-07
Smart Images
Figure CN224473694U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the semiconductor field, and more specifically, to a power module and an electronic device. Background Technology
[0002] The EconoDUAL3 package, as the industry standard package for power modules, is widely used in medium-to-high power applications such as photovoltaic inverters and energy storage converters. However, this package has a significant bottleneck when dealing with the requirements of "high power, low voltage, and high current": an unreasonable substrate layout can lead to differences in current paths, causing localized overheating.
[0003] There is currently no effective solution to the above problems. Utility Model Content
[0004] This application provides a power module and an electronic device to at least solve the technical problem of high temperature in power modules in the related art.
[0005] According to one aspect of the present application, a power module is provided, including: a package housing, a substrate region located within the package housing, and a power chip; the substrate region includes a ceramic substrate layer, a first copper layer, and a second copper layer, the ceramic substrate layer having a first surface and a second surface that are opposite to each other, the first copper layer being fixed on the first surface for mounting the power chip, and the second copper layer being fixed on the second surface; the power transmission path of the substrate region adopts a U-shaped layout.
[0006] Optionally, the liner area includes a first liner and a second liner arranged symmetrically, and the power transmission paths on the first copper layer of the first liner and the first copper layer of the second liner both adopt a U-shaped layout.
[0007] Optionally, the first U-shaped frame on the first copper layer of the first substrate is connected to the first power terminal on the package housing via a bonding wire; the second U-shaped frame on the first copper layer of the second substrate is connected to the second power terminal on the package housing via a bonding wire.
[0008] Optionally, the first U-shaped frame on the first copper layer of the first substrate is connected to the second U-shaped frame on the first copper layer of the second substrate via a bonding wire.
[0009] Optionally, the bonding wires used between the first U-shaped frame on the first copper layer of the first substrate and the second U-shaped frame on the first copper layer of the second substrate, the bonding wires used between the first U-shaped frame on the first copper layer of the first substrate and the first power terminal on the package housing, and the bonding wires used between the second U-shaped frame on the first copper layer of the second substrate and the second power terminal on the package housing are all 16mil copper bonding wires.
[0010] Optionally, the gate lead frame in the liner region adopts a central layout.
[0011] Optionally, the power module further includes a gate resistor connected between the gate of the power chip and the gate lead frame, the gate lead frame being connected to the signal terminals of the package housing via bonding wires.
[0012] Optionally, the gate lead frame on the first copper layer of the first substrate is connected to the gate lead frame on the first copper layer of the second substrate via bonding wires.
[0013] Optionally, the source of the power chip is connected to the source lead frame via bonding wires; the source lead frame on the first copper layer of the first substrate is connected to the source lead frame on the first copper layer of the second substrate via bonding wires.
[0014] According to another aspect of the embodiments of this application, an electronic device is also provided, including the power module described above.
[0015] In this embodiment, the power module provided by the technical solution of this application includes a package housing, a substrate area located within the package housing, and a power chip. The substrate area includes a ceramic substrate layer, a first copper layer, and a second copper layer. The ceramic substrate layer has a first surface and a second surface that are opposite to each other. The first copper layer is fixed on the first surface for mounting the power chip, and the second copper layer is fixed on the second surface. The power transmission path in the substrate area adopts a U-shaped layout. The U-shaped current convergence design can reduce path differences, thereby improving dynamic current sharing characteristics and shortening the current path to reduce parasitic inductance and parasitic resistance problems caused by line connections. Both of these factors will reduce heat generation, thereby solving the technical problem of high temperature in power modules in related technologies. Attached Figure Description
[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.
[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.
[0019] Figure 1 This is a schematic diagram of an optional packaging form according to an embodiment of this application;
[0020] Figure 2 This is a schematic diagram of an optional power module according to an embodiment of this application;
[0021] Figure 3 This is a schematic diagram of an optional liner structure according to an embodiment of this application;
[0022] Figure 4 This is a schematic diagram of an optional power module pinout according to an embodiment of this application;
[0023] Figure 5 This is a schematic diagram of an optional power module according to an embodiment of this application;
[0024] Figure 6 This is a schematic diagram of an optional liner structure according to an embodiment of this application;
[0025] Figure 7 This is a schematic diagram of an optional power module pinout according to an embodiment of this application;
[0026] Figure 8 This is a schematic diagram of an optional power module according to an embodiment of this application. Detailed Implementation
[0027] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0028] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0029] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0030] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0031] Furthermore, terms such as "horizontal," "vertical," and "sag" do not imply that components must be absolutely horizontal or suspended, but rather that they can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal relative to "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.
[0032] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0033] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0034] To adapt to scenarios involving "high power, low voltage, and high current," and focusing on steady-state high current output, this application provides a power module in an EconoDUAL3 package. (See attached image.) Figure 1 It is compatible with existing modules. The U-shaped structure shortens the current path, enhancing current sharing and heat dissipation. The U-shaped current converging design reduces path differences and improves dynamic current sharing characteristics. For example... Figure 2 As shown, this module includes:
[0035] The package housing (including ED3 package side frame 1, ED3 package cover plate, etc.), the substrate area located inside the package housing (i.e. the area composed of substrate 3) and the power chip 8;
[0036] Each substrate in the aforementioned substrate region includes a ceramic substrate layer, a first copper layer, and a second copper layer. The ceramic substrate layer has a first surface and a second surface that are opposite to each other (as shown above and below). The first copper layer is fixed to the first surface (as shown on the upper surface of the ceramic substrate, where the first copper layer is referred to as the upper copper layer) for mounting power chips. The second copper layer is fixed to the second surface (as shown on the lower surface of the ceramic substrate, where the second copper layer is referred to as the lower copper layer) for heat dissipation or providing conductive circuitry. The power transmission path in the substrate region adopts a U-shaped layout, which can shorten the current path, reduce parasitic inductance / resistance, and reduce heat generation.
[0037] In an optional embodiment, the liner area includes, as shown in the figure below. Figure 2 The first substrate 3 and the second substrate are arranged symmetrically on the left and right sides. The power transmission paths on the first copper layer of the first substrate and the first copper layer of the second substrate both adopt a U-shaped layout. The first U-shaped frame on the first copper layer of the first substrate is connected to the second U-shaped frame on the first copper layer of the second substrate through a bonding line.
[0038] The first U-shaped frame on the first copper layer of the first substrate is connected to the first power terminal on the package housing via a bonding wire; the second U-shaped frame on the first copper layer of the second substrate is connected to the second power terminal on the package housing via a bonding wire (the second power terminal and the first power terminal can be one or separate).
[0039] The bonding wires used between the first U-shaped frame on the first copper layer of the first substrate and the second U-shaped frame on the first copper layer of the second substrate, the bonding wires used between the first U-shaped frame on the first copper layer of the first substrate and the first power terminal on the package housing, and the bonding wires used between the second U-shaped frame on the first copper layer of the second substrate and the second power terminal on the package housing are all 16mil copper bonding wires.
[0040] In the technical solution of this application, the current path is shortened by using a U-shaped layout, integrated chip layout, and bonding wire connection, which enhances current sharing and heat dissipation, and reduces parasitic inductance and resistance problems caused by line connections. The use of a double U-shaped parallel current conductor has spatial geometric symmetry and electrical dual-path parallel connection, which can improve the current carrying capacity of the power module and reduce parasitic parameters.
[0041] In another alternative embodiment, the gate lead frame of the substrate region is centrally located (i.e., situated in the central region), and the gate lead frame on the first copper layer of the first substrate is connected to the gate lead frame on the first copper layer of the second substrate via bonding wires. The power module also includes a gate resistor connected between the gate of the power chip and the gate lead frame, which is connected to the signal terminals of the package housing via bonding wires.
[0042] The source of the aforementioned power chip is connected to the source lead frame via bonding wires; the source lead frame on the first copper layer of the first substrate is connected to the source lead frame on the first copper layer of the second substrate via bonding wires. By integrating the centrally located chip gate driver, the chip gate is connected by two lead frames and converges to a single signal terminal, eliminating the need for secondary development of the driver.
[0043] It should be noted that the EconoDUAL3 package is used, with the drain and source forming the main power path: the U-shaped frame carries the high current and is directly connected to the drain (high potential end) of the chip, forming the main power transmission path; the gate is the control loop: the gate is connected to the signal terminal (low potential reference point) via the gate lead frame, forming the control circuit (not connected to the U-shaped frame). A Si MOSFET chip is integrated on the substrate according to a single-switch circuit topology. By optimizing chip selection, parallel connection scheme, and substrate layout, the high current requirements are met. The Si MOSFET chip, as the circuit switch, is simple to drive and improves energy efficiency.
[0044] The power module using the technical solution of this application includes a package housing, a substrate area located within the package housing, and a power chip. The substrate area includes a ceramic substrate layer, a first copper layer, and a second copper layer. The ceramic substrate layer has a first surface and a second surface that are opposite to each other. The first copper layer is fixed to the first surface for mounting the power chip, and the second copper layer is fixed to the second surface. The power transmission path in the substrate area adopts a U-shaped layout. The U-shaped current convergence design can reduce path differences, thereby improving dynamic current sharing characteristics and shortening the current path to reduce parasitic inductance and resistance problems caused by line connections. Both of these factors lead to a reduction in heat generation, thereby solving the technical problem of high temperature in power modules in related technologies.
[0045] This application proposes an EconoDUAL3 package U-shaped substrate layout structure, in which the internal insulating substrate is a copper-clad ceramic substrate with high thermal conductivity Si3N4, and the surface copper layer is etched to form conductive circuits. As an optional embodiment, the technical solution of this application is further described in detail below with reference to specific embodiments:
[0046] like Figure 2The product layout shown includes two ceramic backing plates using AMB (Active Metal Brazing). The ceramic substrate has a three-layer structure: a lower copper layer, a middle ceramic layer, and an upper copper layer.
[0047] The middle layer is an insulating layer made of Si3N4 ceramic substrate with a thermal conductivity ≥80W / (m·K);
[0048] The upper copper layer is an oxygen-free copper layer. The upper copper layer forms conductive paths through etching. The copper layer is soldered onto the heat sink to form heat dissipation paths. The surface copper layer is etched to form multi-area conductive circuits. The lower copper layer is also an oxygen-free copper layer.
[0049] In Option 1 (Reference) Figures 2 to 4 In ) such as Figure 2 and Figure 3 As shown, 1-ED3 package side frame, 2-package side frame rivet ring, 3-backer, 4-source lead frame A, 5-bonding wire, 6-package side frame signal terminal, 7-U-frame A, 8-Si MOSFET chip (i.e., power chip), 9-external resistor (gate resistor), 10-gate lead frame A, 11-U-frame B, 12-source lead frame B, 13-gate lead frame B, 14-thermistor, 15-package side frame power terminal, 16-U-frame C. It should be noted that... Figure 4 The numbers in the package indicate the pin or signal terminal numbers, conforming to the EconoDUAL3 package standard, and are consistent with... Figure 2 and Figure 3 The meanings of the numbers are different.
[0050] Compared to aluminum wire of the same specification, copper wire has 1.5 times the current carrying capacity of aluminum wire. To save production costs, Si MOSFET chips are connected to the chip source by aluminum wire bonding wire with a diameter of 15mil, and the gate bonding wire is aluminum wire with a diameter of 5mil. The power terminals and substrates and the space between the two substrates use copper wire with a diameter of 16mil, and the remaining bonding wires use aluminum wire with a diameter of 15mil.
[0051] In Option 2 (Reference) Figures 5 to 7 In ) such as Figure 5 and Figure 6As shown, 1-ED3 package side frame, 2-package side frame rivet ring, 3-backer plate, 4-source lead frame A, 5-bonding wire, 6-package side frame signal terminal, 7-gate lead frame A, 8-Si MOSFET chip (i.e., power chip), 9-external resistor (i.e., gate resistor), 10-U-frame A, 11-gate lead frame B, 12-U-frame B, 13-source lead frame B, 14-thermistor, 15-package side frame power terminal, 16-gate lead frame D, 17-backer plate frame, 18-gate lead frame C, 19-U-frame C. It should be noted that... Figure 7 The numbers in the package name indicate the pin or signal terminal number (1, 2, 8, 9 are power terminals, 3, 4, 5, 6, 7 are signal terminals), conforming to the EconoDUAL3 package standard. Figure 5 and Figure 6 The meanings of the numbers are different.
[0052] The bonding scheme is almost identical to Scheme 1, but the gate connection path is too long, which affects the chip's conduction. Therefore, Scheme 1 is preferred.
[0053] 1) Chip and gate resistance bonding
[0054] like Figure 2 The product layout shown depicts a Si MOSFET chip and gate resistor soldered to a copper layer on a substrate via solder pads. The chip's source is connected to the source leadframe A / B via a 15mil aluminum wire. (Signal terminal 6 is a special bonding point, a process-specific bonding point, eliminating the need for an additional aluminum wire leadframe design; otherwise, a leadframe extension similar to that at signal terminal 5 would be required.) Figure 8 As shown; to improve substrate utilization, the chip's gate is connected to the gate resistor via a 5mil aluminum wire, and then connected to the gate lead frame A / B via the back electrode of the resistor.
[0055] 2) Module bonding
[0056] U-shaped frames A / B and B / C are connected by 16mil copper wire. Source lead frames A / B are connected by 16mil copper wire. Power terminals 1 / 2 are connected to U-shaped frame B by 16mil copper wire. Power terminals 8 / 9 are connected to source lead frame A (marked as 4) by 16mil copper wire. Gate lead frame A and gate lead frame B are connected by 15mil aluminum wire. Signal terminal 5 is connected to gate lead frame A by 15mil aluminum wire. Signal terminal 6 uses 15mil aluminum wire to connect the chip source to source lead frame A.
[0057] 3) Potting and curing
[0058] The potting compound is injected into the product and then cured.
[0059] In the technical solution of this application, a centrally located SiMOSFET chip gate lead frame is designed; the source signal leads are integrated onto a single chip, eliminating the need for a separate lead frame and increasing substrate space utilization. The bonding wires run from the gate bond wire of the SiMOSFET chip to an external resistor on the gate lead frame, and are then connected to the gate lead frame via the back electrode of the external resistor. The signal is fed back to the pin signal terminals on the package side frame through the gate lead frame. Both substrates are designed with this layout. A U-shaped substrate layout is adopted, with the entire layout being almost symmetrically distributed vertically on the substrates. The U-shaped layout shortens the current path, enhances current sharing and heat dissipation, and the U-shaped current convergence design reduces path differences and improves dynamic current sharing characteristics.
[0060] According to another aspect of the embodiments of this application, an electronic device is also provided, including the power module described above. The electronic device can be a household appliance, a new energy vehicle, an industrial power supply, an industrial motor, or other equipment.
[0061] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.
[0062] The above description is only a preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.
Claims
1. A power module, characterized in that, include: The package housing, the liner area located within the package housing, and the power chip; The liner in the liner area includes a ceramic substrate layer, a first copper layer and a second copper layer. The ceramic substrate layer has a first surface and a second surface that are opposite to each other. The first copper layer is fixed on the first surface for mounting the power chip, and the second copper layer is fixed on the second surface. The power transmission path in the liner area adopts a U-shaped layout.
2. The power module according to claim 1, characterized in that, The liner area includes a first liner and a second liner arranged symmetrically, and the power transmission paths on the first copper layer of the first liner and the first copper layer of the second liner both adopt a U-shaped layout.
3. The power module according to claim 2, characterized in that, The first U-shaped frame on the first copper layer of the first substrate is connected to the first power terminal on the package housing via a bonding wire; the second U-shaped frame on the first copper layer of the second substrate is connected to the second power terminal on the package housing via a bonding wire.
4. The power module according to claim 3, characterized in that, The first U-shaped frame on the first copper layer of the first substrate is connected to the second U-shaped frame on the first copper layer of the second substrate via bonding wires.
5. The power module according to claim 4, characterized in that, The bonding wires used between the first U-shaped frame on the first copper layer of the first substrate and the second U-shaped frame on the first copper layer of the second substrate, the bonding wires used between the first U-shaped frame on the first copper layer of the first substrate and the first power terminal on the package housing, and the bonding wires used between the second U-shaped frame on the first copper layer of the second substrate and the second power terminal on the package housing are all 16mil copper bonding wires.
6. The power module according to any one of claims 1 to 5, characterized in that, The gate lead frame in the substrate area adopts a central layout.
7. The power module according to claim 6, characterized in that, The power module also includes a gate resistor connected between the gate of the power chip and the gate lead frame, which is connected to the signal terminal of the package housing via bonding wires.
8. The power module according to any one of claims 2 to 5, characterized in that, The gate lead frame on the first copper layer of the first substrate is connected to the gate lead frame on the first copper layer of the second substrate via bonding wires.
9. The power module according to any one of claims 2 to 5, characterized in that, The source of the power chip is connected to the source lead frame via bonding wires; The source lead frame on the first copper layer of the first substrate is connected to the source lead frame on the first copper layer of the second substrate via bonding wires.
10. An electronic device, characterized in that, Includes the power module as described in any one of claims 1-9.