A transistor, display panel and display device
By setting a grounded auxiliary gate structure in the transistor, leakage current and parasitic capacitance are reduced, solving the problems of high leakage current and large parasitic capacitance in silicon-based display panels, improving display brightness and dark spots and crosstalk issues, and enhancing display uniformity.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SEEYA INFORMATION TECHNOLOGY CO LTD
- Filing Date
- 2025-06-26
- Publication Date
- 2026-07-10
AI Technical Summary
Existing silicon-based display panels suffer from problems such as high leakage current, large parasitic capacitance, and poor mismatch performance, leading to issues with bright and dark spots and crosstalk, which affect display uniformity.
In the transistor, a second auxiliary gate structure is set on the side of the second doped region near the channel region, and a first auxiliary gate structure is set on the side of the first doped region near the channel region. The first auxiliary gate and the second auxiliary gate are grounded to provide a ground signal, increase the spread resistance of the source and drain, reduce the electric field peak, and reduce the parasitic capacitance through the electric field shielding effect.
It effectively reduces the leakage current and parasitic capacitance of transistors, improves the bright and dark spots and crosstalk issues of the display panel, and enhances display uniformity.
Smart Images
Figure CN224481967U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of display technology, and in particular to a transistor, a display panel, and a display device. Background Technology
[0002] As the refresh rate and resolution requirements of display panels continue to increase, the charging time for each row in silicon-based display panels is constantly decreasing, while the number of pixels per row is also increasing. Therefore, the driving capability of the panel needs to meet the requirement of charging more pixels in each row in a shorter time.
[0003] Semiconductor MOS devices are typically used as switches in display panels to drive pixels to emit light. To avoid issues such as bright and dark spots and crosstalk in the display panel, and to improve brightness uniformity, the MOS devices in the pixel driving circuit are required to have ultra-low leakage current, low gate-source parasitic capacitance (Low Cgs), low gate-drain parasitic capacitance (Low Cgd), and good mismatch performance. Utility Model Content
[0004] This invention provides a transistor, a display panel, and a display device, which can reduce leakage current in the transistor, reduce parasitic capacitance in the transistor, improve the mismatch performance of the transistor, improve the display panel's bright and dark spots and crosstalk problems, and improve the brightness uniformity of the display panel.
[0005] In a first aspect, this utility model provides a transistor, comprising:
[0006] A silicon-based substrate includes a well-doped region, wherein the well-doped region is provided with a first doped region, a second doped region, and a channel region located between the first doped region and the second doped region; a heavily doped source region is provided in the first doped region, and a heavily doped drain region is provided in the second doped region; along a direction parallel to the plane of the silicon-based substrate, the heavily doped source region is located on the side of the first doped region away from the channel region, and the heavily doped drain region is located on the side of the second doped region away from the channel region;
[0007] A main gate structure that at least covers the channel region; the main gate structure includes a main gate insulating structure and a main gate located on the side of the main gate insulating structure facing away from the silicon substrate;
[0008] A first auxiliary gate structure covers a portion of the first doped region; along a direction parallel to the plane of the silicon substrate, the first auxiliary gate structure is located on the side of the first doped region closer to the channel region; the first auxiliary gate structure includes a first gate insulating structure and a first auxiliary gate located on the side of the first gate insulating structure opposite to the silicon substrate.
[0009] A second auxiliary gate structure covers a portion of the second doped region; along a direction parallel to the plane of the silicon substrate, the second auxiliary gate structure is located on the side of the second doped region closer to the channel region; the second auxiliary gate structure includes a second gate insulating structure and a second auxiliary gate located on the side of the second gate insulating structure opposite to the silicon substrate;
[0010] Both the first auxiliary gate and the second auxiliary gate are electrically connected to the ground terminal.
[0011] Secondly, embodiments of the present invention also provide a display panel, comprising: at least one transistor as described in the first aspect.
[0012] Optionally, the display panel may also include: light-emitting devices and driving circuitry;
[0013] The driving circuit is electrically connected to the light-emitting device; the driving circuit includes at least one of the transistors.
[0014] Thirdly, the present invention also provides a display device, including the display panel described in the second aspect.
[0015] The technical solution of this utility model involves setting a second auxiliary gate structure on the side of the second doped region near the channel region along a direction parallel to the plane of the silicon substrate, and a first auxiliary gate structure on the side of the first doped region near the channel region. The first auxiliary gate in the first auxiliary gate structure covering at least a portion of the first doped region is grounded, and the second auxiliary gate in the second auxiliary gate structure covering at least a portion of the second doped region is grounded. This allows the first and second auxiliary gate structures to provide grounding signals to the first and second doped regions on the side away from the silicon substrate when leakage current exists in the transistor. This increases the extended resistance of the source and drain electrodes, and it does not change with the operating voltage of the first and second doped regions. This makes it easier to improve the electric field distribution gradient on the side of the first or second doped region near the communication region away from the silicon substrate, reducing the electric field peak at that location and causing the electric field peak to shift towards the silicon substrate side. This, in turn, reduces the leakage current of the transistor and improves the mismatch performance of the transistor. In addition, grounding the first and second auxiliary gates can serve as an electric field shield, which can greatly reduce the side electric field strength between the main gate and the first or second doped region, thereby greatly reducing the parasitic side capacitance between the main gate and the first or second doped region, and further reducing the overall parasitic capacitance within the transistor. This can improve the bright and dark spots and crosstalk issues in the display panel, and also improve the display uniformity. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, although the drawings described below are some specific embodiments of this utility model, those skilled in the art can extend and extend to other structures and drawings based on the basic concepts of the device structure, driving method and manufacturing method disclosed and indicated by the various embodiments of this utility model. Undoubtedly, these should all be within the scope of the claims of this utility model.
[0017] Figure 1 This is a schematic diagram of the structure of a transistor in a related technology.
[0018] Figure 2 A schematic diagram of the structure of a first type of transistor provided in an embodiment of this utility model;
[0019] Figure 3 This is a schematic diagram of the structure of a second type of transistor provided in an embodiment of the present invention;
[0020] Figure 4 This is a schematic diagram of the structure of a third type of transistor provided in an embodiment of the present invention;
[0021] Figure 5This is a schematic diagram of the structure of the fourth transistor provided in an embodiment of the present utility model;
[0022] Figure 6 This is a schematic diagram of the structure of the fifth type of transistor provided in the embodiments of this utility model;
[0023] Figure 7 A schematic diagram of the structure of the sixth transistor provided in this embodiment of the present invention;
[0024] Figure 8 A schematic diagram of the structure of the seventh transistor provided in this embodiment of the present invention;
[0025] Figure 9 This is a schematic diagram of the structure of the eighth transistor provided in the embodiment of the present utility model;
[0026] Figure 10 This is a structural schematic diagram of the ninth type of display panel provided in this embodiment of the utility model.
[0027] Figure 11 This is a schematic diagram of the structure of a display device provided in an embodiment of the present utility model. Detailed Implementation
[0028] To make the objectives, technical solutions, and advantages of this utility model clearer, the technical solutions of this utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments of this utility model. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the basic concepts disclosed and indicated in the embodiments of this utility model, all other embodiments obtained by those skilled in the art are within the protection scope of this utility model.
[0029] Figure 1 This is a schematic diagram of a transistor structure in a related technology, such as... Figure 1 As shown, the transistor includes a substrate 01, a channel region 023 located on one side of the substrate 01, and a first doped region 021 and a second doped region 022 located on both sides of the channel region 023. The first doped region 021 and the second doped region 022 have the same doping type, while the first doped region 021 has a different doping type than the channel region 023.
[0030] Taking an N-type transistor as an example, the leakage current types of transistors include channel leakage current, gate-drain leakage current, and drain-junction leakage current. Channel leakage current refers to the leakage current formed by the diffusion of a small number of carriers in the channel region 023 when the transistor is in the off state, in the subthreshold region where the gate voltage is below the threshold voltage Vth but greater than zero. Gate-drain leakage current refers to the leakage phenomenon caused by the inter-band tunneling effect induced by the strong electric field in the gate-drain overlap region when the transistor is in the off state. Drain-junction leakage current refers to the leakage current generated when the PN junction of the drain 052 and the substrate 01 is reverse biased when the transistor is in the off state.
[0031] To reduce leakage current in the transistor, a first auxiliary gate 041 electrically connected to the source 051 and a second auxiliary gate 042 electrically connected to the drain 052 are typically provided within the first doped region 021. The potential of the first auxiliary gate 041 is synchronized with the potential of the source 051, and the potential of the second auxiliary gate 042 is synchronized with the potential of the drain 052. Under the shielding effect of the second auxiliary gate 042, no metal silicide is formed in the active region located below the second auxiliary gate 042 near the substrate 01. This increases the spread resistance of the second doped region 022, affecting the electric field distribution gradient between the gate 03 and the drain 052, reducing the electric field peak value in the heavily doped drain region, and shifting the electric field peak value towards the substrate 01 side, thereby reducing the gate-drain leakage current and the drain junction leakage current of the transistor.
[0032] However, along the direction parallel to the plane where the substrate 01 is located, the first auxiliary gate 041 is located between the source 051 and the gate 03. When the transistor is in the on state, a gate-source parasitic capacitance is generated between the gate 03 and the source 051, and an additional parasitic capacitance is generated between the gate 03 and the first auxiliary gate 041. Correspondingly, the second auxiliary gate 042 is located between the drain 052 and the gate 03. When the transistor is in the on state, a gate-drain parasitic capacitance is generated between the gate 03 and the drain 052, and an additional parasitic capacitance is generated between the gate 03 and the second auxiliary gate 042. Thus, setting the first auxiliary gate 041 and the second auxiliary gate 042 increases the parasitic capacitance in the transistor, thereby affecting the transistor's on / off rate and power consumption, and making it easier to cause display crosstalk problems in the display panel. Furthermore, the existing first auxiliary gate 041 and second auxiliary gate 042 were originally part of gate 03, which shortened the effective channel length in the active region 023 of the transistor. Small fluctuations in the fabrication parameters had a significant impact on the performance of the transistor, resulting in high mismatch of the transistor and thus easily causing display uniformity problems in the display panel.
[0033] To address the aforementioned problems, this utility model provides a transistor, comprising: a silicon substrate including a well-doped region, wherein the well-doped region is provided with a first doped region, a second doped region, and a channel region located between the first doped region and the second doped region; a heavily doped source region is provided within the first doped region, and a heavily doped drain region is provided within the second doped region; along a direction parallel to the plane of the silicon substrate, the heavily doped source region is located on the side of the first doped region facing away from the channel region, and the heavily doped drain region is located on the side of the second doped region facing away from the channel region; a main gate structure, at least covering the channel region; the main gate structure includes a main gate insulating structure and a main gate located on the side of the main gate insulating structure facing away from the silicon substrate; a first auxiliary... A first auxiliary gate structure covers a portion of the first doped region; along a direction parallel to the plane of the silicon substrate, the first auxiliary gate structure is located on the side of the first doped region near the channel region; the first auxiliary gate structure includes a first gate insulating structure and a first auxiliary gate located on the side of the first gate insulating structure away from the silicon substrate; a second auxiliary gate structure covers a portion of the second doped region; along a direction parallel to the plane of the silicon substrate, the second auxiliary gate structure is located on the side of the second doped region near the channel region; the second auxiliary gate structure includes a second gate insulating structure and a second auxiliary gate located on the side of the second gate insulating structure away from the silicon substrate; wherein, both the first auxiliary gate and the second auxiliary gate are electrically connected to a ground terminal.
[0034] By employing the above technical solution, by setting a second auxiliary gate structure on the side of the second doped region near the channel region and a first auxiliary gate structure on the side of the first doped region near the channel region along a direction parallel to the plane of the silicon substrate, and grounding the first auxiliary gate in the first auxiliary gate structure covering at least part of the first doped region and grounding the second auxiliary gate in the second auxiliary gate structure covering at least part of the second doped region, when leakage current exists in the transistor, the first and second auxiliary gate structures can provide grounding signals to the first and second doped regions on the side away from the silicon substrate, thereby increasing the extended resistance of the source and drain electrodes, which does not change with the operating voltage of the first and second doped regions. This makes it easier to improve the electric field distribution gradient on the side of the first or second doped region near the communication region away from the silicon substrate, reducing the electric field peak at that location and causing the electric field peak to shift towards the silicon substrate side, thereby reducing the leakage current of the transistor and improving the mismatch performance of the transistor. In addition, grounding the first and second auxiliary gates can serve as an electric field shield, which can greatly reduce the side electric field strength between the main gate and the first or second doped region, thereby greatly reducing the parasitic side capacitance between the main gate and the first or second doped region, and further reducing the overall parasitic capacitance within the transistor. This can improve the bright and dark spots and crosstalk issues in the display panel, and also improve the display uniformity.
[0035] The above is the core idea of this utility model. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model. The technical solutions in the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings.
[0036] Figure 2 A schematic diagram of the structure of the first transistor provided in the embodiment of this utility model is shown below. Figure 2 As shown, the transistor includes a silicon substrate 10, a main gate structure 30, a first auxiliary gate structure 41, and a second auxiliary gate structure 42. The silicon substrate 10 includes a well doped region 20, within which a first doped region 21, a second doped region 22, and a channel region 23 located between the first doped region 21 and the second doped region 22 are disposed. A heavily doped source region 211 is disposed within the first doped region 21, and a heavily doped drain region 221 is disposed within the second doped region 22. Along the direction X parallel to the plane of the silicon substrate 10, the heavily doped source region 211 is located on the side of the first doped region 21 facing away from the channel region 23, and the heavily doped drain region 221 is located on the side of the second doped region 22 facing away from the channel region 23. The main gate structure 30 at least covers the channel region 23. The main gate structure 30 includes a main gate insulating structure 31 and a main gate 32 located on the side of the main gate insulating structure 31 facing away from the silicon substrate 10. A first auxiliary gate structure 41 covers a portion of the first doped region 21; along the direction X parallel to the plane of the silicon substrate 10, the first auxiliary gate structure 41 is located on the side of the first doped region 21 near the channel region 23; the first auxiliary gate structure 41 includes a first gate insulating structure 411 and a first auxiliary gate 412 located on the side of the first gate insulating structure 411 facing away from the silicon substrate 10. A second auxiliary gate structure 42 covers a portion of the second doped region 22; along the direction X parallel to the plane of the silicon substrate 10, the second auxiliary gate structure 42 is located on the side of the second doped region 22 near the channel region 23; the second auxiliary gate structure 42 includes a second gate insulating structure 421 and a second auxiliary gate 422 located on the side of the second gate insulating structure 421 facing away from the silicon substrate 10.
[0037] The first auxiliary gate 412 and the second auxiliary gate 422 are both electrically connected to the ground terminal GND.
[0038] The silicon substrate 10 includes materials such as SiC, monocrystalline silicon, or polycrystalline silicon. The first doping region 21 and the second doping region 22 have the same doping type, while the first doping region 21 and the well doping region 20 have different doping types. For example, if trivalent elements such as boron or aluminum are doped in the first doping region 21 and the second doping region 22, and pentavalent elements such as phosphorus or arsenic are doped in the well doping region 20, a P-type transistor can be formed. If pentavalent elements such as phosphorus or arsenic are doped in the first doping region 21 and the second doping region 22, and trivalent elements such as boron or aluminum are doped in the channel region 23, an N-type transistor can be formed.
[0039] For ease of description, the dopant concentration in the heavily doped source region 211 is greater than that in the first lightly doped region 212, and the dopant concentration in the heavily doped drain region 221 is greater than that in the second lightly doped region 222. This reduces the electric field gradient between the drain and source, thus minimizing the risk of breakdown. NMOS transistors have high electron mobility, making them prone to hot carrier effects. By keeping the dopant concentrations in the first and second lightly doped regions 212 and 222 lower, these hot carrier effects can be effectively suppressed, improving transistor reliability.
[0040] Taking the fabrication process of an N-type transistor as an example, the formation method of the well-doped region 20 can be described as follows: After providing a silicon substrate 10, boron is implanted into the region where the well-doped region 20 is located in the silicon substrate 10 using ion implantation technology. The energy is 100–400 keV, and the dose is 2E13–6E13 / cm. 2 Phosphorus elements are implanted into the first lightly doped region 212 and the second lightly doped region 222 in the silicon substrate 10 at energies of 50–300 keV and doses of 1 E12–8 E12 / cm. 2 Phosphorus elements are implanted into the regions containing the heavily doped source region 211 and the heavily doped drain region 221 in the silicon substrate 10 at energies of 10–50 keV and doses of 2E14–2E15 / cm². 2 The well-doped region 20 can also be formed in other ways, which are not specifically limited here.
[0041] The main gate insulating structure 31, the first gate insulating structure 411, and the second gate insulating structure 421 include oxide insulating materials such as silicon dioxide. The main gate 32, the first auxiliary gate 412, and the second auxiliary gate 422 are made of at least one of polycrystalline silicon, aluminum, titanium, tantalum, molybdenum, etc., and can be set according to actual needs.
[0042] Specifically, along the direction X parallel to the plane of the silicon substrate 10, the second auxiliary gate structure 42 is located on the side of the heavily doped drain region 221 near the channel region 23, and the first auxiliary gate structure 41 is located on the side of the heavily doped source region 211 near the channel region 23, so that the first auxiliary gate structure 41 covers at least part of the first doped region 21 and the second auxiliary gate structure 42 covers at least part of the second doped region 22. After that, the first auxiliary gate structure 41 can be located on the side of the heavily doped source region 211 near the channel region 23, and the second auxiliary gate structure 42 can be located on the side of the heavily doped drain region 221 near the channel region 23. By electrically connecting both the first auxiliary gate 412 and the second auxiliary gate 422 to the ground terminal GND, the ground terminal GND can provide a stable zero-potential signal. This increases the extended resistance of the source and drain regions, and it does not change with the operating voltage of the first and second doped regions. This makes it easier to improve the electric field distribution gradient on the side of the first or second doped region near the communication region away from the silicon substrate, reducing the electric field peak at that location and shifting the electric field peak towards the silicon substrate side. This reduces the leakage current of the transistor and improves the transistor's mismatch performance. It can improve the brightness and darkness of the display panel and also improve display uniformity.
[0043] Furthermore, by grounding the first auxiliary gate 412 and the second auxiliary gate 422, the parasitic capacitance between the main gate 32 and the source region 211 is increased by the grounded first auxiliary gate 412, and the parasitic capacitance between the main gate 32 and the drain region 221 is increased by the grounded second auxiliary gate 422. The grounded first auxiliary gate 412 and the second auxiliary gate 422 can act as electric field shielding, which can reduce the side electric field strength between the main gate 32 and the source region 211 and between the main gate 32 and the drain region 221, thereby reducing the side parasitic capacitance between the main gate 32 and the source region 211 and between the main gate 32 and the drain region 221. This reduces the overall parasitic capacitance between the main gate 32 and the source region 211 and the drain region 221, improves the switching speed of the transistor, reduces the power consumption of the transistor, and can improve the display crosstalk problem of the display panel.
[0044] It should be noted that the above analysis only addresses the effects of the first auxiliary gate 412 and the second auxiliary gate 422 on the leakage current and parasitic capacitance of the transistor. The first auxiliary gate 412 and the second auxiliary gate 422 can also be understood as influencing the resistance within the transistor, as analyzed below: Since the resistivity of a doped semiconductor material is related to the carrier concentration within the doped semiconductor material, i.e., the higher the carrier concentration, the lower the resistivity, when the first auxiliary gate 412 and the second auxiliary gate 422 are electrically connected to the ground terminal, they can weaken the electric field between the drain region 221 and the channel region 23, or between the source region 211 and the channel region 23, reducing the amount of carrier migration towards the first auxiliary gate 412 and the second auxiliary gate 422, thereby reducing the amount of leakage current and parasitic capacitance in the well doped region 20 near the first auxiliary gate 412. The carrier concentration on the sides of 12 and the second auxiliary gate 422 increases the resistivity of the well doped region 20 near the first auxiliary gate 412 and the second auxiliary gate 422, thereby improving the spread resistance between the main gate structure 30 and the heavily doped drain region 221, as well as the spread resistance between the main gate structure 30 and the heavily doped source region 211, compared to the prior art. This makes it easier to improve the electric field distribution gradient on the side of the first or second doped region near the communication region away from the silicon substrate, which can reduce the electric field peak at that location and make the electric field peak move towards the silicon substrate side, thereby reducing the leakage current of the transistor and improving the brightness and darkness of the display panel.
[0045] The technical solution of this embodiment involves setting a second auxiliary gate structure on the side of the heavily doped drain region near the channel region along a direction parallel to the plane of the silicon substrate, and a first auxiliary gate structure on the side of the heavily doped source region near the channel region. The first auxiliary gate in the first auxiliary gate structure covering at least a portion of the first doped region is grounded, and the second auxiliary gate in the second auxiliary gate structure covering at least a portion of the second doped region is grounded. This allows the first and second auxiliary gate structures to provide grounding signals to the first and second doped regions on the side away from the silicon substrate when leakage current exists in the transistor. This increases the extended resistance of the heavily doped source region, and this resistance does not change with the operating voltage of the first and second doped regions. It also makes it easier to improve the electric field distribution gradient on the side of the first or second doped region near the communication region away from the silicon substrate, reducing the electric field peak value and causing the electric field peak value to shift towards the silicon substrate side. This, in turn, reduces the leakage current of the transistor and improves the mismatch performance of the transistor. In addition, grounding the first and second auxiliary gates can serve as an electric field shield, which can greatly reduce the side electric field strength between the main gate and the first or second doped region, thereby greatly reducing the parasitic side capacitance between the main gate and the first or second doped region, and further reducing the overall parasitic capacitance within the transistor. This can improve the bright and dark spots and crosstalk issues in the display panel, and also improve the display uniformity.
[0046] Optional, Figure 3 A schematic diagram of the structure of the second transistor provided in this embodiment of the present invention is shown below. Figure 3 As shown, the transistor also includes a gate isolation structure 50, which is located at least on the side surface of the first doped region 21 between the first auxiliary gate structure 41 and the main gate structure 30 that is away from the silicon substrate 10, and on the side surface of the second doped region 22 between the second auxiliary gate structure 42 and the main gate structure 30 that is away from the silicon substrate 10.
[0047] The gate isolation structure 50 includes insulating materials such as silicon dioxide or silicon nitride, which can be set according to actual needs, and no specific limitation is made here.
[0048] Specifically, by providing a gate isolation structure 50 between the first auxiliary gate structure 41 and the main gate structure 30, and by providing a gate isolation structure 50 between the second auxiliary gate structure 42 and the main gate structure 30, oxygen or water vapor is prevented from entering the main gate structure 30, the first doped region 21 located between the main gate structure 30 and the first auxiliary gate structure 41, and the second doped region 22 located between the main gate structure 30 and the second auxiliary gate structure 42 during subsequent heat treatment and other process processes. This protects the main gate structure 30, the first doped region 21, and the second doped region 22, thereby improving the reliability of transistor fabrication.
[0049] Optional, Figure 4 A schematic diagram of the structure of the third transistor provided in this embodiment of the present invention is shown below. Figure 4 As shown, the gate isolation structure 50 is also located on the side surface of the first doped region 21 between the first auxiliary gate structure 41 and the source heavily doped region 211 that is away from the silicon substrate 10, and on the side surface of the second doped region 22 between the second auxiliary gate structure 42 and the drain heavily doped region 221 that is away from the silicon substrate 10.
[0050] Specifically, by providing a gate isolation structure 50 between the first auxiliary gate structure 41 and the heavily doped source region 211, and by providing a gate isolation structure 50 between the second auxiliary gate structure 42 and the heavily doped drain region 221, oxygen or moisture is prevented from entering the first auxiliary gate structure 41, the second auxiliary gate structure 42, the first doped region 21 located between the first auxiliary gate structure 41 and the heavily doped source region 211, and the second doped region 22 located between the second auxiliary gate structure 42 and the heavily doped drain region 221 during subsequent process steps such as heat treatment. This protects the first auxiliary gate structure 41, the second auxiliary gate structure 42, the first doped region 21, and the second doped region 22, improves the fabrication reliability of the first auxiliary gate structure 41, the second auxiliary gate structure 42, the first doped region 21, and the second doped region 22, and thus improves the operational reliability of the transistor.
[0051] Optional, Figure 5 A schematic diagram of the structure of the fourth transistor provided in this embodiment of the present invention is shown below. Figure 5 As shown, the transistor also includes a source lead 61 and a drain lead 62; the source lead 61 covers a portion of the heavily doped source region 211; and the drain lead 62 covers a portion of the heavily doped drain region 221.
[0052] The source lead 61 and drain lead 62 are made of materials such as silver. Based on the fact that the source lead 61 can provide a source electrical signal to the heavily doped source region 211 and the drain lead 62 can receive a drain electrical signal provided by the heavily doped drain region 221, the materials of the source lead 61 and drain lead 62 can also be other materials, which can be set according to actual needs.
[0053] Specifically, by setting the source lead 61, after the source lead 61 is electrically connected to the source electrical signal providing terminal, the source lead 61 can transmit the source electrical signal to the heavily doped source region 211. When the voltage difference between the main gate structure 30 and the heavily doped source region 211 is greater than the threshold voltage of the transistor, the transistor is controlled to turn on. The source electrical signal on the side of the heavily doped source region 211 can be transmitted to the heavily doped drain region 221 through the first doping region 21, the channel region 23 and the second doping region 22. The heavily doped drain region 221 transmits the received electrical signal to other devices or lines through the drain lead 62, so that the transistor can realize electrical signal transmission.
[0054] Optional, Figure 6 A schematic diagram of the structure of the fifth transistor provided in this embodiment of the present invention is shown below. Figure 6 As shown, the transistor also includes a first ohmic contact structure 71 located between the heavily doped source region 211 and the source lead 61; and / or, a second ohmic contact structure 72 located between the heavily doped drain region 221 and the drain lead 62.
[0055] The materials of the first ohmic contact structure 71 and the second ohmic contact structure 72 may include at least one of the following metal silicides: titanium disilicide (TiSi2), cobalt silicide (CoSi2), nickel silicide (NiSi), tungsten disilicide (WSi2), etc., and can be set according to actual needs.
[0056] Specifically, the first ohmic contact structure 71 and the second ohmic contact structure 72 can be metal silicides formed by a chemical reaction between metal and silicon. Therefore, the resistivity of the first ohmic contact structure 71 and the second ohmic contact structure 72 is between that of metal and silicon, and less than that of polycrystalline silicon. The first ohmic contact structure 71 and the second ohmic contact structure 72 are formed by two annealing processes involving a metal layer and a silicon layer. During the fabrication process, residual oxygen and defects at the interface can be reduced, thereby lowering the contact resistance between the heavily doped source region 211 and the source lead 61, and / or the contact resistance between the heavily doped drain region 221 and the drain lead 62, thus improving the switching speed of the transistor.
[0057] Optional, Figure 7 A schematic diagram of the sixth transistor provided in this embodiment of the present invention is shown below. Figure 7 As shown, the transistor also includes a first auxiliary gate lead 43 and a second auxiliary gate lead 44. The first auxiliary gate lead 43 is electrically connected to the side of the first auxiliary gate 412 away from the silicon substrate 10 and the ground terminal GND, respectively. The second auxiliary gate lead 44 is electrically connected to the side of the second auxiliary gate 422 away from the silicon substrate 10 and the ground terminal GND, respectively.
[0058] The materials of the first auxiliary gate lead 43 and the second auxiliary gate lead 44 may include tungsten. Based on the fact that the first auxiliary gate lead 43 can provide a grounding signal to the first auxiliary gate 412 and the second auxiliary gate lead 44 can provide a grounding signal to the second auxiliary gate 422, the materials of the first auxiliary gate lead 43 and the second auxiliary gate lead 44 may also be other materials, which can be set according to actual needs.
[0059] Specifically, by setting a first auxiliary gate lead 43 electrically connected to the ground terminal GND and the first auxiliary gate 412 respectively, and a second auxiliary gate lead 44 electrically connected to the ground terminal GND and the second auxiliary gate 422 respectively, the conductivity of the first auxiliary gate lead 43 can be greater than that of the first auxiliary gate 412, and the conductivity of the second auxiliary gate lead 44 can be greater than that of the second auxiliary gate 422, so as to provide a grounding signal to the first auxiliary gate 412 through the first auxiliary gate lead 43 and to provide a grounding signal to the second auxiliary gate 422 through the second auxiliary gate lead 44, thereby improving the stability and reliability of the first auxiliary gate 43 and the second auxiliary gate 44 in receiving the grounding signal.
[0060] Optional, Figure 8 A schematic diagram of the structure of the seventh transistor provided in this embodiment of the present invention is shown below. Figure 8As shown, the transistor also includes a third ohmic contact structure 73, a fourth ohmic contact structure 74, and a fifth ohmic contact structure 75. The third ohmic contact structure 73 is located between the first auxiliary gate 412 and the first auxiliary gate lead 43; the fourth ohmic contact structure 74 is located between the second auxiliary gate 422 and the first auxiliary gate lead 44; and the fifth ohmic contact structure 75 is located on the side of the main gate 32 away from the silicon substrate 10.
[0061] The materials of the third ohmic contact structure 73, the fourth ohmic contact structure 74, and the fifth ohmic contact structure 75 may include at least one of the following metal silicides: titanium disilicide (TiSi2), cobalt silicide (CoSi2), nickel silicide (NiSi), and tungsten disilicide (WSi2), and can be set according to actual needs.
[0062] Specifically, the third ohmic contact structure 73, the fourth ohmic contact structure 74, and the fifth ohmic contact structure 75 can be metal silicides formed by a chemical reaction between metal and silicon. Therefore, the resistivity of the third ohmic contact structure 73, the fourth ohmic contact structure 74, and the fifth ohmic contact structure 75 is between that of metal and silicon, and less than that of polycrystalline silicon. The third ohmic contact structure 73, the fourth ohmic contact structure 74, and the fifth ohmic contact structure 75 are formed by a metal layer and a silicon layer through two annealing processes. During the preparation process, the residual oxygen and defects at the interface can be reduced, thereby reducing the contact resistance between the first auxiliary gate 412 and the first auxiliary gate lead 43, the contact resistance between the second auxiliary gate 422 and the first auxiliary gate lead 44, and the contact resistance between the main gate 32 and the signal line that provides the gate control signal to the main gate 32, thus improving the switching speed of the transistor.
[0063] Optional, Figure 9 A schematic diagram of the structure of the eighth transistor provided in this embodiment of the present invention is shown below. Figure 9 As shown, the silicon substrate 10 also includes an isolation region 80; in the same transistor, the isolation region 80 is located at least on the side of the first doped region 21 away from the channel region 23, and on the side of the second doped region 22 away from the channel region 23.
[0064] The material of the isolation zone 80 includes insulating materials such as silicon dioxide. The isolation zone 80 can be a shallow trench isolation, which is formed by etching and filling with materials such as silicon dioxide. It can be set according to actual needs.
[0065] Specifically, by setting an isolation region 80 on the side of the first doped region 21 away from the channel region 23, and setting an isolation region 80 on the side of the second doped region 22 away from the channel region 23, the transistor located between two adjacent isolation regions 80 is isolated from another transistor or electronic device that is away from the transistor by the isolation region 80. This prevents the transistor or electronic device adjacent to the transistor from affecting the operating parameters of the transistor, reduces interference and cross-coupling effects between devices, and improves the operating reliability of the transistor.
[0066] Based on the same inventive concept, this utility model also provides a display panel, which includes at least one transistor provided in any embodiment of this utility model. Therefore, this display panel possesses the technical features of the transistor provided in the embodiments of this utility model and can achieve the beneficial effects of the transistor provided in the embodiments of this utility model. Similarities can be found in the above description of the transistor provided in the embodiments of this utility model, and will not be repeated here.
[0067] Optional, Figure 10 A schematic diagram of the structure of the ninth type of display panel provided in this embodiment of the present utility model is shown below. Figure 10 As shown, the display panel also includes a light-emitting device 91 and a driving circuit 92; the driving circuit 92 is electrically connected to the light-emitting device 91; the driving circuit 91 includes at least one transistor.
[0068] Among them, the light-emitting device 91 includes devices such as Micro LED or mini LED, and the driving circuit 92 may include pixel circuit or other control circuit, which can be set according to actual needs, and no specific limitation is made here.
[0069] Specifically, the driving circuit 92 can provide a driving signal to the light-emitting device 91 to drive the light-emitting device 91 to display light emission. The driving circuit 92 may include active devices and / or passive devices. Active devices include transistors, and passive devices include resistors, capacitors, inductors, etc. Provided that the driving circuit 92 can drive the light-emitting element to display light emission, the specific structure of the driving circuit 92 in this embodiment of the invention is not limited. By setting the driving circuit 92 to include the transistors provided in any embodiment of the invention, when the light-emitting device 90 is controlled to be in a non-light-emitting state by the transistors in the driving circuit 92, problems such as leakage current generated in the transistors causing the light-emitting device 90 to emit light erroneously can be prevented, thus ensuring the reliability of the light emission of the display panel.
[0070] It should be noted that the number of transistors in the driving circuit 92 is related to the structure of the driving circuit 92. When the driving circuit 92 is a pixel circuit, the driving circuit 92 may include 7 transistors, 13 transistors, or 14 transistors, or other types, without specific limitations here.
[0071] Based on the same inventive concept, this utility model embodiment also provides a display device. Figure 11 This is a schematic diagram of the structure of a display device provided in an embodiment of the present utility model, as shown below. Figure 11 As shown, the display device 200 includes the display panel 100 in the above embodiments. Therefore, the display device 200 provided in this embodiment also possesses the beneficial effects of the display panel 100 described in the above embodiments, which will not be repeated here. For example, the display device 200 can be an AR (Augmented Reality) display device, a VR (Virtual Reality) display device, a mobile phone, a computer, or a television, or other electronic display devices.
[0072] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the protection scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments. Many other equivalent embodiments may be included without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims
1. A transistor, characterized in that, include: A silicon-based substrate includes a well-doped region, wherein the well-doped region is provided with a first doped region, a second doped region, and a channel region located between the first doped region and the second doped region; a heavily doped source region is provided in the first doped region, and a heavily doped drain region is provided in the second doped region; along a direction parallel to the plane of the silicon-based substrate, the heavily doped source region is located on the side of the first doped region away from the channel region, and the heavily doped drain region is located on the side of the second doped region away from the channel region; A main gate structure that at least covers the channel region; the main gate structure includes a main gate insulating structure and a main gate located on the side of the main gate insulating structure facing away from the silicon substrate; A first auxiliary gate structure covers a portion of the first doped region; Along a direction parallel to the plane of the silicon substrate, the first auxiliary gate structure is located on the side of the first doped region closer to the channel region; the first auxiliary gate structure includes a first gate insulating structure and a first auxiliary gate located on the side of the first gate insulating structure opposite to the silicon substrate; A second auxiliary gate structure covers a portion of the second doped region; Along a direction parallel to the plane of the silicon substrate, the second auxiliary gate structure is located on the side of the second doped region closer to the channel region; the second auxiliary gate structure includes a second gate insulating structure and a second auxiliary gate located on the side of the second gate insulating structure opposite to the silicon substrate; Both the first auxiliary gate and the second auxiliary gate are electrically connected to the ground terminal.
2. The transistor according to claim 1, characterized in that, Also includes: A gate isolation structure, wherein at least one of the first doped regions located between the first auxiliary gate structure and the main gate structure is on the side of the silicon substrate facing away from the first doped region, and the other of the second doped region located between the second auxiliary gate structure and the main gate structure is on the side of the silicon substrate facing away from the first doped region.
3. The transistor according to claim 2, characterized in that, The gate isolation structure is also located on the side surface of the first doped region facing away from the silicon substrate between the first auxiliary gate structure and the heavily doped source region, and on the side surface of the second doped region facing away from the silicon substrate between the second auxiliary gate structure and the heavily doped drain region.
4. The transistor according to claim 1, characterized in that, Also includes: Source leads and drain leads; The source lead covers a portion of the heavily doped source region; the drain lead covers a portion of the heavily doped drain region.
5. The transistor according to claim 4, characterized in that, Also includes: The first ohmic contact structure is located between the heavily doped source region and the source lead; And / or, The second ohmic contact structure is located between the heavily doped drain region and the drain lead.
6. The transistor according to claim 1, characterized in that, Also includes: The first auxiliary gate lead is electrically connected to the side of the first auxiliary gate away from the silicon substrate and the ground terminal, respectively. The second auxiliary gate lead is electrically connected to the side of the second auxiliary gate away from the silicon substrate and the ground terminal, respectively.
7. The transistor according to claim 6, characterized in that, Also includes: A third ohmic contact structure is located between the first auxiliary gate and the first auxiliary gate lead; A fourth ohmic contact structure is located between the second auxiliary gate and the second auxiliary gate lead; The fifth ohmic contact structure is located on the side of the main gate opposite to the silicon substrate.
8. The transistor according to claim 1, characterized in that, The silicon-based substrate further includes an isolation region; In the same transistor, the isolation region is located at least on the side of the first doped region away from the channel region, and on the side of the second doped region away from the channel region.
9. A display panel, characterized in that, include: At least one transistor according to any one of claims 1 to 8.
10. The display panel according to claim 9, characterized in that, Also includes: Light-emitting devices and driving circuits; The driving circuit is electrically connected to the light-emitting device; The driving circuit includes at least one of the transistors.
11. A display device, characterized in that, Includes the display panel as described in any one of claims 9 to 10.