Chip package structure
By introducing stepped sections and molding compound designs into the chip packaging structure, the problem of excessively large packaging structures caused by wire bonding is solved, achieving a compact chip packaging structure and effective connection.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- CHINA WAFER LEVEL CSP
- Filing Date
- 2025-06-26
- Publication Date
- 2026-07-14
AI Technical Summary
In existing technologies, wire bonding results in excessively large package sizes when applied to stacked chip packaging.
The chip packaging structure includes a circuit board, a first chip structure and a second chip structure stacked sequentially. By setting a plastic encapsulation and a first rewiring layer on the side of the first chip structure, electrical connection is achieved using a stepped portion and a second pad, reducing the space occupied by wires.
By using wire bonding and stepped design, the size of the chip packaging structure was reduced, space utilization was improved, and an effective connection between the first chip structure and the circuit board was achieved.
Smart Images
Figure CN224503945U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor packaging and testing, and in particular to a chip packaging structure. Background Technology
[0002] In the field of semiconductor packaging and testing, through-silicon via (TSV) technology is widely used for vertical interconnects between chips and between chips and substrates. To ensure the electrical performance of vertical interconnects using TSV technology, there are generally requirements for silicon thickness. When the silicon thickness design of a product does not meet the requirements of TSV technology, existing technologies can use wire bonding to replace TSV to achieve electrical connections between chips and between chips and substrates. However, when wire bonding is applied to stacked chip package structures, it leads to excessively large stacked chip package structures. Utility Model Content
[0003] One of the objectives of this invention is to provide a chip packaging structure to solve the technical problem that wire bonding in the prior art results in a large package size when applied to stacked chip packaging.
[0004] To achieve one of the above-mentioned objectives, one embodiment of this utility model provides a chip packaging structure, including a circuit board, a first chip structure, and a second chip structure stacked sequentially. The chip packaging structure includes a molding compound disposed on the side of the first chip structure and a first redistribution layer disposed on the surface of the first chip structure, with the first redistribution layer facing the second chip structure. The molding compound includes a stepped portion lower than the surface of the first chip structure. The first redistribution layer extends from the first chip structure to the molding compound. The first redistribution layer includes a first pad formed on the first chip structure and a second pad formed on the stepped portion. The first pad is used for electrical connection with the second chip structure, and the second pad is used for connection with the circuit board wires.
[0005] As a further improvement of one embodiment of the present invention, the encapsulation body includes a first encapsulation body and a second encapsulation body disposed on opposite sides of the first chip structure.
[0006] As a further improvement of one embodiment of the present invention, the stepped portion and the second pad are formed on the first molding compound, or the stepped portion and the second pad are formed on the first molding compound and the second molding compound.
[0007] As a further improvement of one embodiment of the present invention, the size of the first chip structure is smaller than that of the second chip structure.
[0008] As a further improvement of one embodiment of the present invention, the stepped portion includes a transition surface and a horizontal surface, the horizontal surface being lower than the surface of the first chip structure, the transition surface connecting the horizontal surface and the surface of the first chip structure, the second pad extending to the horizontal surface, and the wire being soldered to the second pad corresponding to the horizontal surface.
[0009] As a further improvement of one embodiment of the present invention, the transition surface includes an inclined plane.
[0010] As a further improvement of one embodiment of the present invention, the highest point corresponding to the wire does not exceed the first pad.
[0011] As a further improvement of one embodiment of the present invention, the circuit board includes a mounting surface for mounting the first chip structure and a fourth pad formed on the mounting surface, wherein the second pad and the fourth pad are connected by wires; the chip packaging structure includes a covering structure that encapsulates the second pad, the fourth pad and the wires.
[0012] As a further improvement of one embodiment of the present invention, the surface of the covering structure facing the second chip structure does not exceed the first wiring layer.
[0013] As a further improvement of one embodiment of the present invention, the fourth pad is located on the outside of the molding compound and is spaced apart from the molding compound.
[0014] Compared with the prior art, the present invention provides a chip packaging structure in which a first chip structure and a circuit board are connected by wire bonding. The silicon thickness of the first chip structure is not limited. The molding compound has a stepped portion lower than the first chip structure. The first redistribution layer includes a first pad located on the first chip structure and a second pad located on the stepped portion. After the second pad and the circuit board are connected by wire bonding, the space occupied by the wires can be reduced, thereby reducing the size of the chip packaging structure. Attached Figure Description
[0015] Figure 1 This is a schematic diagram of the chip packaging structure in the first embodiment of this utility model.
[0016] Figure 2 This is a schematic diagram of the chip packaging structure in the second embodiment of this utility model.
[0017] Figure 3 This is a schematic diagram of the chip packaging structure in the third embodiment of this utility model.
[0018] Figure 4-5 This is a schematic diagram of the chip packaging method in the first embodiment of this utility model.
[0019] Figure 6-7This is a schematic diagram of the chip packaging method in the second embodiment of this utility model.
[0020] Figure 8-9 This is a schematic diagram of the chip packaging method in the third embodiment of this utility model.
[0021] Figure 10 This is a schematic diagram of a heavy component provided in one embodiment of the present invention. Detailed Implementation
[0022] The present invention will now be described in detail with reference to the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional modifications made by those skilled in the art based on these embodiments are included within the protection scope of the present invention.
[0023] It should be noted that the term "comprising" or any other variation thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Furthermore, the terms "first," "second," "third," "fourth," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0024] The terms “connection,” “connected to,” or any other variations are intended to encompass various relative positions where a connection exists, including both direct and indirect connections. A direct connection can be formed through a pneumatic conduit, while an indirect connection can be formed through devices such as valves or sensors, through pneumatic components such as brake control units, or through any other medium such as air.
[0025] Please see Figure 1 This is a schematic diagram of a chip packaging structure 100 provided in an embodiment of the present invention. The chip packaging structure 100 includes a circuit board 10, a first chip structure 30 and a second chip structure 50 stacked sequentially. The circuit board 10 is electrically connected to the first chip structure 30, and the first chip structure 30 is electrically connected to the second chip structure 50, so as to achieve the performance of multi-chip stacking and interconnection.
[0026] The first chip structure 30 is located between the circuit board 10 and the second chip structure 50. Both sides of the first chip structure 30 facing the circuit board 10 and the second chip structure 50 need to be connected and packaged. In the prior art, the first chip structure 30 and the second chip structure 50 are usually different types of chips, and the first chip structure 30 and the second chip structure 50 have different sizes. Using wafer-level bonding packaging between the first chip structure 30 and the second chip structure 50 would waste area and result in a large package structure size.
[0027] The chip package structure 100 includes a molding compound 40 disposed on the side of the first chip structure 30, and a first redistribution layer 31 disposed on the surface of the first chip structure 30, the first redistribution layer 31 facing the second chip structure 50. The first redistribution layer 31 includes a first pad 311 for electrically connecting the second chip structure 50 and a second pad 312 for electrically connecting the circuit board 10.
[0028] The second chip structure 50 includes a third pad 51, which faces the first chip structure 30 and corresponds to the first pad 311 for electrical connection. Specifically, the first pad 311 and the third pad 51 can be bonded together via conductive bumps. In other embodiments, the first pad 311 and the third pad 51 can also be connected in a one-to-one correspondence using mixed bonding.
[0029] The circuit board 10 has a mounting surface 11 for mounting the first chip structure 30. The first chip structure 30 is mounted on the mounting surface 11 on the side opposite to the first redistribution layer 31. The circuit board 10 has a fourth pad 12 on its mounting surface 11, which is used to electrically connect to the second pad 312.
[0030] The fourth pad 12 is located outside the molding compound 40 and is spaced apart from the molding compound 40. The circuit board 10 provides sufficient installation space and wire bonding space for the first chip structure 30 and the molding compound 40.
[0031] The molding compound 40 includes a stepped portion 41 that is lower than the surface of the first chip structure 30. The first redistribution layer 31 extends from the first chip structure 30 to the molding compound 40. The first redistribution layer 31 includes a first pad 311 formed on the first chip structure 30 and a second pad 312 formed on the stepped portion 41. The first pad 311 is used to electrically connect to the second chip structure 50, and the second pad 312 is used to connect to the electrical wires of the circuit board 10.
[0032] Thus, the first chip structure 30 and the circuit board 10 are connected by wire bonding, and the silicon thickness of the first chip structure 30 is not limited, allowing for freedom in silicon thickness control. The stepped portion 41 is lower than the surface of the first chip structure 30, and the second pad 312 is formed on the stepped portion 41. After wire bonding, the position of the highest point of the electric arc is lowered, reducing the space occupied by the wires between the first chip structure 10 and the second chip structure 50, thereby facilitating the miniaturization of the chip package structure size.
[0033] In one embodiment, the size of the first chip structure 30 is smaller than the size of the second chip structure 50, and the first chip structure 30 is located between the second chip structure 50 and the circuit board 10. It is understood that if wires are directly connected between the first chip structure 30 and the circuit board 10, the wires would need to be routed to the surface of the first chip structure 30, increasing the space occupied above the first chip structure 30.
[0034] This application features a molding compound 40, which fully utilizes the horizontal space outside the second chip structure 50, which is larger than the first chip structure 30, without occupying the height space between the first chip structure 30 and the second chip structure 50, thus improving the utilization rate of limited space. This application also features a stepped portion 41, further lowering the position of the highest point of the wires and saving space for the installation of the second chip structure 50.
[0035] In one embodiment, the size of the combined first chip structure 30 and the molding compound 40 is no larger than the size of the second chip structure 50. It is understood that the molding compound 40 extends outwards to ensure it does not exceed the periphery of the second chip structure 50, which also helps to reduce the size of the stacked chip package structure. In other embodiments, to facilitate wire bonding, the molding compound 40 is made appropriately larger, and the size of the combined first chip structure 30 and the molding compound 40 appropriately exceeds the size of the second chip structure 50, which is also feasible.
[0036] The chip packaging structure 100 includes a dielectric layer 32 disposed between the surface of the first chip structure 30 and the first redistribution layer 31. In other words, the first redistribution layer 31 is formed on the surface of the dielectric layer 32, which can prevent the metal material of the first redistribution layer 31 from diffusing into the first chip structure 30, and also serves to insulate between the first redistribution layer 31 and the first chip structure 30.
[0037] Combination Figure 1 As shown, in the first embodiment of this application, the dielectric layer 32 extends from the surface of the first chip structure 30 to the surface of the molding compound 40, and the first redistribution layer 31 is completely formed on the surface of the dielectric layer 32.
[0038] Combination Figure 2As shown, the difference between the second embodiment and the first embodiment of this application is that in the second embodiment, the dielectric layer 32 covers the surface of the first chip structure 30, but does not completely cover the surface of the molding compound 40. Specifically, the area corresponding to the step portion 41 has no dielectric layer 32; in other words, the second pad 312 is formed directly on the step portion 41, instead of being formed on the dielectric layer 32 as in the first embodiment. It is understood that the other structures of the second embodiment of this application are completely consistent with the first embodiment.
[0039] The molding compound 40 includes a first molding compound 401 and a second molding compound 402 disposed on opposite sides of the first chip structure 30. It can be understood that when the first chip structure 30 is rectangular, the first chip structure 30 includes two pairs of opposite sides, and each pair of opposite sides can be correspondingly formed with a first molding compound 401 and a second molding compound 402.
[0040] The stepped portion 41 and the second pad 312 are formed on the first molding compound 401, and are combined Figure 1 As shown, in the first embodiment of this application, the second molding compound 402 is shorter and does not form a stepped portion 41 structure, nor does it have a corresponding first superwiring layer 31. Only the first molding compound 401 forms a stepped portion 41 structure and a corresponding first superwiring layer 31, which meets the requirements of the actual product and the solder pads of the circuit board 10.
[0041] The stepped portion 41 and the second pad 312 are formed on the first molding compound 401 and the second molding compound 402, and are combined with Figure 3 As shown, the difference between the third embodiment and the first embodiment of this application is that: the first chip structure 30 has symmetrical first molding compound 401 and second molding compound 402 formed on opposite sides, and both the first molding compound 401 and the second molding compound 402 have stepped portions 41 and second pads 312, which is beneficial to the stress balance of the overall chip packaging structure 100.
[0042] In the third embodiment of this application, when the first chip structure 30 has second pads 312 on both opposite sides, the mounting surface 11 of the circuit board also has fourth pads 12 corresponding to the second pads 312 on both opposite sides. It is understood that the other structures of the third embodiment of this application are completely consistent with the first embodiment.
[0043] The stepped portion 41 includes a transition surface 411 and a horizontal surface 412. The horizontal surface 412 is lower than the surface of the first chip structure 30. The transition surface 411 connects the horizontal surface 412 and the surface of the first chip structure 30. The second pad 312 extends to the horizontal surface 412, and the wire 60 is soldered to the second pad corresponding to the horizontal surface 412. The second pad 312 at the horizontal surface 412 is located at the lowest point. The horizontal shape of the second pad 312 facilitates wire bonding and can lower the position of the highest point of the wire 60.
[0044] The transition surface 411 includes an inclined plane, and the two ends of the transition surface 411 are respectively used to connect the horizontal surface 412 and the surface of the first chip structure 30.
[0045] Combination Figure 1 As shown, specifically, the molding compound 40 includes a top surface, which is a horizontal surface and flush with the surface of the first chip structure 30. The surface of the first chip structure 30 is horizontally connected to the top surface of the molding compound 40, the top surface of the molding compound 40 is connected to a transition surface 411, and the transition surface 411 is connected to a horizontal surface 412, forming a complete and continuous surface, which facilitates the subsequent fabrication of the first redistribution layer 31.
[0046] Combination Figure 1 , 3 As shown, in the first and third embodiments of this application, the dielectric layer 32 extends from the surface of the first chip structure 30 to the top surface of the molding compound 40, and then to the transition surface 411 and the horizontal surface 412 of the step portion 41. The first redistribution layer 31 extends from the surface of the first chip structure 30 to the top surface of the molding compound 40, and then to the transition surface 411 and the horizontal surface 412 of the step portion 41.
[0047] Combination Figure 2 As shown, in the second embodiment of this application, the dielectric layer 32 extends from the surface of the first chip structure 30 to the top surface of the molding compound 40, but does not extend further to the step portion 41. The first redistribution layer 31, however, extends from the surface of the first chip structure 30 to the top surface of the molding compound 40, then to the transition surface 411 and the horizontal surface 412 of the step portion 41. Therefore, the second pad 312 is directly formed on the step portion 41, which can also appropriately lower the position of the highest point of the wire 60.
[0048] The highest point of the wire 60 does not exceed the first pad 311. The depth of the step portion 41 should be such that when the wire 60 is soldered to the second pad 312, the highest point of the arc formed by the wire 60 is lower than the first pad 311, so that the subsequent covering structure will not be too high. Otherwise, it will affect the electrical connection between the first pad 311 and the second chip structure 50.
[0049] The second pad 312 and the fourth pad 12 are connected by a wire 60. The chip package structure includes a covering structure 70 that encloses the second pad 312, the fourth pad 12 and the wire 60 to ensure good connection performance between the second pad 312, the fourth pad 12 and the wire 60, and to protect the second pad 312, the fourth pad 12 and the wire 60.
[0050] The surface of the covering structure 70 facing the second chip structure 50 does not exceed the first overlay layer 31. In other words, the covering structure 70 is flush with or lower than the first pad 311. Otherwise, the covering structure 70 will overflow the first pad 311, affecting the electrical connection between the first pad 311 and the second chip structure 50.
[0051] This application also provides a chip packaging method, combined with Figure 4-5 As shown, it includes the following steps:
[0052] S1: A recombinant component 200 integrating a plurality of first chip structures 30 is provided, the recombinant component 200 including a molding compound 40 connecting the plurality of first chip structures 30. (Combined with...) Figure 4 As shown, several first chip structures 30 are recombined and encapsulated to obtain the recombinant component 200.
[0053] Combination Figure 10 As shown, the heavy component 200 integrating a plurality of first chip structures 30 includes: dicing a wafer to obtain a plurality of individual first chip structures 30; providing a carrier board to transfer the plurality of first chip structures 30 to the carrier board, wherein the plurality of first chip structures 30 maintain equal spacing between them; and encapsulating the first chip structures 30 on the carrier board with adhesive.
[0054] It is understood that the method steps for providing a heavy component 200 integrating a plurality of first chip structures 30 are consistent in the first, second and third embodiments of this application.
[0055] Each first chip structure 30 has a pad area exposed on the side away from the carrier board. The side of the first chip structure 30 away from the carrier board is used for subsequent fabrication of a first rewiring layer 31. The pad area is used for electrical connection to the first rewiring layer 31 to connect the first chip structure 30 to the circuit board 10.
[0056] S2: A second chip structure 50 and a circuit board 10 are provided. The second chip structure 50 has a third pad 51, and the circuit board 10 has a fourth pad 12. It is understood that there is no specific order among the above-mentioned components 200, the second chip structure 50, and the circuit board 10.
[0057] S3: Cut the molding compound 40 to form a groove 410 on its surface; combine Figure 4As shown, the longitudinal section of the groove 410 is trapezoidal. During actual cutting, the corresponding cutting head can be selected according to the required shape of the groove 410.
[0058] S4: Fabricate a first redistribution layer 31; the first redistribution layer 31 includes a first pad 311 formed on the surface of the first chip structure 30 and a second pad 312 formed in the groove 410.
[0059] Before fabricating the first wiring layer 31, the chip packaging method includes: fabricating a dielectric layer 32.
[0060] Combination Figure 4-5 As shown in Figures 8-9, in the first and third embodiments of this application, the dielectric layer 32 is fabricated after the molding compound 40 is cut. Thus, during the fabrication of the dielectric layer 32, the groove 410 is already formed. The dielectric layer 32 covers the surface of the first chip structure 30 and the surface of the groove 410. The groove 410 will subsequently be cut to form a stepped portion 41. The dielectric layer 32 has a wide coverage area, completely blocking the space between the first redistribution layer 31 and the first chip structure 30.
[0061] Combination Figure 6-7 As shown, in the second embodiment of this application, the dielectric layer 32 is fabricated before the molding compound 40 is cut. Therefore, the absence of the groove 410 is more conducive to the formation of the dielectric layer 32. After the dielectric layer 32 is fabricated, the molding compound 40 is cut, and the dielectric layer 32 is also cut away at the location where the groove 410 is formed. Subsequently, when fabricating the first multi-level wiring layer 31, the first multi-level wiring layer 31 at the groove 410 is formed directly on the groove surface instead of the dielectric layer 32.
[0062] The chip packaging method includes the steps of: cutting the heavy component 200, wherein the molding compound 40 is cut into a first molding compound 401 and a second molding compound 402. Each first chip structure 30 retains the first molding compound 401 and the second molding compound 402 on opposite sides.
[0063] Cutting the heavy component 200 includes: cutting the heavy component 200 along a cutting path located within the groove 410, with only the first molding compound 401 retaining a portion of the groove structure. (Combined) Figure 4-5 As shown in 6-7, the cutting path is biased to one side, the groove 410 is cut to form a stepped portion 41, and only the first plastic seal 401 retains the stepped portion 41.
[0064] In the first and second embodiments of this application, the molding compound 40 is defined with a cleaving track offset from the middle position of two adjacent chip structures 30, and the second pad 312 is distributed on one side of the cleaving track. Thus, when the heavy component 200 is cut along the cleaving track, the molding compound 40 is cut into a first molding compound 401 and a second molding compound 402 of different sizes. The first molding compound 401 is longer than the second molding compound 402, thereby retaining the stepped portion 41 and the second pad 312.
[0065] Cutting the heavy component 200 includes: cutting the heavy component 200 along a cutting path located within the groove 410, wherein the first molding compound 401 and the second molding compound 402 each retain a portion of the groove structure. (Combined) Figure 8-9 As shown, the cutting channel is located in the middle of the two first chip structures 30. The groove 410 is cut to form two symmetrical stepped portions 41. Both the first molding compound 401 and the second molding compound 402 retain the stepped portions 41.
[0066] In the third embodiment of this application, the molding compound 40 defines a cleaving channel located between two adjacent first chip structures 30, and the second pads 312 are distributed on both sides of the cleaving channel. Thus, when the heavy component 200 is cut along the cleaving channel, the molding compound 40 is cut into a first molding compound 401 and a second molding compound 402 of the same size, and the first molding compound 401 and the second molding compound 402 respectively retain the stepped portion 41 and the second pad 312.
[0067] S5: Wire bonding is performed between the first chip structure 30 and the circuit board 10, with the circuit board 10 facing away from the first redistribution layer 31; the circuit board 10 includes a fourth pad 12 located on its mounting surface, and wires connect the second pad 312 and the fourth pad 12. Thus, the first chip structure 30 is connected to the circuit board 10.
[0068] Specifically, the first chip structure 30 is attached to the mounting surface 11 of the circuit board 10, and wire-connected to the second pad 312 and the fourth pad 12. It is understood that when the first chip structure 30 is rectangular, in the first and second embodiments, each pair of opposite sides of the first chip structure 30 corresponds to a first molding compound 401, and only the first molding compound has a second pad 312 formed thereon, so that only two sides of the four sides of the first chip structure 30 are wire-connected to the circuit board 10. In the third embodiment, both the first molding compound 401 and the second molding compound 402 have second pads 312 formed thereon, so that all four sides of the first chip structure 30 should be wire-connected to the circuit board 10.
[0069] S51: After wire bonding the first chip structure 30 and the circuit board 10, the following is included: plastic encapsulating the wire 60, the second pad 312 and the fourth pad 12.
[0070] The adhesive filler forms an encapsulation structure 70, which encapsulates the wire 60, the second solder pad 312, and the fourth solder pad 12. The encapsulation structure 70 fills the space of the stepped portion 41, the outer side of the encapsulation body 40, and the upper side of the mounting surface 11.
[0071] It is understood that the cutting of the heavy component 200 is done before wire bonding the first chip structure 30 and the circuit board 10, as a single first chip structure 30 is easier to wire bond.
[0072] S6: The first chip structure 30 and the second chip structure 50 are bonded together; the first pad 311 is connected to the second chip structure 50, and the second chip structure 50 faces the first redistribution layer 31. Thus, the second chip structure 50, the first chip structure 30, and the circuit board 10 are stacked and interconnected. Specifically, a conductive bump is formed on the first pad 311, and a third pad 51 is aligned with the conductive bump and electrically connected to the conductive bump and the third pad 51.
[0073] The packaging methods of the chip packaging structure 100 in the first, second and third embodiments of this application will be briefly described below.
[0074] Combination Figure 4-5 As shown, a heavy component 200 is provided; a molding compound 40 is cut to form a groove 410; a dielectric layer 32 is fabricated, the dielectric layer 32 exposing the pad area of the first chip structure 30, the dielectric layer 32 extending into the groove 410; a first redistribution layer 31 is fabricated on the surface of the dielectric layer 32; the heavy component 200 is cut to obtain a plurality of individual first chip structures 30, each first chip structure 30 having a first molding compound 401 and a second molding compound 402 on opposite sides, with a step portion 41 and a second pad 312 formed only at the first molding compound 401; the first chip structure 30 and the circuit board 10 are connected by wire bonding; the first chip structure 30 and the second chip structure 50 are connected by bonding.
[0075] Combination Figure 6-7 As shown, a heavy component 200 is provided; a dielectric layer 32 is fabricated, which exposes the pad area of the first chip structure 30; a molding compound 40 is cut to form a groove 410, and the dielectric layer 32 corresponding to the groove 410 is removed; a first redistribution layer 31 is fabricated on the surface of the dielectric layer 32 and the groove 410; the heavy component 200 is cut to obtain a plurality of individual first chip structures 30, each first chip structure 30 having a first molding compound 401 and a second molding compound 402 on opposite sides, with a step portion 41 and a second pad 312 formed only at the first molding compound 401; the first chip structure 30 and the circuit board 10 are connected by wire bonding; and the first chip structure 30 and the second chip structure 50 are connected by bonding.
[0076] Combination Figure 8-9As shown, a heavy component 200 is provided; a molding compound 40 is cut to form a groove 410; a dielectric layer 32 is fabricated, the dielectric layer 32 exposing the pad area of the first chip structure 30, the dielectric layer 32 extending into the groove 410; a first redistribution layer 31 is fabricated on the surface of the dielectric layer 32; the heavy component 200 is cut to obtain a plurality of individual first chip structures 30, each first chip structure 30 having a first molding compound 401 and a second molding compound 402 on opposite sides, the first molding compound 401 and the second molding compound 402 each correspondingly forming a step portion 41 and a second pad 312; wire bonding connects the first chip structure 30 and the circuit board 10; and bonding connects the first chip structure 30 and the second chip structure 50.
[0077] The beneficial effects of this utility model are as follows: the first chip structure 30 and the circuit board 10 are connected by wire bonding, and the silicon thickness of the first chip structure 30 is not limited; the step portion 41 is lower than the first chip structure 30, and the first redistribution layer 31 includes a second pad 312 located on the step portion 41. After the second pad 312 and the circuit board 10 are connected by wire bonding, the space occupied by the wire 60 can be reduced, thereby reducing the size of the chip package structure 100; the first chip structure 30 is smaller than the second chip structure 30, making full use of the space around the first chip structure 30 to form the molding compound 40 and the step portion 41.
[0078] This can be formed by referring to any of the technical solutions provided above, and will not be elaborated here.
[0079] It should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This way of describing the specification is only for clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.
[0080] The detailed descriptions listed above are merely specific descriptions of feasible implementations of this utility model, and are not intended to limit the scope of protection of this utility model. All equivalent implementations or modifications made without departing from the spirit of this utility model should be included within the scope of protection of this utility model.
Claims
1. A chip packaging structure, characterized in that, The package includes a circuit board, a first chip structure, and a second chip structure stacked sequentially. The chip packaging structure includes a molding compound disposed on the side of the first chip structure and a first redistribution layer disposed on the surface of the first chip structure, with the first redistribution layer facing the second chip structure. The molding compound includes a stepped portion lower than the surface of the first chip structure. The first redistribution layer extends from the first chip structure to the molding compound. The first redistribution layer includes a first pad formed on the first chip structure and a second pad formed on the stepped portion. The first pad is used for electrical connection with the second chip structure, and the second pad is used for connection with the circuit board wires.
2. The chip packaging structure according to claim 1, characterized in that, The encapsulation includes a first encapsulation and a second encapsulation disposed on opposite sides of the first chip structure.
3. The chip packaging structure according to claim 2, characterized in that, The stepped portion and the second pad are formed on the first molding compound, or the stepped portion and the second pad are formed on the first molding compound and the second molding compound.
4. The chip packaging structure according to claim 1, characterized in that, The size of the first chip structure is smaller than that of the second chip structure.
5. The chip packaging structure according to claim 1, characterized in that, The stepped portion includes a transition surface and a horizontal surface. The horizontal surface is lower than the surface of the first chip structure. The transition surface connects the horizontal surface and the surface of the first chip structure. The second pad extends to the horizontal surface. The wire is soldered to the second pad corresponding to the horizontal surface.
6. The chip packaging structure according to claim 5, characterized in that, The transition surface includes an inclined plane.
7. The chip packaging structure according to claim 1, characterized in that, The highest point corresponding to the wire does not exceed the first pad.
8. The chip packaging structure according to claim 1, characterized in that, The circuit board includes a mounting surface for mounting the first chip structure and a fourth pad formed on the mounting surface, wherein the second pad and the fourth pad are connected by wires; the chip package structure includes a covering structure that encloses the second pad, the fourth pad and the wires.
9. The chip packaging structure according to claim 8, characterized in that, The surface of the covering structure facing the second chip structure does not exceed the first wiring layer.
10. The chip packaging structure according to claim 8, characterized in that, The fourth pad is located on the outside of the molding compound and is spaced apart from the molding compound.