Wafer electrical testing device
By setting marking codes on the probe card and using images to acquire real-time updated parameter information of components and processors, the problem of probe card identification errors is solved, improving the accuracy and efficiency of wafer testing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SHANGHAI INTEGRATED CIRCUIT RESEARCH & DEVELOPMENT CENTER CO LTD
- Filing Date
- 2025-08-05
- Publication Date
- 2026-07-24
AI Technical Summary
In existing wafer acceptability testing, the RFID tags on probe cards are prone to falling off or shifting at high temperatures, leading to identification errors, increasing the time process engineers spend dealing with problems and causing misjudgments, thus affecting testing efficiency.
By directly setting the marker code on the probe card, acquiring the marker code through the image acquisition component, and having the processor read the parameter information, the status of the probe card is updated and judged in real time, thus avoiding the use of incorrect probe cards and reducing misjudgments and losses.
Accurately obtaining probe card parameter information reduces losses from misjudgments, saves process engineers time in troubleshooting, improves testing efficiency, and increases production capacity.
Smart Images
Figure CN224553428U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of integrated circuit chip testing technology, specifically relating to a wafer electrical testing device. Background Technology
[0002] In recent years, with the continuous advancement of integrated circuit technology, people have been able to manufacture integrated circuits with highly complex circuit structures, high integration levels, and diverse functions. Integrated circuit testing is one of the key links in ensuring the performance and quality of integrated circuits. The ultimate goal of testing is to verify whether the logic design, circuit design, layout design, and process design meet the predetermined requirements, thereby ensuring the quality and reliability of the IC products used.
[0003] In the semiconductor manufacturing process, hundreds of process steps are required. Wafer Acceptance Test (WAT) plays a crucial role in chip quality inspection and is an indispensable step in chip manufacturing. The purpose of WAT is to detect whether the wafer meets process specifications by performing electrical tests on specific test structures on the wafer. Besides determining the pass / fail status of the device under test, the test also provides useful information about the manufacturing process, thereby helping to improve yield, providing information about weaknesses in the design, and helping to detect design problems.
[0004] Probe cards are crucial components in wafer testing. They are printed circuit boards (PCBs) with numerous fine probes that make contact with the pads or bumps of the device under test (DUT) on the wafer. Different probe card models are typically designed for different types of chips, different sizes of pads or bumps, and different testing requirements. Using the wrong probe card can lead to poor contact, signal interference, or chip damage, affecting the accuracy of test results.
[0005] In existing technologies, the identification probe card used in wafer acceptability testing employs radio frequency identification (RFID) technology, such as... Figure 1 As shown, the RFID tag 231a is mounted on the probe card 23a via a plastic tray. However, the plastic tray is prone to falling off at high temperatures, and vibrations during wafer loading can easily cause the RFID tag to shift. This can lead to the RFID reader being unable to read the RFID tag when the plastic tray falls off. After the RFID tag shifts, the RFID reader may fail to recognize the RFID tag or the recognized RFID tag may have an inaccurate ID (i.e., it may be recognized as the ID of another probe card). This increases the time required for the PE (process engineer) to handle the problem and increases the loss caused by misjudgment of the probe card. Utility Model Content
[0006] The technical problem to be solved by this application is to provide a wafer electrical testing device. The wafer electrical testing device of this application can accurately acquire the parameter information of the probe card and update the parameter information in real time. It can save process engineers time in handling problems, reduce the loss caused by misjudgment information of the probe card, save the cost of handling problems, gain more time for wafer fabrication, improve testing efficiency, and increase production capacity.
[0007] This application provides a wafer electrical testing device, comprising: Wafer carrier mechanism, including a carrier platform for holding wafers; An electrical testing mechanism, located above the support platform, includes a test circuit board, a clamping assembly for fixing probe cards, and an image acquisition assembly. The test circuit board is electrically connected to each probe on the probe card, and the image acquisition assembly is used to acquire the marking codes on the probe card. The processor is signal-connected to the image acquisition component, and the processor obtains the parameter information of the probe card according to the tag code read by the image acquisition component.
[0008] Furthermore, there are multiple probe cards, and each probe card is affixed or sprayed with a marking code.
[0009] Furthermore, the image acquisition component is located on the test circuit board.
[0010] Furthermore, the test circuit board has a groove, and the image acquisition component is embedded in the groove.
[0011] Furthermore, the wafer electrical testing device also includes an alarm module, which is connected to the processor. When the processor determines that the probe card is in an abnormal state based on the parameter information of the probe card, it controls the alarm module to output an alarm signal.
[0012] Furthermore, the alarm module is a warning light and / or a voice module and / or a display screen.
[0013] Furthermore, the processor includes: The storage module is used to store the tag codes and parameter information of all probe cards; A signal transmission module is used to connect to the image acquisition component to receive the tag code fed back by the image acquisition component; The data processing module is used to obtain the parameter information of the corresponding probe card based on the feedback marking code, and update the number of times the probe card has been used in the parameter information.
[0014] Furthermore, the processor is connected to the probe card management system, which stores the tag codes and parameter information of all probe cards.
[0015] Furthermore, the parameter information includes the probe card model, manufacturing date, PM count, probe card contact count, leakage current of each needle, resistance of each needle, capacitance data of each needle, needle tip level of each needle, needle tip length of each needle, insertion depth of each needle, single row of needles, double row of needles, needle material of each needle, and probe card status. The probe card management system is used to receive the current probe card information fed back by the processor to update the number of times the probe card has been used in the parameter information.
[0016] Furthermore, the wafer electrical testing apparatus also includes a heating component disposed at the support platform, the heating component being used to heat the wafer.
[0017] The beneficial effects of this application are: The wafer electrical testing apparatus of this application includes an image acquisition component that acquires the marking codes on a probe card, and a processor that obtains the parameter information of the probe card based on the marking codes read by the image acquisition component. Therefore, before wafer testing, it is possible to determine whether the probe card has been manually misidentified, avoiding the use of incorrect probe cards that could lead to poor contact, signal interference, or chip damage, thus affecting the accuracy of test results. The parameter information corresponding to the marking codes on the probe card can be updated in a timely manner during the use of the probe card, thereby recording the usage frequency and wear condition of the probe card and providing a basis for developing reasonable maintenance, calibration, and replacement plans. The marking codes are directly pasted or sprayed onto the probe card, eliminating the need for a tray for setting RFID tags. This avoids the tray for setting RFID tags falling off under high temperatures and the RFID tags shifting due to vibration during wafer loading, which could lead to the inability to identify or accurately identify the probe card information, thereby increasing the time required for process engineers to handle problems. Therefore, this application can accurately obtain the parameter information of the probe card and update the parameter information in real time, which can save process engineers time in handling problems, reduce losses caused by misjudgment of probe card information, save the cost of problem handling, gain more time for tape-out, improve testing efficiency, and increase production capacity. Attached Figure Description
[0018] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.
[0019] Figure 1 A schematic diagram of the structure of a probe card using existing radio frequency identification technology; Figure 2This is a schematic diagram of the wafer electrical testing device in an embodiment of this disclosure; Figure 3 This is a schematic diagram of the structure of the carrying platform in an embodiment of this disclosure; Figure 4 This is a schematic diagram of the probe card structure in an embodiment of this disclosure; Figure 5 This is a block diagram of the processor in an embodiment of the present disclosure; Figure 6 This is a structural block diagram of a wafer electrical testing apparatus according to another embodiment of the present disclosure. Detailed Implementation
[0020] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.
[0021] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” indicate that the element or object preceding “comprising” or “including” encompasses the element or object listed following “comprising” or “including” and its equivalents, and do not exclude other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.
[0022] This disclosure provides a wafer electrical testing apparatus. The wafer electrical testing apparatus includes: A wafer carrier mechanism, including a carrier platform for holding wafers.
[0023] An electrical testing mechanism is located above the support platform. The electrical testing mechanism includes a test circuit board, a clamping component for fixing the probe card, and an image acquisition component. The test circuit board is used to electrically connect with each probe on the probe card, and the image acquisition component is used to acquire the marking code on the probe card.
[0024] The processor is signal-connected to the image acquisition component, and the processor obtains the parameter information of the probe card according to the tag code read by the image acquisition component.
[0025] The wafer electrical testing apparatus provided in the above embodiments of this disclosure includes an image acquisition component that acquires the marking codes on a probe card. The processor then uses these marking codes to obtain the probe card's parameter information. Therefore, before wafer testing, it is possible to determine if the probe card has been manually misidentified, preventing the use of incorrect probe cards that could lead to poor contact, signal interference, or chip damage, thus affecting the accuracy of test results. The parameter information corresponding to the marking codes on the probe card can be updated during its use, allowing for the recording of the probe card's usage frequency and wear condition, providing a basis for developing reasonable maintenance, calibration, and replacement plans. Since the marking codes are directly set on the probes, there is no need to install a tray for setting RFID tags on the probe card. This avoids the tray falling off under high temperatures and the RFID tags shifting due to vibration during wafer loading, which could lead to the probe card not being identified or accurately identified, thereby increasing the time required for process engineers to resolve the issue. Therefore, this application can accurately obtain the parameter information of the probe card and update the parameter information in real time, which can save process engineers time in handling problems, reduce losses caused by misjudgment of probe card information, save the cost of problem handling, gain more time for tape-out, improve testing efficiency, and increase production capacity.
[0026] The wafer electrical testing apparatus of this disclosure is described below by way of example with reference to the accompanying drawings.
[0027] Figure 2 This is a schematic diagram of the wafer electrical testing device in an embodiment of this disclosure. Figure 3 This is a schematic diagram of the structure of the carrier platform in an embodiment of this disclosure.
[0028] like Figure 2 As shown, the wafer electrical testing apparatus 100 includes: a wafer carrier (not shown), an electrical testing mechanism 20, and a processor 30.
[0029] like Figure 3 As shown, the wafer carrier mechanism includes a carrier platform 11 for holding the wafer 200. The wafer carrier mechanism can drive the carrier platform 11 to move forward, backward, left, right, up, and down, so that the chip die contact holes on the wafer 200 are aligned with the probes on the probe card 23, so as to test all the chips on the entire wafer one by one.
[0030] Specifically, such as Figure 3As shown, the wafer carrier mechanism further includes an X-axis driving component 12, a Y-axis driving component 13, and a Z-axis driving component 14. The X-axis driving component 12 drives the carrier platform 11 to reciprocate along the X-axis, the Y-axis driving component 13 drives the carrier platform 11 to reciprocate along the Y-axis, and the Z-axis driving component 14 drives the carrier platform 11 to reciprocate along the Z-axis. Specifically, the specific structures of the X-axis driving component 12, the Y-axis driving component 13, and the Z-axis driving component 14 can be any methods that can be implemented in the prior art, and will not be described in detail here.
[0031] The electrical testing unit 20 is located above the support platform 11. The electrical testing unit 20 is used for electrical testing of the wafer. The electrical testing unit 20 includes a test circuit board 21, a clamping assembly (not shown), and an image acquisition assembly 22. The clamping assembly is used to fix the probe card 23, the test circuit board 21 is used to electrically connect to each probe on the probe card 23, and the image acquisition assembly 22 is used to acquire the marking code 231 on the probe card 23.
[0032] Figure 4 This is a schematic diagram of the probe card structure in an embodiment of this disclosure.
[0033] like Figure 4 As shown, the marking code 231 is directly set on the probe card 23. For example, the marking code 231 is printed, sprayed, pasted or engraved on the probe card 23. Therefore, there is no need to install a tray for setting RFID tags on the probe card. This avoids the tray for setting RFID tags falling off under high temperature conditions and the RFID tags moving due to vibration when loading wafers, which would lead to the inability to identify or accurately identify the information on the probe card. This increases the time for process engineers to deal with problems, thereby saving the cost of problem handling, allowing more time for tape-out, improving testing efficiency and increasing production capacity.
[0034] Specifically, the tag code 231 can be a QR code, barcode, etc. It can be understood that the tag code only needs to be recognizable by the image acquisition component 22 and represent the unique ID of the probe card.
[0035] In some embodiments, there are multiple probe cards 23, and each probe card is provided with a marking code 231.
[0036] In some embodiments, the image acquisition component 22 is located on the test circuit board 21.
[0037] More specifically, the test circuit board 21 has a groove, and the image acquisition component 22 is embedded in the groove.
[0038] In some embodiments, the image acquisition component 22 is a CCD camera.
[0039] The processor 30 is signal-connected to the image acquisition component 22. The processor 30 obtains the parameter information of the probe card based on the tag code read by the image acquisition component 22. Specifically, the processor 30 identifies the ID of the probe card 23 based on the tag code 231 acquired by the image acquisition component 22, and retrieves the parameter information of the probe card 23 corresponding to that ID from the database. This allows the processor 30 to determine whether the probe card 23 matches the pads and the wafer to be tested, and whether it is a probe card 23 that meets the testing requirements. This avoids using an incorrect probe card, which could lead to poor contact, signal interference, or chip damage, affecting the accuracy of the test results.
[0040] Specifically, the processor 30 and the image acquisition component 22 can be connected via a data cable or wirelessly, as long as signal transmission can be achieved between the processor 30 and the image acquisition component 22.
[0041] Figure 5 This is a block diagram of the processor in an embodiment of this disclosure.
[0042] In some embodiments, such as Figure 5 As shown, the processor 30 includes a storage module 31, a signal transmission module 32, and a data processing module 33.
[0043] The storage module 31 is used to store the marking codes and parameter information of all probe cards 23 used in the wafer electrical testing device. Specifically, the parameter information includes the probe card model, manufacturing date, PM count, probe card contact count, leakage current of each pin, resistance of each pin, capacitance data of each pin, pin tip level of each pin, pin tip length of each pin, insertion depth of each pin, single row of pins, double row of pins, pin material of each pin, probe card status, etc.
[0044] The signal transmission module 32 is connected to the image acquisition component 22 to receive image information with a tag code fed back by the image acquisition component 22.
[0045] The data processing module 33 is used to obtain the parameter information of the corresponding probe card according to the feedback marking code, and update the number of times the probe card is used in the parameter information.
[0046] In some embodiments, the data processing module 33 also updates the parameter information, such as the most recent use time of the probe card and the associated wafer batch. The parameter information corresponding to the marking code on the probe card is updated during the use of the probe card, thereby recording the usage frequency and wear of the probe card and providing a basis for formulating reasonable maintenance, calibration and replacement plans.
[0047] Figure 6 This is a structural block diagram of a wafer electrical testing apparatus according to another embodiment of the present disclosure.
[0048] In some embodiments, such as Figure 6 As shown, the processor 30 is connected to the probe card management system 300, which stores the tag codes and parameter information of all probe cards. The parameter information includes the probe card model, manufacturing date, PM count, probe card contact count, leakage current of each pin, resistance of each pin, capacitance of each pin, pin tip level, pin tip length, insertion depth of each pin, single-row pins, double-row pins, pin material of each pin, and probe card status. Specifically, the probe card management system 300 is a remote management and control center for probe cards, centrally managing the information of all probe cards available for wafer electrical testing equipment. The processor 30 can obtain the parameter information of each probe card in the probe card management system 300 through data transmission, compare and update it with the data information stored in the storage module, and also feed back the updated probe card parameter information from the data processing module to the probe card management system 300.
[0049] In some embodiments, the probe card management system 300 receives current probe card information fed back by the processor 30 to update the number of times the probe card has been used in the parameter information. Specifically, the updated parameter information also includes information such as the most recent usage time of the probe card and the associated wafer batch.
[0050] In some embodiments, the wafer electrical testing apparatus 100 further includes an alarm module 40, which is connected to the processor 30. When the processor 30 determines that the probe card is in an abnormal state based on the parameter information of the probe card, it controls the alarm module to output an alarm signal. An abnormal state of the probe card may include, for example, a mismatch between the probe card model and the wafer model being tested, or frequent test anomalies occurring with the probe card.
[0051] Specifically, the alarm module 40 includes a warning light and / or a voice module and / or a display screen. For example, when the probe card model does not match the tested wafer model, the processor 30 controls the warning light to illuminate, and the display screen shows an abnormality, displaying the abnormality information that the probe card model does not match the tested wafer model.
[0052] In some embodiments, the wafer electrical testing apparatus 100 further includes a heating component (not shown in the figure), which is disposed at the support platform and is used to heat the wafer, thereby detecting the electrical performance, stability and other indicators of the wafer at different temperatures during the testing process, and ensuring that the wafer can work normally in various operating temperature ranges.
[0053] The text and accompanying drawings in this disclosure are provided by way of example only to aid in understanding this disclosure. They should not be construed as limiting the scope of this disclosure in any way. Although certain embodiments and examples have been provided, it will be apparent to those skilled in the art, based on the content disclosed herein, that changes can be made to the illustrated embodiments and examples without departing from the scope of this disclosure.
[0054] Although this disclosure has been described with reference to exemplary embodiments, various changes and modifications may be suggested to those skilled in the art. This disclosure is intended to cover such changes and modifications that fall within the scope of the appended claims.
[0055] Nothing described in this disclosure should be construed as implying that any particular element, step, or function is an essential element that must be included within the scope of the claims. The scope of the patent subject matter is defined only by the claims.
Claims
1. A wafer electrical testing device, characterized in that, include: Wafer carrier mechanism, including a carrier platform for holding wafers; An electrical testing mechanism is located above the support platform. The electrical testing mechanism includes a test circuit board, a clamping component for fixing the probe card, and an image acquisition component. The test circuit board is used to electrically connect with each probe on the probe card, and the image acquisition component is used to acquire the marking code on the probe card. as well as The processor is signal-connected to the image acquisition component, and the processor obtains the parameter information of the probe card according to the tag code read by the image acquisition component.
2. The wafer electrical testing apparatus according to claim 1, characterized in that, There are multiple probe cards, and each probe card has a marking code pasted or sprayed on it.
3. The wafer electrical testing apparatus according to claim 1, characterized in that, The image acquisition component is located on the test circuit board.
4. The wafer electrical testing apparatus according to claim 3, characterized in that, The test circuit board has a groove, and the image acquisition component is embedded in the groove.
5. The wafer electrical testing apparatus according to claim 1, characterized in that, It also includes an alarm module, which is connected to the processor. When the processor determines that the probe card is in an abnormal state based on the parameter information of the probe card, it controls the alarm module to output an alarm signal.
6. The wafer electrical testing apparatus according to claim 5, characterized in that, The alarm module is a warning light and / or a voice module and / or a display screen.
7. The wafer electrical testing apparatus according to claim 1, characterized in that, The processor includes: The storage module is used to store the tag codes and parameter information of all probe cards; A signal transmission module is used to connect to the image acquisition component to receive the tag code fed back by the image acquisition component; The data processing module is used to obtain the parameter information of the corresponding probe card based on the feedback marking code, and update the number of times the probe card has been used in the parameter information.
8. The wafer electrical testing apparatus according to claim 7, characterized in that, The processor is connected to the probe card management system, which stores the tag codes and parameter information of all probe cards.
9. The wafer electrical testing apparatus according to claim 8, characterized in that, The parameter information includes at least one of the following: probe card model, manufacturing date, PM count, probe card contact count, leakage current of each needle, resistance of each needle, capacitance data of each needle, needle tip level of each needle, needle tip length of each needle, insertion depth of each needle, single row of needles, double row of needles, and needle material of each needle. The probe card management system is used to receive the current probe card information fed back by the processor to update the number of times the probe card has been used in the parameter information.
10. The wafer electrical testing apparatus according to claim 1, characterized in that, It also includes a heating assembly disposed at the support platform, the heating assembly being used to heat the wafer.