A synchronous flip-flop of configurable multi-level interface based on ARM controller
By using a configurable multi-level interface synchronous trigger based on an ARM controller, the problems of transmission distance and electromagnetic interference for TTL level signals are solved, achieving flexible interface switching and high anti-interference capability, which is suitable for fields such as intelligent manufacturing, medical instruments and automated testing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SUZHOU INST OF TECH PHYSICS OF SCI & TECH OF CHINA
- Filing Date
- 2025-08-05
- Publication Date
- 2026-07-24
Smart Images
Figure CN224553671U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of trigger technology, specifically to a synchronous trigger based on an ARM controller with a configurable multi-level interface. Background Technology
[0002] In practical applications, to synchronize the sampling behavior of the device with other hardware (such as an electric platform), in addition to software commands, communication between different hardware can also be achieved through level signals (such as TTL level signals, LVCMOS level signals, etc.). The device can both receive and output level signals.
[0003] Typically, TTL level signals are used at the receiving end of the device to receive the synchronization trigger signal. The level signal has two states, high level and low level; through the information transmitted by the high-low level transition, the device can communicate with other hardware. The voltage difference between the high and low levels of the level signal is not exactly the same for different devices. Hardware such as cameras generally use the following types of signals: (1) rising edge and falling edge, which refer to the voltage change during the high-low level transition; (2) the duration of the level.
[0004] However, in practical applications, TTL level signals are easily affected by transmission distance limitations and electromagnetic interference. Generally, synchronous signal interfaces need to be designed to convert TTL level signals into differential signals or other signal types with strong anti-interference capabilities. Utility Model Content
[0005] In view of this, in order to solve the problem that TTL level trigger signals are easily affected by transmission distance and electromagnetic interference, the purpose of this utility model is to propose a synchronous trigger based on an ARM controller with a configurable multi-level interface. Through a configurable hardware architecture, flexible switching and mode adaptation of the multi-level interface can be realized, thus solving the problem that TTL level trigger signals are easily affected by transmission distance and electromagnetic interference.
[0006] To achieve the above objectives, this utility model provides the following technical solution: To achieve the above objectives, in a first aspect, this utility model provides a synchronous trigger with a configurable multilevel interface based on an ARM controller, comprising an ARM controller, a multilevel input processing circuit, a multilevel output processing circuit, a multilevel input interface module, a multilevel output interface module, and a FLASH storage module; wherein the ARM controller is connected to the FLASH storage module; The multi-level input processing circuit includes a synchronous trigger cascade processing circuit, an LVDS trigger processing circuit, an RS422 trigger processing circuit, an RS485 trigger processing circuit, an RS232 trigger processing circuit, and a TTL / CMOS trigger processing circuit; the multi-level output processing circuit includes a synchronous trigger cascade processing circuit, a synchronous software trigger processing circuit, a synchronous hardware trigger processing circuit, and a synchronous trigger mode configuration circuit.
[0007] As a further embodiment of this utility model, the ARM controller is a GD32F103C8T6 controller or an STM32F103C8T6 controller. The peripheral circuit of the ARM controller is designed based on the GD32F103C8T6 chip and integrates a reset module, a startup mode module, an SPWM module, a power supply filtering module, a crystal oscillator module, a power supply module, and an ARM core module.
[0008] As a further embodiment of this utility model, the FLASH storage module is located in the configuration module of the ARM core module and is used to configure the working mode, input mode, output mode and trigger thermal characteristic parameters. The trigger thermal characteristic parameters include trigger level, trigger mode, positive pulse selection, negative pulse selection and pulse width.
[0009] As a further embodiment of this invention, the multi-level input interface module supports at least six configurable level standards, including a synchronous trigger cascaded input interface, an LVDS trigger input interface, an RS422 trigger input interface, an RS485 trigger input interface, an RS232 trigger input interface, and a TTL / CMOS trigger input interface, and is respectively connected to the synchronous trigger cascaded processing circuit, LVDS trigger processing circuit, RS422 trigger processing circuit, RS485 trigger processing circuit, RS232 trigger processing circuit, and TTL / CMOS trigger processing circuit of the multi-level input processing circuit.
[0010] As a further embodiment of this utility model, the LVDS trigger input interface adopts the DS90LV032 differential receiver chip, the RS422 trigger input interface adopts the AM26LV32IDR differential receiver chip, the RS485 trigger input interface adopts the MAX3085EESA+T differential receiver chip, and the RS232 trigger input interface adopts the MAX3232 chip.
[0011] As a further embodiment of this utility model, the multi-level input interface module and the multi-level output interface module include a bus driver circuit, which adopts the SN74AHCT16245DGGR chip.
[0012] As a further embodiment of this utility model, the multi-level output interface module supports at least four configurable output forms, including a synchronous trigger cascade output interface, a synchronous software trigger output interface, a synchronous hardware trigger output interface, and a synchronous trigger mode configuration interface. The synchronous trigger cascade output interface is connected to cascaded devices, the synchronous software trigger output interface and the synchronous hardware trigger output interface are connected to the controlled devices, and the synchronous trigger mode configuration interface is connected to the host computer configuration software.
[0013] As a further embodiment of this utility model, the configurable multi-level interface synchronous trigger also includes a physical structure module. The physical structure module includes a main control board PCB, a housing, a front panel, a rear panel, and multiple interface components. The interface components include an external trigger cascaded signal input interface, a multi-level external trigger interface, a main control board power supply interface, a system configuration USB interface, a synchronous software trigger output interface, a synchronous hardware trigger output interface, and a synchronous trigger cascaded output interface, all integrated on the same main control board PCB.
[0014] As a further embodiment of this utility model, the configuration module includes a synchronous software triggering processing circuit, which uses a CH340 chip to implement the USB to serial port function for host computer communication and mode configuration.
[0015] Compared with existing technologies, the synchronous trigger based on an ARM controller with a configurable multi-level interface proposed in this invention has the following advantages: This invention, through software configuration of the ARM controller, supports the free selection of multiple trigger input and trigger output interfaces, enabling dynamic switching of multi-level interfaces. It solves the problem of poor compatibility of traditional TTL level interfaces, adapts to different device level standards, and seamlessly switches interface types in complex industrial environments without hardware replacement. Furthermore, addressing long-distance transmission and electromagnetic interference issues, this invention integrates high anti-interference interfaces. The LVDS interface supports 400Mbps high-speed transmission, converting differential signals to CMOS levels using the DS90LV032 chip, significantly reducing noise impact. The RS422 / RS485 interface uses AM26LV32IDR and MAX3085EESA+T chips, supporting ±15kV ESD protection to ensure stable signal transmission in harsh environments, enhancing anti-interference and signal stability.
[0016] This invention also allows for real-time configuration of waveform characteristics and mode switching parameters via host computer or serial port commands. The configuration parameters are automatically saved to the ARM controller's built-in FLASH memory for storage, eliminating the need for repeated settings after power failure. It covers all scenarios with four operating modes: independent receiver, cascaded receiver, independent control host, and cascaded control host, providing multi-mode collaboration and cascade expansion capabilities. All interfaces are integrated into a single-board design, reducing size and assembly costs. During the control process, FLASH parameters are automatically loaded upon power-up, configuration requirements are detected, and real-time switching of operating states is supported, providing a highly reliable synchronous triggering solution for fields such as intelligent manufacturing, medical instruments, and automated testing.
[0017] These or other aspects of this application will become more apparent from the following description of embodiments. It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the application. Attached Figure Description
[0018] To more clearly illustrate the technical solutions in the embodiments of this utility model or related technologies, the accompanying drawings used in the description of the exemplary embodiments or related technologies will be briefly introduced below. The drawings are used to provide a further understanding of this utility model and constitute a part of the specification. They are used together with the embodiments of this utility model to explain this utility model and do not constitute a limitation on this utility model. In the drawings: Figure 1 This is a system block diagram of a synchronous trigger with a configurable multi-level interface based on an ARM controller, according to an embodiment of the present invention.
[0019] Figure 2 This is a block diagram illustrating the use of a configurable multi-level interface synchronous trigger based on an ARM controller as a receiver, according to an embodiment of this utility model.
[0020] Figure 3 This is a connection block diagram illustrating the use of a configurable multi-level interface synchronous trigger based on an ARM controller as a receiver in a cascaded mode, according to an embodiment of this utility model.
[0021] Figure 4 This is a connection diagram illustrating the use of a configurable multi-level interface synchronous trigger based on an ARM controller as a control host, according to an embodiment of this utility model.
[0022] Figure 5 This is a connection diagram illustrating the use of a cascaded mode of a synchronous trigger with a configurable multi-level interface based on an ARM controller as a control host, according to an embodiment of this utility model.
[0023] Figure 6This is a flowchart illustrating the configuration of a cascaded synchronous trigger control system based on an ARM controller with a configurable multi-level interface, according to an embodiment of this utility model.
[0024] Figure 7 This is a peripheral circuit diagram based on GD32F103C8T6 in a synchronous trigger with a configurable multi-level interface based on an ARM controller, according to an embodiment of this utility model.
[0025] Figure 8 This is a bus drive circuit diagram based on SN74AHCT16245DGGR in a synchronous trigger with a configurable multi-level interface based on an ARM controller, according to an embodiment of this utility model.
[0026] Figure 9 This is a circuit diagram of the LVDS trigger input processing circuit based on DS90LV032 in a synchronous trigger with a configurable multi-level interface based on an ARM controller, according to an embodiment of this utility model.
[0027] Figure 10 This is a circuit diagram of RS422 trigger input processing based on AM26LV32IDR in a synchronous trigger with a configurable multi-level interface based on an ARM controller, according to an embodiment of this utility model.
[0028] Figure 11 This is a circuit diagram of RS485 trigger input processing based on MAX3085EESA+T in a synchronous trigger with a configurable multi-level interface based on an ARM controller, according to an embodiment of this utility model.
[0029] Figure 12 This is a circuit diagram of RS232 trigger input processing based on MAX3232 in a synchronous trigger with a configurable multi-level interface based on an ARM controller, according to an embodiment of this utility model.
[0030] Figure 13 This is a circuit diagram of the synchronous software triggering processing and synchronous triggering mode configuration processing based on CH340 in a synchronous trigger with a configurable multi-level interface based on an ARM controller, according to an embodiment of this utility model.
[0031] Figure 14 This is a system control flowchart of a synchronous trigger with a configurable multi-level interface based on an ARM controller, according to an embodiment of the present invention.
[0032] Figure 15 This is a structural assembly diagram of a synchronous trigger with a configurable multi-level interface based on an ARM controller, according to an embodiment of this utility model. Detailed Implementation
[0033] The present application will now be further described in conjunction with the accompanying drawings and specific embodiments. It should be noted that, without conflict, the various embodiments or technical features described below can be arbitrarily combined to form new embodiments.
[0034] To make the objectives, technical solutions, and advantages of this utility model clearer, the embodiments of this utility model are further described in detail below with reference to specific examples and the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit this application.
[0035] It should be noted that all uses of the terms "first" and "second" in the embodiments of this utility model are for the purpose of distinguishing two different entities or different parameters with the same name. Therefore, "first" and "second" are merely for convenience of expression and should not be construed as limiting the embodiments of this utility model. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, such as other steps or units inherent in a process, method, system, product, or device that includes a series of steps or units.
[0036] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0037] The flowchart shown in the attached diagram is for illustrative purposes only and does not necessarily include all content and operations / steps, nor does it necessarily have to be performed in the order described. For example, some operations / steps can be broken down, combined, or partially merged, so the actual execution order may change depending on the actual situation.
[0038] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0039] To address the issue of TTL level trigger signals being susceptible to transmission distance and electromagnetic interference, this invention proposes a synchronous trigger with a configurable multi-level interface based on an ARM controller. Through a configurable hardware architecture, it achieves flexible switching and mode adaptation of the multi-level interface, thus resolving the problems of TTL level trigger signals being susceptible to transmission distance and electromagnetic interference.
[0040] See Figure 1As shown, an embodiment of this utility model provides a synchronous trigger with a configurable multilevel interface based on an ARM controller, including an ARM controller, a multilevel input processing circuit, a multilevel output processing circuit, a multilevel input interface module, a multilevel output interface module, and a FLASH storage module; the ARM controller is connected to the FLASH storage module, the FLASH storage module runs on the ARM controller, the ARM controller is used to read the default parameters stored in the FLASH when powered on, and dynamically adjust the working state according to the configuration command, and is also used to process signal conversion, mode control and trigger signal generation.
[0041] The multi-level input processing circuit includes a synchronous trigger cascade processing circuit, an LVDS trigger processing circuit, an RS422 trigger processing circuit, an RS485 trigger processing circuit, an RS232 trigger processing circuit, and a TTL / CMOS trigger processing circuit; the multi-level output processing circuit includes a synchronous trigger cascade processing circuit, a synchronous software trigger processing circuit, a synchronous hardware trigger processing circuit, and a synchronous trigger mode configuration circuit.
[0042] This invention's synchronous trigger allows for flexible selection of trigger interfaces with different level standards based on control commands. It supports various trigger input interfaces, including synchronous trigger cascade input, LVDS trigger input, RS422 trigger input, RS485 trigger input, RS232 trigger input, and TTL / CMOS trigger input. The system design also allows for flexible selection of trigger output forms based on control commands, supporting synchronous software trigger output, synchronous hardware trigger output, and synchronous trigger cascade output interfaces. System parameters can be configured via a host computer and serial port commands, allowing selection of different trigger input interfaces, trigger output interfaces, and trigger pulse waveform characteristics. The system includes a FLASH storage module to store the configured system parameters.
[0043] In this embodiment, to achieve system control and operation, the ARM controller is a GD32F103C8T6 controller or an STM32F103C8T6 controller. The peripheral circuit of the ARM controller is designed based on the GD32F103C8T6 chip and integrates a reset module, a startup mode module, an SPWM module, a power supply filtering module, a crystal oscillator module, a power supply module, and an ARM core module. It is used to select trigger interfaces and trigger output forms with different level standards according to control instructions, and to configure system parameters through host computer and serial port commands, and select different types of trigger input interfaces, trigger output interfaces, and trigger pulse waveform characteristics.
[0044] In this embodiment, the controller circuit can use either GigaDevice's GD32F103C8T6 ARM core control chip or STMicroelectronics' STM32F103C8T6 ARM core control chip. The design selects GigaDevice's GD32F103C8T6 controller to realize and complete the control and timing drive of the entire system. To achieve the control of the entire system, peripheral circuits based on the GD32F103C8T6 are designed, including a reset module, a startup mode module, an SPWM module, a power supply filtering module, a crystal oscillator module, a power supply module, and the GD32F103C8T6 core module, such as... Figure 7 As shown.
[0045] To implement synchronous trigger cascaded input processing circuits, synchronous trigger cascaded output processing circuits, TTL / CMOS trigger input processing circuits, and synchronous hardware trigger output processing circuits, this invention can use 16245 series bus drivers such as SN74LVC16245ADGGR or SN74AHCT16245DGGR as digital signal input and output interface chips.
[0046] The FLASH storage module is located in the configuration module of the ARM core module and is used to configure the working mode, input mode, output mode and trigger thermal characteristic parameters through the host computer or serial port commands. The trigger thermal characteristic parameters include trigger level, trigger mode, positive pulse selection, negative pulse selection and pulse width.
[0047] In this embodiment, the multi-level input interface module is used to receive external trigger signals. The multi-level input interface module supports at least six configurable level standards, including a synchronous trigger cascade input interface, an LVDS trigger input interface, an RS422 trigger input interface, an RS485 trigger input interface, an RS232 trigger input interface, and a TTL / CMOS trigger input interface, and is respectively connected to the synchronous trigger cascade processing circuit, LVDS trigger processing circuit, RS422 trigger processing circuit, RS485 trigger processing circuit, RS232 trigger processing circuit, and TTL / CMOS trigger processing circuit of the multi-level input processing circuit.
[0048] The LVDS trigger input interface uses the DS90LV032 differential receiver chip, the RS422 trigger input interface uses the AM26LV32IDR differential receiver chip, the RS485 trigger input interface uses the MAX3085EESA+T differential receiver chip, and the RS232 trigger input interface uses the MAX3232 chip. The LVDS trigger input interface, based on the DS90LV032 differential receiver chip, supports a data transmission rate of 400Mbps, converts low-voltage differential signals to 3V CMOS levels, and provides open-circuit and short-circuit fault protection. The RS422 trigger input interface, based on the AM26LV32IDR differential receiver chip, has ±200mV sensitivity and tri-state output. The RS485 trigger input interface, based on the MAX3085EESA+T differential receiver chip, supports ±15kV ESD protection and fail-safe output. The RS232 trigger input interface, based on the MAX3232 chip, supports a data rate of 250kbit / s and ±15kV... ESD protection, charge pump circuit compatible with 3V to 5.5V single power supply.
[0049] This invention utilizes the SN74AHCT16245DGGR as a bus driver, which can buffer input and output digital signals. This improves the driving capability and signal integrity of digital signals, and also enables level conversion, such as... Figure 8 As shown.
[0050] To implement the LVDS trigger input processing circuit, this design can use LVDS differential receiver chips such as DS90LV032 or DS90LV048 as the LVDS trigger input interface chip. The DS90LV032 selected in this design, as an LVDS differential receiver chip, employs Low Voltage Differential Signaling (LVDS) technology, supports a data transmission rate of 400Mbps (200MHz), and is suitable for high-speed point-to-point communication. It can convert low-voltage differential input signals (typically 350mV) to a 3V CMOS output level. It supports open-circuit, short-circuit, and terminated input fault protection; the output remains high during faults, improving system reliability. Figure 9 As shown.
[0051] To implement the RS422 trigger processing circuit, this design can use RS422 differential receiver chips such as AM26LV32IDR or SN75176B as RS422 trigger input interface chips. The AM26LV32IDR used in this design, as an RS422 differential receiver chip, employs Low Voltage Differential Signaling (LVDS) technology, features tri-state output, and has a sensitivity of ±200mV. The interface circuit design supports open-circuit, short-circuit, and terminated input fault protection; the output remains high during faults, improving system reliability. Figure 10 As shown.
[0052] To implement the RS485 trigger processing circuit, this design can use RS485 differential receiver chips such as the MAX3085EESA+T or SN75176B as the RS485 trigger input interface chip. The MAX3085EESA+T used in this design, as an RS485 differential receiver chip, features high reliability and low power consumption. The circuit design can implement ±15kV ESD protection, fault-safe output, and multi-node support, such as... Figure 11 As shown.
[0053] To implement the RS232 trigger processing circuit, this design uses the dedicated RS232 chip MAX3232. The MAX3232 is chosen as a dedicated RS232 chip to receive RS232 trigger signals. The MAX3232 device consists of two line drivers, two line receivers, and a dual charge pump circuit, featuring ±15kV ESD protection between terminals (serial port connection terminals, including GND). This part of the circuit design complies with TIA / EIA-232-F requirements and provides an electrical interface between the asynchronous communication controller and the serial port connector. The charge pump and four small external capacitors support a single supply from 3V to 5.5V. The device operates at data signal transmission rates up to 250kbit / s, with a driver output slew rate of up to 30V / μs. Figure 12 As shown.
[0054] To achieve synchronous software triggering and synchronous trigger mode configuration, this design uses the CH340 USB bus adapter chip to implement USB-to-serial port control functionality. The CH340 chip is chosen for its ability to transmit synchronous software triggers and configure synchronous trigger modes. Using the CH340 chip, the system design utilizes a full-speed USB device interface, compatible with USB V2.0. The host computer is designed for compatibility with a serial port application running on a Windows operating system. Figure 13 As shown.
[0055] The multi-level input interface module and the multi-level output interface module include a bus driver circuit, which uses the SN74AHCT16245DGGR chip for digital signal buffering and level conversion, thereby improving signal driving capability and integrity.
[0056] The multi-level output interface module is used to output trigger signals to the controlled device. The multi-level output interface module supports at least four configurable output forms, including synchronous trigger cascade output interface, synchronous software trigger output interface, synchronous hardware trigger output interface, and synchronous trigger mode configuration interface. The synchronous trigger cascade output interface is connected to the cascaded device, the synchronous software trigger output interface and the synchronous hardware trigger output interface are connected to the controlled device, and the synchronous trigger mode configuration interface is connected to the host computer configuration software.
[0057] Among them, see Figure 14 As shown, the configurable multi-level interface synchronous trigger also includes a physical structure module, which includes a main control board PCB 1, a housing 11, a front panel 9, a rear panel 10, and multiple interface components. The interface components include an external trigger cascaded signal input interface 2, a multi-level external trigger interface 3, a main control board power supply interface 4, a system configuration USB interface 5, a synchronous software trigger output interface 6, a synchronous hardware trigger output interface 7, and a synchronous trigger cascaded output interface 8, all integrated on the same main control board PCB 1.
[0058] In this embodiment of the present invention, the synchronous trigger supports four operating modes, which can be dynamically switched through the configuration module, wherein: Mode 1: Receiver mode, where the synchronous trigger acts as an independent receiver host, receives external trigger signals and forwards them to the controlled device through the output interface module, and the external trigger signals are input through any interface in the multi-level input interface module; Mode 2: Receiver cascade mode, where multiple synchronization triggers are cascaded, one of which acts as the receiving master connected to an external trigger interface, and the others act as receiving slaves connected through trigger cascade input and output interfaces to achieve multi-device synchronization; Mode 3: Control host mode, where the synchronous trigger uses an internal timer module to actively generate a trigger signal and controls the controlled device through the output interface module; Mode 4: Control host cascade mode, where multiple synchronous triggers are cascaded, one of which acts as the control host to generate trigger signals and transmit them through the cascade interface, while the others act as slaves to receive signals, thereby realizing synchronous control of multiple devices.
[0059] This utility model's synchronous trigger can be combined to achieve multiple usage modes. Usage mode 1: The synchronous trigger is used as a receiver. Usage mode 2: The synchronous trigger is used in a cascaded receiver mode. Usage mode 3: The synchronous trigger is used as a control host. Usage mode 4: The synchronous trigger is used in a cascaded control host mode. Specifically: In mode 1, the synchronous trigger is used as a receiver. This system's synchronous trigger can be used independently as a receiver for synchronous trigger signals, connecting to an external trigger interface to receive externally transmitted trigger signals. The external trigger signal interface can be selected from various types, including LVDS, RS422, RS485, RS232, and TTL / CMOS trigger input interfaces. For the controlled device, the system parameters of the synchronous trigger can be configured to select whether the controlled device supports software triggering, hardware triggering, and the thermal characteristics of the trigger waveform. The connection for using the synchronous trigger as a receiver is as follows: Figure 2 As shown.
[0060] In mode 2, the synchronous trigger is used as a cascaded receiver. The synchronous trigger designed for this system can also achieve synchronous trigger control of multiple devices via a cascaded interface. The cascaded mode of the synchronous trigger is as follows: Figure 2 As shown. In cascade mode, only the trigger acting as the receiving master of the synchronous trigger connects to the external trigger interface; other synchronous triggers, acting as receiving slaves, connect using the trigger cascade interface. For the controlled device, the system parameters of the synchronous triggers can be configured to select whether to use software triggering, hardware triggering, or trigger waveform thermal characteristics supported by the controlled device. The connection method for the synchronous trigger acting as a receiver in cascade mode is as follows: Figure 3 As shown.
[0061] In mode 3, the synchronous trigger is used as the control host. This system's synchronous trigger can also be used independently, acting as a control host for synchronous trigger signals to achieve synchronous control of the controlled equipment in the absence of an external trigger signal. The device uses an internal timer to set the waveform thermal characteristics of the trigger signal. For the controlled equipment, the system parameters of the synchronous trigger can be configured to select whether to use software triggering, hardware triggering, and trigger waveform thermal characteristics supported by the controlled equipment. The connection for using the synchronous trigger as the control host is as follows: Figure 4 As shown.
[0062] In mode 4, the synchronous trigger is used as a cascaded control unit. The synchronous triggers in this system can also be used independently in conjunction with the trigger cascade interface to achieve synchronous trigger control of multiple devices without an external trigger signal. The synchronous trigger control unit sets the waveform thermal characteristics of the trigger signal through an internal timer, while other synchronous triggers act as receiving slaves connected via the trigger cascade interface. For the controlled devices, the system parameters of the synchronous triggers can be configured to select whether to use software triggering, hardware triggering, or trigger waveform thermal characteristics supported by the controlled device. The connection for using the synchronous trigger as a cascaded control unit is as follows: Figure 5 As shown.
[0063] Among them, see Figure 6 As shown, the configuration process of the configuration module includes: Configure the working mode by selecting the control host working mode, the receiving host working mode, or the receiving slave working mode. Input mode configuration: Select synchronous trigger cascade input mode, LVDS trigger input mode, RS422 trigger input mode, RS485 trigger input mode, RS232 trigger input mode, or TTL / CMOS trigger input mode; Output mode configuration: Select synchronous trigger cascade output mode, synchronous software trigger output mode, or synchronous hardware trigger output mode; Trigger thermal characteristics configuration: Set trigger level, trigger mode, positive pulse selection, negative pulse selection, or pulse width; After configuration, the parameters are stored in the FLASH storage module.
[0064] In this invention, the settings for the trigger control system include the following configuration interfaces. Upon initial use, the operating mode, input mode, output mode, and trigger thermal characteristics need to be configured according to the usage scenario and operating mode of the equipment. After configuration, the system configuration parameters will be saved in the internal FLASH memory of the main control chip.
[0065] In this embodiment, the configuration module includes a synchronous software trigger processing circuit, which uses a CH340 chip to implement a USB-to-serial port function for host computer communication and mode configuration. The workflow of the synchronous software trigger processing circuit includes: system power-on initialization and reading FLASH parameters; detecting mode configuration requirements; updating the working mode, input mode, output mode, or trigger thermal characteristics according to serial port or host computer commands; after entering the working state, generating a trigger signal using an internal timer in the host control mode, and detecting and forwarding the trigger signal in the host / slave receiving mode.
[0066] This invention, through software configuration of the ARM controller, supports the free selection of multiple trigger input and trigger output interfaces, enabling dynamic switching of multi-level interfaces. It solves the problem of poor compatibility of traditional TTL level interfaces, adapts to different device level standards, and seamlessly switches interface types in complex industrial environments without hardware replacement. Furthermore, addressing long-distance transmission and electromagnetic interference issues, this invention integrates high anti-interference interfaces. The LVDS interface supports 400Mbps high-speed transmission, converting differential signals to CMOS levels using the DS90LV032 chip, significantly reducing noise impact. The RS422 / RS485 interface uses AM26LV32IDR and MAX3085EESA+T chips, supporting ±15kV ESD protection to ensure stable signal transmission in harsh environments, enhancing anti-interference and signal stability.
[0067] The control flowchart of the synchronous trigger of this utility model is as follows: Figure 13 As shown, it includes the following steps: During the initial power-up phase, the system's default operating parameters are configured by reading the internal FLASH parameters.
[0068] During the initialization phase, the synchronous trigger mode configuration interface will be used to check if there is a mode configuration that needs to be set. If no configuration is required, it will directly enter the working state. If mode configuration is required, the system's working mode, input mode, output mode, and triggering hot characteristics will be configured accordingly based on the configuration command sent by the synchronous trigger mode configuration interface. After the corresponding mode configuration is completed, the system will enter the working state.
[0069] Optional operating mode configurations include: control host operating mode, receiving host operating mode, and receiving slave operating mode; Optional input mode configurations include: synchronous trigger cascade input mode, LVDS trigger input mode, RS422 trigger input mode, RS485 trigger input mode, RS232 trigger input mode, and TTL / CMOS trigger input mode; Optional output mode configurations include: synchronous trigger cascade output mode, synchronous software trigger output mode, and synchronous hardware trigger mode; Optional trigger thermal characteristic configurations include: trigger level, trigger mode, positive pulse selection, negative pulse selection, pulse width, etc. All configurations can be completed via the host computer designed with this system or by directly sending instruction sets.
[0070] The system operates in two main modes: master control mode and master / slave receiver mode. In master control mode, the system uses the ARM controller's internal timer module to actively generate trigger signals according to configuration parameters and control the controlled devices, achieving synchronous triggering. In master / slave receiver mode, the system detects trigger signals based on the currently selected input and output interfaces, completing the reception and forwarding of these signals.
[0071] This invention, in conjunction with control software, allows for flexible selection of trigger interfaces with different level standards based on control commands. It supports various trigger input interfaces, including synchronous trigger cascade input, LVDS trigger input, RS422 trigger input, RS485 trigger input, RS232 trigger input, and TTL / CMOS trigger input. The control software also allows for flexible selection of trigger output forms, supporting synchronous software trigger output, synchronous hardware trigger output, and synchronous trigger cascade output interfaces. System parameters can be configured via host computer and serial port commands, allowing selection of different trigger input and output interfaces. The control software facilitates easy setting of trigger pulse waveform characteristics, including trigger level, trigger mode, positive pulse selection, negative pulse selection, and pulse width. An embedded software system can be used to design a FLASH storage module to store configured system parameters. Furthermore, the control software allows for multiple usage modes. Mode 1 uses the synchronous trigger as a receiver. Mode 2 uses the synchronous trigger as a cascaded receiver. Mode 3 uses the synchronous trigger as a control host. Using mode 4, the synchronous trigger is used as the cascading mode for the control host.
[0072] This invention also allows for real-time configuration of waveform characteristics and mode switching parameters via host computer or serial port commands. The configuration parameters are automatically saved to the ARM controller's built-in FLASH memory for storage, eliminating the need for repeated settings after power failure. It covers all scenarios with four operating modes: independent receiver, cascaded receiver, independent control host, and cascaded control host, providing multi-mode collaboration and cascade expansion capabilities. All interfaces are integrated into a single-board design, reducing size and assembly costs. During the control process, FLASH parameters are automatically loaded upon power-up, configuration requirements are detected, and real-time switching of operating states is supported, providing a highly reliable synchronous triggering solution for fields such as intelligent manufacturing, medical instruments, and automated testing.
[0073] The above are exemplary embodiments disclosed in this utility model. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments of this utility model as defined by the claims. The functions, steps, and / or actions of the methods according to the disclosed embodiments described herein do not need to be performed in any particular order. Furthermore, although the elements disclosed in the embodiments of this utility model may be described or claimed individually, they may be understood as multiple unless explicitly limited to a singular number.
[0074] It should be understood that, as used herein, the singular form "a" is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" refers to any and all possible combinations of one or more of the associatedly listed items. The embodiment numbers disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.
[0075] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the present invention (including the claims) is limited to these examples. Within the framework of the present invention, technical features of the above embodiments or different embodiments can also be combined, and many other variations of different aspects of the present invention exist, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A synchronous trigger with a configurable multi-level interface based on an ARM controller, characterized in that, It includes an ARM controller, a multi-level input processing circuit, a multi-level output processing circuit, a multi-level input interface module, a multi-level output interface module, and a FLASH storage module; the input terminal of the ARM controller is connected to the multi-level input processing circuit, the multi-level input processing circuit is connected to the multi-level input interface module, the output terminal of the ARM controller is connected to the multi-level output processing circuit, the multi-level output processing circuit is connected to the multi-level output interface module, and the ARM controller is connected to the FLASH storage module; The multi-level input processing circuit includes a synchronous trigger cascade processing circuit, an LVDS trigger processing circuit, an RS422 trigger processing circuit, an RS485 trigger processing circuit, an RS232 trigger processing circuit, and a TTL / CMOS trigger processing circuit; the multi-level output processing circuit includes a synchronous trigger cascade processing circuit, a synchronous software trigger processing circuit, a synchronous hardware trigger processing circuit, and a synchronous trigger mode configuration circuit.
2. The synchronous trigger with a configurable multi-level interface based on an ARM controller as described in claim 1, characterized in that, The ARM controller is a GD32F103C8T6 controller or an STM32F103C8T6 controller. The peripheral circuit of the ARM controller is designed based on the GD32F103C8T6 chip and integrates a reset module, a startup mode module, an SPWM module, a power supply filtering module, a crystal oscillator module, a power supply module, and an ARM core module.
3. The synchronous trigger with a configurable multi-level interface based on an ARM controller as described in claim 2, characterized in that, The FLASH storage module is located in the configuration module of the ARM core module and is used to configure the working mode, input mode, output mode and trigger thermal characteristic parameters. The trigger thermal characteristic parameters include trigger level, trigger mode, positive pulse selection, negative pulse selection and pulse width.
4. The synchronous trigger with a configurable multi-level interface based on an ARM controller as described in claim 3, characterized in that, The multi-level input interface module supports at least six configurable level standards, including synchronous trigger cascade input interface, LVDS trigger input interface, RS422 trigger input interface, RS485 trigger input interface, RS232 trigger input interface, and TTL / CMOS trigger input interface, and is respectively connected to the synchronous trigger cascade processing circuit, LVDS trigger processing circuit, RS422 trigger processing circuit, RS485 trigger processing circuit, RS232 trigger processing circuit, and TTL / CMOS trigger processing circuit of the multi-level input processing circuit.
5. The synchronous trigger with a configurable multi-level interface based on an ARM controller as described in claim 4, characterized in that, The LVDS trigger input interface uses the DS90LV032 differential receiver chip, the RS422 trigger input interface uses the AM26LV32IDR differential receiver chip, the RS485 trigger input interface uses the MAX3085EESA+T differential receiver chip, and the RS232 trigger input interface uses the MAX3232 chip.
6. The synchronous trigger with a configurable multi-level interface based on an ARM controller as described in claim 1, characterized in that, The multi-level input interface module and the multi-level output interface module include a bus driver circuit, which uses the SN74AHCT16245DGGR chip.
7. The synchronous trigger with a configurable multi-level interface based on an ARM controller as described in claim 6, characterized in that, The multi-level output interface module supports at least four configurable output forms, including a synchronous trigger cascade output interface, a synchronous software trigger output interface, a synchronous hardware trigger output interface, and a synchronous trigger mode configuration interface. The synchronous trigger cascade output interface is connected to cascaded devices, the synchronous software trigger output interface and the synchronous hardware trigger output interface are connected to the controlled devices, and the synchronous trigger mode configuration interface is connected to the host computer configuration software.
8. The synchronous trigger with a configurable multi-level interface based on an ARM controller as described in claim 1, characterized in that, The configurable multi-level interface synchronous trigger also includes a physical structure module, which includes a main control board PCB, a housing, a front panel, a rear panel, and multiple interface components. The interface components include an external trigger cascade signal input interface, a multi-level external trigger interface, a main control board power supply interface, a system configuration USB interface, a synchronous software trigger output interface, a synchronous hardware trigger output interface, and a synchronous trigger cascade output interface, all integrated on the same main control board PCB.