A wireless baseband chip
By integrating a processor and hardware accelerator subsystem into the wireless baseband chip, the problem of balancing energy efficiency and flexibility is solved, achieving high energy efficiency and flexible software scheduling control, and supporting the scalability and hardware-software integration of various accelerator units.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SHANHE ZHIXIN (SHENZHEN) TECHNOLOGY CO LTD
- Filing Date
- 2025-08-28
- Publication Date
- 2026-07-24
AI Technical Summary
Existing wireless baseband chips struggle to balance energy efficiency and flexibility. Pure hardware circuits offer high energy efficiency but low flexibility, while purely software-based solutions offer good flexibility but poor energy efficiency.
Design a wireless baseband chip with a built-in processor and hardware accelerator subsystem, including a DMA transfer controller, a memory management unit, and multiple accelerator units with different functions. It connects to other subsystems of the SOC chip through an AXI interface to realize a hardware and software integration strategy.
It achieves high energy efficiency while possessing flexible software scheduling and control capabilities, supporting the flexibility and scalability of various accelerator units, and reducing the complexity of software and hardware interaction.
Smart Images
Figure CN224555634U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of wireless communication technology, and in particular to a wireless baseband chip. Background Technology
[0002] The wireless baseband chip is a core component of wireless communication equipment, responsible for processing digital baseband signals and performing functions such as signal encoding, decoding, modulation, and demodulation.
[0003] In general, wireless baseband chips implement various channel and control signal transmission and reception processing functions. The usual strategies are: pure hardware circuit logic implementation or software processing (commonly known as soft baseband).
[0004] However, the advantage of a purely hardware-based implementation is its better energy efficiency, but its flexibility is lower. The advantage of a purely software-based implementation is its flexibility and ability to support software upgrades, but its energy efficiency is relatively poor. Utility Model Content
[0005] This invention provides a wireless baseband chip that has a high energy efficiency ratio and flexible scheduling and control.
[0006] A wireless baseband chip integrates a processor and a hardware accelerator subsystem. The hardware accelerator subsystem includes a DMA transfer controller, a memory management unit, and multiple accelerator units. The DMA transfer controller is communicatively connected to the memory management unit. The multiple accelerator units are each communicatively connected to the memory management unit. The memory management unit is communicatively connected to the processor. The different accelerator units have different functions.
[0007] Furthermore, the chip also incorporates other subsystems besides the hardware accelerator subsystem; the wireless baseband chip includes a SOC chip; the different subsystems have different functions; the hardware accelerator subsystem communicates with the other subsystems.
[0008] Furthermore, the hardware accelerator subsystem also includes an AXI interface; the storage management unit of the hardware accelerator subsystem communicates with other subsystems in the SOC chip through the AXI interface.
[0009] Furthermore, the plurality of accelerator units include at least two of the following: a Polar encoder, an LDPC encoder, a Fourier transform, a symbol-level equalization algorithm calculation unit, a Polar decoder, an LDPC decoder, a Cholesky decomposition calculation kernel, and a basic sequence generator.
[0010] Furthermore, the hardware accelerator subsystem also includes a shared memory; one end of the shared memory is communicatively connected to the accelerator unit, and the other end is communicatively connected to the storage management unit.
[0011] Furthermore, the hardware accelerator subsystem also includes a communication interface; one end of the communication interface is connected to the accelerator unit, and the other end is connected to the storage management unit.
[0012] Furthermore, the hardware accelerator subsystem also includes a first configuration interface; one end of the first configuration interface is communicatively connected to the first accelerator unit among the plurality of accelerator units, and the other end is communicatively connected to the storage management unit, the DMA transfer controller, and the other subsystems respectively; the configuration interface is used to convert communication interface protocols.
[0013] Furthermore, the hardware accelerator subsystem also includes a second configuration interface; one end of the second configuration interface is communicatively connected to the second accelerator unit among the plurality of accelerator units, and the other end is communicatively connected to the other subsystems; the communication interface protocols of the first accelerator unit and the second accelerator unit are different.
[0014] Furthermore, the communication interface protocol of the first accelerator unit is the APB bus protocol.
[0015] Furthermore, the communication interface protocol of the second accelerator unit is the AXI-Lite bus protocol.
[0016] This invention provides a wireless baseband chip that integrates an accelerator subsystem with other hardware subsystems of the chip to flexibly support wireless baseband processing requirements based on a hardware-software combination strategy. This ensures both high energy efficiency and flexible software scheduling and control capabilities. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 This is a schematic diagram of the structure of a wireless baseband chip provided in one embodiment of the present invention;
[0019] Figure 2 This is a schematic diagram of the architecture of a wireless baseband chip provided in two embodiments of this utility model. Detailed Implementation
[0020] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0021] The technical solution of this utility model will be further described below with reference to the accompanying drawings and specific embodiments.
[0022] Example 1
[0023] Figure 1 This is a schematic diagram of the structure of a wireless baseband chip according to an embodiment of the present invention. As shown in the figure, the wireless baseband chip integrates a processor 11 and a hardware accelerator subsystem 12. The hardware accelerator subsystem includes a DMA transfer controller 13, a storage management unit 14, and multiple accelerator units 15. The DMA transfer controller 13 is communicatively connected to the storage management unit 14. The multiple accelerator units 15 are each communicatively connected to the storage management unit 14. The storage management unit 14 is communicatively connected to the processor 11. The different accelerator units have different functions.
[0024] Specifically, DMA (Direct Memory Access) is a mechanism that bypasses the CPU to transfer data directly between a device and memory. A DMA controller is a unique peripheral that transfers data within a wireless baseband chip; it can be viewed as a controller that connects internal and external memory to each DMA-capable peripheral via a set of dedicated buses. One or more DMA transfer controllers can be configured according to actual needs.
[0025] Specifically, the memory management unit (MMU) provides memory protection and isolation for the accelerator units, offering an independent address space mapping table for each unit, optimizing memory access efficiency, controlling memory access by the accelerator units to ensure they do not interfere with critical data on the chip, and providing interrupt handling, such as handling memory access errors and notifying the processor via interrupts. Simultaneously, the MMU provides overall control over all bus accesses within the accelerator unit, achieving unified access address management. Through the communication connection between the MMU and the processor, information exchange between the processor and the hardware accelerator subsystem is realized. The processor, with its built-in software program, can control the information exchange between the various hardware components in the wireless baseband chip.
[0026] Specifically, accelerator units can be customized as needed, and can be added or removed, ensuring the flexibility and scalability of integrating multiple accelerator units.
[0027] The communication connection between the aforementioned hardware components can be achieved through electrical connection.
[0028] The wireless baseband chip provided in Embodiment 1 of this utility model integrates the accelerator subsystem with other hardware subsystems of the entire chip in a highly efficient manner, so as to flexibly support the wireless baseband processing requirements based on the combination of software and hardware strategies. This ensures both a high energy efficiency ratio and flexible software scheduling and control capabilities.
[0029] Example 2
[0030] The wireless baseband chip in this embodiment is based on the first embodiment and further includes:
[0031] Optionally, the chip may also include other subsystems besides the hardware accelerator subsystem; the wireless baseband chip includes a SOC chip; different subsystems have different functions; the hardware accelerator subsystem communicates with the other subsystems.
[0032] Optionally, the hardware accelerator subsystem also includes an AXI interface; the storage management unit of the hardware accelerator subsystem communicates with the SOC chip through the AXI interface to enable communication between the SOC chip and other subsystems.
[0033] Optionally, the plurality of accelerator units include at least two of the following: a Polar encoder, an LDPC encoder, a Fourier transform, a symbol-level equalization algorithm calculation unit, a Polar decoder, an LDPC decoder, a Cholesky decomposition calculation kernel, and a basic sequence generator.
[0034] Optionally, the hardware accelerator subsystem further includes a shared memory; one end of the shared memory is communicatively connected to the accelerator unit, and the other end is communicatively connected to the storage management unit.
[0035] Optionally, the hardware accelerator subsystem further includes a communication interface; one end of the communication interface is communicatively connected to the accelerator unit, and the other end is communicatively connected to the storage management unit.
[0036] Optionally, the hardware accelerator subsystem further includes a first configuration interface; one end of the first configuration interface is communicatively connected to the first accelerator unit among the plurality of accelerator units, and the other end is communicatively connected to the storage management unit, the DMA transfer controller, and the other subsystems respectively; the configuration interface is used to convert communication interface protocols.
[0037] Optionally, the hardware accelerator subsystem further includes a second configuration interface; one end of the second configuration interface is communicatively connected to the second accelerator unit among the plurality of accelerator units, and the other end is communicatively connected to the other subsystems; the communication interface protocols of the first accelerator unit and the second accelerator unit are different.
[0038] Optionally, the communication interface protocol of the first accelerator unit is the APB bus protocol.
[0039] Optionally, the communication interface protocol of the second accelerator unit is the AXI-Lite bus protocol.
[0040] Figure 2 This is a schematic diagram of the architecture of a wireless baseband chip provided in Embodiment 2 of this utility model. Figure 2 As shown, the wireless baseband chip includes:
[0041] 1) Integration Unit 100: This unit is the integration unit of the hardware accelerator subsystem. This unit is connected to the main bus 300 through bus interface units (200, 201 and 202), thereby supporting interaction with other subsystems such as the processor subsystem, storage subsystem and peripheral subsystem through the main bus 300.
[0042] 2) Bus interface units 200, 201, and 202: This group of units enables the interconnection between the accelerator subsystem and the main bus 300. Multiple units can be flexibly configured according to requirements. The bus interface units can be high-performance AXI interfaces, or modified to other bus interfaces as needed.
[0043] 3) Main bus 300: This is the main bus within the SOC chip. The integrated unit 100 can be connected to the main bus 300 through the bus interface units (200, 201, and 202), thereby enabling the integrated unit 100 to interact with other subsystems.
[0044] 4) DMA transfer controllers 101 and 102: This group of units is a sub-unit within the integrated unit 100, and one or more can be configured according to actual needs.
[0045] 5) Memory Management Unit 103: This unit provides memory protection and isolation for the accelerator units, offers an independent address space mapping table for each accelerator, optimizes memory access efficiency, controls memory access by the accelerator units to ensure they do not interfere with critical system data, and provides interrupt handling, such as handling memory access errors and notifying the processor via interrupts. Simultaneously, the Memory Management Unit 103 enables overall control of access to all buses within the accelerator. Specifically, DMA transfer controllers 101 and 102, bus interface units 200, 201 and 202, communication interface 205, and shared memory 104 are all connected to the Memory Management Unit 103 to achieve unified access address management.
[0046] 6) Shared memory 104: Provided for shared access by all accelerator units within the integrated unit 100. Read and write access to the shared memory 104 can be achieved through a bus interface (e.g., ...). Figure 2 As an example, this can be achieved through an AXI interface connected to the storage management unit 103, enabling each unit connected to the storage management unit 103 to access the shared memory 104.
[0047] 7) Accelerator Units 105, 106, 107, 108, 109, 110, 111, and 112: This group of units includes eight independently functional accelerators, which can be added or removed. The functions of the accelerator units can be designed according to requirements. Unit 105 can be a Polar encoder, unit 106 can be an LDPC encoder, sub-functional unit 107 can be a Fourier transform (such as FFT, IFFT, or DFT), unit 108 can be a symbol-level equalization algorithm computation unit, unit 109 can be a Polar decoder, unit 110 can be an LDPC decoder, unit 111 can be a Cholesky decomposition computation kernel for matrix inversion, and unit 112 can be a basic sequence generator. The specific functions of this group of units can be customized as needed and can be added or removed. The architecture of this chip ensures the flexibility and scalability of integrating multiple functional accelerator units.
[0048] 8) Configuration interfaces 203 and 204: These provide register or parameter configuration interfaces for each unit within integrated unit 100. The software in the processor can achieve switching between different bus interface protocols via the main bus 300 and bus interface unit 200 (or directly from the main bus 300 to configuration interfaces 203 and 204), and then through configuration interfaces 203 and 204. Configuration interfaces 203 and 204 can be flexibly selected according to specific needs. For example, unit 203 can be a bridge module for the AXI to APB protocol, and unit 204 can be a bridge module for the AXI to AXI-Lite protocol, or an AXI to AHB protocol. The selection can be flexible based on the number of registers and parameters transmitted and the configuration delay requirements.
[0049] 9) Communication Interface 205: Enables interconnection between the accelerator unit and the memory management unit 103. Multiple sets of this unit can be flexibly configured as needed. The communication interface 205 can be a high-performance AXI interface, or it can be modified to other bus interfaces as required.
[0050] The wireless baseband chip provided in Embodiment 2 of this utility model efficiently integrates the accelerator subsystem with the processor cluster and other subsystems of the entire chip, and incorporates a flexible hardware accelerator structure. Functions involving high computational demands and high algorithm stability are implemented using hardware logic. By forming the accelerator subsystem, the accelerator subsystem is efficiently integrated with other hardware subsystems of the entire chip to flexibly support the implementation of wireless baseband processing requirements based on a hardware-software combination strategy. This ensures both high energy efficiency and flexible software scheduling and control capabilities, guarantees a certain degree of flexibility in upgrading baseband processing functions, supports good architectural scalability, and reduces the complexity of hardware-software interaction.
Claims
1. A wireless baseband chip, characterized in that, The chip integrates a processor and a hardware accelerator subsystem. The hardware accelerator subsystem includes a DMA transfer controller, a memory management unit, and multiple accelerator units. The DMA transfer controller is communicatively connected to the memory management unit. The multiple accelerator units are each communicatively connected to the memory management unit. The memory management unit is communicatively connected to the processor. The different accelerator units have different functions.
2. The wireless baseband chip according to claim 1, characterized in that, The chip also includes other subsystems besides the hardware accelerator subsystem; the wireless baseband chip includes a SOC chip; different subsystems have different functions; the hardware accelerator subsystem communicates with the other subsystems.
3. The wireless baseband chip according to claim 2, characterized in that, The hardware accelerator subsystem also includes an AXI interface; The storage management unit of the hardware accelerator subsystem communicates with other subsystems in the SOC chip through the AXI interface.
4. The wireless baseband chip according to claim 1, characterized in that, The plurality of accelerator units include at least two of the following: a Polar encoder, an LDPC encoder, a Fourier transform, a symbol-level equalization algorithm computation unit, a Polar decoder, an LDPC decoder, a Cholesky decomposition computation kernel, and a basic sequence generator.
5. The wireless baseband chip according to claim 1, characterized in that, The hardware accelerator subsystem also includes a shared memory; one end of the shared memory is communicatively connected to the accelerator unit, and the other end is communicatively connected to the storage management unit.
6. The wireless baseband chip according to claim 5, characterized in that, The hardware accelerator subsystem also includes a communication interface; one end of the communication interface is connected to the accelerator unit, and the other end is connected to the storage management unit.
7. The wireless baseband chip according to claim 2, characterized in that, The hardware accelerator subsystem also includes a first configuration interface; one end of the first configuration interface is communicatively connected to the first accelerator unit among the plurality of accelerator units, and the other end is communicatively connected to the storage management unit, the DMA transfer controller and the other subsystems respectively; the configuration interface is used to convert the communication interface protocol.
8. The wireless baseband chip according to claim 7, characterized in that, The hardware accelerator subsystem also includes a second configuration interface; one end of the second configuration interface is communicatively connected to the second accelerator unit among the plurality of accelerator units, and the other end is communicatively connected to the other subsystems; the communication interface protocols of the first accelerator unit and the second accelerator unit are different.
9. The wireless baseband chip according to claim 7, characterized in that, The communication interface protocol of the first accelerator unit is the APB bus protocol.
10. The wireless baseband chip according to claim 8, characterized in that, The communication interface protocol of the second accelerator unit is the AXI-Lite bus protocol.